TWI800995B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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Publication number
TWI800995B
TWI800995B TW110143000A TW110143000A TWI800995B TW I800995 B TWI800995 B TW I800995B TW 110143000 A TW110143000 A TW 110143000A TW 110143000 A TW110143000 A TW 110143000A TW I800995 B TWI800995 B TW I800995B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
TW110143000A
Other languages
English (en)
Other versions
TW202301355A (zh
Inventor
中澤新悟
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202301355A publication Critical patent/TW202301355A/zh
Application granted granted Critical
Publication of TWI800995B publication Critical patent/TWI800995B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
TW110143000A 2021-06-21 2021-11-18 半導體記憶裝置 TWI800995B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021102805A JP2023001828A (ja) 2021-06-21 2021-06-21 半導体記憶装置
JP2021-102805 2021-06-21

Publications (2)

Publication Number Publication Date
TW202301355A TW202301355A (zh) 2023-01-01
TWI800995B true TWI800995B (zh) 2023-05-01

Family

ID=84490356

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110143000A TWI800995B (zh) 2021-06-21 2021-11-18 半導體記憶裝置

Country Status (4)

Country Link
US (1) US11929123B2 (zh)
JP (1) JP2023001828A (zh)
CN (1) CN115579034A (zh)
TW (1) TWI800995B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171861B2 (en) * 2013-05-07 2015-10-27 SK Hynix Inc. Semiconductor memory device and system having the same
US10147731B2 (en) * 2014-03-17 2018-12-04 SK Hynix Inc. Semiconductor device
US20200335513A1 (en) * 2019-04-17 2020-10-22 Kioxia Corporation Semiconductor memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9397110B2 (en) 2014-05-21 2016-07-19 Macronix International Co., Ltd. 3D independent double gate flash memory
US9666594B2 (en) 2014-09-05 2017-05-30 Sandisk Technologies Llc Multi-charge region memory cells for a vertical NAND device
KR20160107553A (ko) * 2015-03-04 2016-09-19 에스케이하이닉스 주식회사 반도체 장치
US10269828B2 (en) 2017-03-27 2019-04-23 Toshiba Memory Corporation Semiconductor memory device
JP6948892B2 (ja) 2017-09-19 2021-10-13 キオクシア株式会社 半導体記憶装置
JP2022048489A (ja) 2020-09-15 2022-03-28 キオクシア株式会社 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171861B2 (en) * 2013-05-07 2015-10-27 SK Hynix Inc. Semiconductor memory device and system having the same
US10147731B2 (en) * 2014-03-17 2018-12-04 SK Hynix Inc. Semiconductor device
US20200335513A1 (en) * 2019-04-17 2020-10-22 Kioxia Corporation Semiconductor memory device

Also Published As

Publication number Publication date
US20220406384A1 (en) 2022-12-22
TW202301355A (zh) 2023-01-01
US11929123B2 (en) 2024-03-12
JP2023001828A (ja) 2023-01-06
CN115579034A (zh) 2023-01-06

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