TWI780598B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI780598B
TWI780598B TW110106307A TW110106307A TWI780598B TW I780598 B TWI780598 B TW I780598B TW 110106307 A TW110106307 A TW 110106307A TW 110106307 A TW110106307 A TW 110106307A TW I780598 B TWI780598 B TW I780598B
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Taiwan
Prior art keywords
pad
terminal
bonding wire
bonding
semiconductor memory
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TW110106307A
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English (en)
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TW202209643A (zh
Inventor
佐野雄一
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日商鎧俠股份有限公司
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Publication of TWI780598B publication Critical patent/TWI780598B/zh

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    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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Abstract

本發明之實施形態提供一種電特性提高之半導體裝置。實施形態之半導體裝置具有：基板，其具有第1端子；第1半導體記憶晶片，其設置於基板上，具有第1焊墊；第2半導體記憶晶片，其設置於第1半導體元件上，具有第2焊墊；第1接合線，其連接第1端子與第1焊墊；及第2接合線，其自第1端子上之與第1接合線不同之座標位置連接第1端子與第1焊墊或第2焊墊。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
於先前之將NAND快閃記憶體晶片積層之封裝中，若考慮電特性面，則存在一種藉由使信號與電源配線並行而減少電感，使動作穩定之方法。為了使動作更穩定而強化電源。
本發明之實施形態提供一種電特性提高之半導體裝置。
實施形態之半導體裝置具有：基板，其具有第1端子；第1半導體記憶晶片，其設置於基板上，具有第1焊墊；第2半導體記憶晶片，其設置於第1半導體元件上，具有第2焊墊；第1接合線，其連接第1端子與第1焊墊；及第2接合線，其自第1端子上之與第1接合線不同之座標位置連接第1端子與第1焊墊或第2焊墊。
根據上述構成，可提供一種電特性提高之半導體裝置。
以下，參照圖式對實施形態進行說明。
本說明書中，於若干要件附設有複數種表現例。另，該等表現例僅為例示，並非否定以其它表現來表達上述要件之情況。又，對於未附有複數種表現之要件，亦可以其它表現來表達。
又，圖式係模式圖，有時厚度與平面尺寸之關係或各層之厚度比例等與實際情況不同。又，有時亦包含圖式相互之間彼此之尺寸關係或比例不同之部分。又，於圖式中省略了一部分符號。
(第1實施形態) 第1實施形態係關於一種半導體裝置。圖1顯示半導體裝置100之模式性剖視圖。圖2及圖3顯示半導體裝置100之要部之俯視圖。更具體而言，實施形態之半導體裝置100係搭載有NAND快閃記憶體晶片等之半導體封裝。另，X方向、Y方向及Z方向較佳為彼此交叉且彼此正交。
半導體裝置100係記憶裝置之一例。半導體裝置100包含具有端子之基板1、具有焊墊之半導體記憶晶片2(2A、2B)、第1接合線6、第2接合線7、控制器晶片8、密封材9及焊料球10。
基板1係半導體記憶晶片2之支持基板。更具體而言，基板1係多層配線基板。於基板1之第1面側設置有半導體記憶晶片2。基板1之與第1面對向之第2面側設置有用於與半導體裝置100之外部連接之焊料球10等半球狀電極。
基板1經由接合線與半導體記憶晶片2電性連接。於基板1具有與半導體記憶晶片2連接之端子。端子包含電源用端子、IO(Input/Output：輸入/輸出)用端子、接地用端子及除IO以外之信號用端子等複數種端子，各個端子設置於基板1上。例如，IO用端子係用於半導體記憶晶片2之資料輸入輸出之端子。例如，信號用端子係用於控制半導體記憶晶片2之動作之控制信號輸入用端子，圖2顯示基板1與半導體記憶晶片2之配線之一例。圖2顯示4個端子(3A、3B、3C、3x)。亦可於端子3A與端子3x之間存在複數個端子。於圖2及圖3中，複數根接合線自作為第1端子之端子3A與半導體記憶晶片2連接。
於圖2及圖3中，第1端子3A係電源用端子或接地用端子。於第1端子3為電源用端子時，第2端子3B為接地用端子，第3端子3C為IO用端子。第3端子3C與第1端子3A及第2端子3B相鄰，位於第1端子3A與第2端子3B之間。於第1端子3A為接地用端子之情形時，第2端子3B為電源用端子，第3端子3C為IO用端子。因IO用端子為差動配線用端子之情形亦包含於實施形態中，故於電源用端子與接地用端子之間，設置有1個或2個IO用端子。施加於接地用端子之電壓低於施加於電源用端子之電壓。
半導體記憶晶片2設置於基板1上。半導體記憶晶片2係進行資料之讀寫之半導體晶片。作為非揮發性記憶晶片，可使用NAND記憶晶片、相變記憶晶片、阻變記憶晶片、強介電質記憶晶片、磁性記憶晶片等。作為揮發性記憶晶片，可使用DRAM(DynamicRandom Access Memory：動態隨機存取記憶體)等。半導體記憶晶片2較佳為除個體差異以外皆為同一電路且為同一構造之半導體晶片。又，於本實施形態中，作為半導體記憶晶片2，可使用非揮發性記憶晶片、揮發性記憶晶片。使半導體記憶晶片2於Y方向上偏移且積層之層數，不僅可如圖1般設為2層，亦可設為3層以上，但為了進行高速動作需強化電源，且基於進行高速動作之觀點，如圖1般積層之層數(以第1接合線6A連接之半導體記憶晶片2之數量)較佳為2層。
如圖1所示，於包含複數個半導體記憶晶片2之情形時，半導體記憶晶片2較佳於Y方向上偏移且於Z方向積層。於包含複數個半導體記憶晶片2之情形時，例如圖1等所示，於基板1上設置第1半導體記憶晶片2A，於第1半導體記憶晶片2A上設置有第2半導體記憶晶片2B。
半導體記憶晶片2之間或半導體記憶晶片2與基板1之間較佳以未圖示之接著性樹脂薄膜固定。
半導體記憶晶片2具有作為用於與基板1或其它半導體記憶晶片2連接之端子之焊墊。焊墊包含電源用焊墊、IO用焊墊、接地用焊墊及除IO以外之信號用焊墊等複數種焊墊，分別設置於半導體記憶晶片2上，且與半導體記憶晶片2之配線連接。圖2及圖3顯示基板1與半導體記憶晶片2之配線之一例。於圖2及圖3中，顯示第1半導體記憶晶片2A之4個焊墊(4A、4B、4C、4x)。又，於圖2及圖3中，顯示第2半導體記憶晶片2B之4個焊墊(5A、5B、5C、5x)。亦可於焊墊4A與焊墊4x之間及焊墊5A與焊墊5x之間存在複數個焊墊。於圖2及圖3中，基板1之第1端子3A、第1半導體記憶晶片2A之第1焊墊4A與第2半導體記憶晶片2B之第2焊墊5A經由兩根接合線6、7電性連接。
第1焊墊4A與第1半導體記憶晶片2A之第1配線連接，第2焊墊5A與第2半導體記憶晶片2B之第2配線連接。第1配線及第2配線兩者係電源配線或接地配線中之一者。即，第1焊墊4A及第2焊墊5A兩者係電源用焊墊或接地用焊墊中之一者。
第1半導體記憶晶片2A與第2半導體記憶晶片2B具有共通之記憶體電路，第1半導體記憶晶片2A之第1焊墊4A對應於第2半導體記憶晶片2B之第2焊墊5A，藉此可強化複數個半導體記憶晶片2所共通之電源電路之配線。基於強化電源之觀點，較佳對隔著IO配線之焊墊之電源側焊墊與接地側焊墊兩者使用第2接合線7。IO配線係進行資料輸入輸出之配線，亦可作為信號配線。但，為了形成第2接合線7，必須增大第1端子3A之面積，故藉由對電源側焊墊使用第2接合線7，可有效率且有效果地強化使半導體記憶晶片2動作之電源。
第4焊墊4C與第1焊墊4A及第3焊墊4B相鄰，位於第1焊墊4A與第3焊墊4B之間。第3焊墊4B與第1半導體記憶晶片2A之第3配線連接。第4焊墊4C與第1半導體記憶晶片2A之第4配線連接。且，例如第1配線及第2配線之兩者與第3配線之一者係電源配線，另一者係接地配線，第4配線係IO配線。於第1焊墊4A及第2焊墊5A係電源用焊墊之情形時，第3焊墊4B及焊墊5B係接地用焊墊，第4焊墊4C及焊墊5C係IO用焊墊。此時，第1焊墊4A與第1半導體記憶晶片2A之電源配線連接，第3焊墊4B與第1半導體記憶晶片2A之接地配線連接，第4焊墊4C與第1半導體記憶晶片2A之IO配線連接。且，第2焊墊5A與第2半導體記憶晶片2B之電源配線連接，焊墊5B與第2半導體記憶晶片2B之接地配線連接，焊墊5C與第2半導體記憶晶片2B之IO配線連接。又，若第1焊墊4A及第2焊墊5A為接地用焊墊，則第3焊墊4B及焊墊5B為電源用焊墊，第4焊墊4C為IO用焊墊。此時，第1焊墊4A與第1半導體記憶晶片2A之接地配線連接，第3焊墊4B與第1半導體記憶晶片2A之電源配線連接，第4焊墊4C與第1半導體記憶晶片2A之IO配線連接。且，第2焊墊5A與第2半導體記憶晶片2B之接地配線連接，焊墊5B與第2半導體記憶晶片2B之電源配線連接，焊墊5C與第2半導體記憶晶片2B之IO配線連接。因IO用焊墊為差動配線用焊墊之情形亦包含於實施形態中，故於電源用焊墊與接地用焊墊之間，設置有1個或2個IO用焊墊。
基板1之端子3與半導體記憶晶片2之焊墊4、5由複數根接合線電性連接。接合線6與基板及第1半導體記憶晶片2A及第2半導體記憶晶片2B兩者連接。第1接合線6A將基板1之第1端子3A與第1半導體記憶晶片2A之第1焊墊4A連接。第2接合線7與基板1之第1端子3A及第1半導體記憶晶片2A之第1焊墊4A或第2半導體記憶晶片2B之第2焊墊5A連接。
於圖2及圖3中，基板1之第1端子3A、第1半導體記憶晶片2A之第1焊墊4A及第2半導體記憶晶片2B之第2焊墊5A經由第1接合線6A連接。第3接合線與基板1之第2端子3B及第1半導體記憶晶片2A之第3焊墊連接。第4接合線6C將基板1之第3端子3C與第1半導體記憶晶片2A之第4焊墊4C連接。於圖2及圖3中，基板1之第2端子3B、第1半導體記憶晶片2A之第3焊墊4B及第2半導體記憶晶片2B之焊墊5B經由第3接合線6B連接。 於圖2及圖3中，基板1之第3端子3C、第1半導體記憶晶片2A之第4焊墊4C及第2半導體記憶晶片2B之焊墊5C經由第4接合線6C連接。於圖2中，基板1之第1端子3A及第2半導體記憶晶片2B之第2焊墊5A經由第2接合線7連接。於圖3中，基板1之第1端子3A及第1半導體記憶晶片2A之第1焊墊4A經由第2接合線7連接。又，基板1之端子3x、第1半導體記憶晶片2A之焊墊4x及第2半導體記憶晶片2B之焊墊5x經由接合線6x連接。
第2接合線7自基板1之第1端子3A上與第1接合線6A不同之座標位置連接第1端子3A與第1焊墊4A或第2焊墊5。第2接合線7係不連接半導體記憶晶片2之間之配線。第2接合線7與第1接合線6A並行，第1接合線6A與連接於第1端子3A之第1焊墊4A及第2焊墊5A之任一者連接。第2接合線7與第1接合線6A相同，以第1端子3A為起點朝半導體記憶晶片2延伸。因第1接合線6A與第2接合線7於第1端子3A上未重疊，故第1端子3A上之第1接合線6A之起點之X-Y座標與第2接合線7之X-Y座標不同。
第1接合線6A與第2接合線7自1個端子即第1端子3A延伸。若自2個端子分別形成第1接合線6A與第2接合線7，則因於基板1中佔據之面積增加，故而欠佳。若為與其它端子相同程度之面積，則難以形成複數根接合線。又，若第1端子3A之面積較其它端子過大，則於基板1上獨佔較大面積，而會對其它接合線之形成造成影響。
基於降低接合線之配線電阻及電感且強化電源之觀點，較佳使用第1接合線6A與第2接合線7。
接合線之配線電阻與電感對半導體記憶晶片2之動作之影響於半導體記憶晶片2之動作速度為高速之情形時變大。例如，較佳採用以下構成：對於與以500 MHz以上高速動作之IO配線連接之焊墊相鄰之電源用焊墊或接地用焊墊併用實施形態之第1接合線6A與第2接合線7。若動作速度為1000 MHz以上，則因電源之影響增大，故較佳採用以下構成：對於與此種要求高速動作之IO配線連接之焊墊相鄰之電源用焊墊或接地用焊墊併用實施形態之第1接合線6A與第2接合線7。
若半導體記憶晶片2變為多層，則於配線變長之上層側，阻抗容易上升，因此較佳使第2接合線7連接於半導體記憶晶片2之上層側。
若第1接合線6A與第2接合線7並行連接，則第1接合線6A與第2接合線7形成電路環路。藉由形成電路環路，可強化第1半導體記憶晶片2A與第2半導體記憶晶片2B之對應之配線之電源。
基於配線空間之觀點，第2接合線7較佳藉由與上層側之第2半導體記憶晶片2B連接而容易製作。因於下層側之第1半導體記憶晶片2A之焊墊4上形成自基板1延伸之接合線6，進而形成朝第2半導體記憶晶片2B延伸之接合線6，故若較第2半導體記憶晶片2B更靠下層側之第1半導體記憶晶片2A連接第2接合線7，則有線連接之可靠性降低之情形。因此，第2接合線7較佳與上層側之第2半導體記憶晶片2B側之第2焊墊5連接。
又，第4接合線6C之形狀較佳與相鄰之第1接合線6A及第3接合線6B不同，當接合線形狀不同時，因接合線彼此之干擾變少，故而較佳。為了改變接合線之形狀，列舉改變接合方法之技術。 例如，於形成第4接合線6C時，以正向接合形成接合線。即，藉由球形接合與縫合式接合，自半導體記憶晶片2側朝基板1形成環路而形成接合線。因此，正向接合之情形時，於晶片側殘留凸塊，於基板側殘留縫合痕跡。 於形成相鄰之第1接合線6A或第3接合線6B時，進行反向接合。首先，於半導體記憶晶片2側形成凸塊。其後，藉由球形接合與縫合接合，自基板1朝半導體記憶晶片2側形成環路且形成接合線。因此，於基板側殘留凸塊，於半導體晶片側之凸塊上殘留縫合之痕跡。 藉由刻意改變接合線高度，亦可改變接合線之形狀。若接合線之長度變長，則配線電阻與電感容易變高，因而較佳以避免接合線高度變得過高之方式改變接合線之形狀。例如，只要將第1接合線6A或第3接合線6B之最大高度形成得較高，且於接合線6C中降低最大高度即可。又，亦可與之相反。 又，實施形態之接合線6、7可採用具有凸塊之接合線，亦可採用楔形接合中鏈上不間斷之線。 若接合線6A為反向接合，則接合線7可設為正向接合。若接合線6A為正向接合，則接合線7可設為反向接合。 正向接合與反向接合中，接合線達到最大高度之場所不同。正向接合中達到最大高度之場所較反向接合者距晶片更近。
控制器晶片8係控制半導體記憶晶片2之讀寫及抹除等之半導體晶片。控制器晶片8之位置除圖1所示之位置外，亦可設置於半導體記憶晶片2之上方或下方。控制器晶片8以未圖示之配線與基板1連接，且與半導體記憶晶片2電性連接。
密封材9密封半導體記憶晶片2、接合線6、7及控制器晶片8。密封材9係例如鑄模樹脂。
焊料球10係與半導體裝置100之外部電性連接之端子。
(第2實施形態) 第2實施形態係關於一種半導體裝置。第2實施形態係第1實施形態之半導體裝置100之變化例。圖4顯示第2實施形態之半導體裝置200之剖視模式圖。圖5顯示半導體裝置200之要部之俯視圖。第2實施形態與第1實施形態之半導體裝置100之不同在於，將第2半導體記憶晶片2B反轉設置於第1半導體記憶晶片2A上，於第1半導體記憶晶片2A與第2半導體記憶晶片2B中，分別自基板1之1個端子之不同座標位置具有兩根接合線。對於第1實施形態與第2實施形態中共通之內容，省略其說明。
於第1實施形態中，第1半導體記憶晶片2A與第2半導體記憶晶片2B以相同方向於Y方向上偏移且積層，但於第2實施形態中，使第2半導體記憶晶片2B與第1半導體記憶晶片2A旋轉180°而於Y方向上偏移且積層。因第1半導體記憶晶片2A與第2半導體記憶晶片2B具有共通之記憶體電路，較佳為同一電路晶片，故於如第2實施形態般使半導體記憶晶片2旋轉180°而配置之情形時，基於電源強化之觀點，較佳對兩個半導體記憶晶片2同樣採用強化電源之構成。
因第1半導體記憶晶片2A與第2半導體記憶晶片2B反轉，故即使接合線6朝第2半導體記憶晶片2B側延伸，亦無法連接於第1半導體記憶晶片2A與第2半導體記憶晶片2B所共通之配線，故第2半導體記憶晶片2B亦以來自基板1之接合線12、13連接基板1與第2半導體記憶晶片2B。
第1實施形態中，第2接合線7與第2半導體記憶晶片2B連接，但於第2實施形態中，第2接合線7與第1半導體記憶晶片2A之第1焊墊4A連接。
於基板1，除端子3外，並設置有端子11(11A、11B、11C、11D)。基板1上之端子11經由接合線12、13而與第2半導體記憶晶片2B之焊墊5連接。基板1之端子11除位置反轉外，皆與端子相同。
於圖5中，基板1之第4端子11A、第2半導體記憶晶片2A之第2焊墊5A經由第5接合線12A連接。於圖5中，基板1之端子11B、第2半導體記憶晶片2B之焊墊5B經由接合線12B連接。於圖5中，基板1之端子11C、第2半導體記憶晶片2B之焊墊5C經由接合線12C連接。於圖5中，基板1之第4端子11A及第2半導體記憶晶片2B之第2焊墊5A經由第6接合線13連接。較佳由第2接合線7與第6接合線13強化第1半導體記憶晶片2A與第2半導體記憶晶片2B共通之電路之電源。
(第3實施形態) 第3實施形態係關於一種半導體裝置。第3實施形態係第1實施形態之半導體裝置100之變化例。圖6顯示第3實施形態之半導體裝置300之剖視模式圖。第3實施形態與第1實施形態之半導體裝置100之不同在於，將控制器晶片8設置於下部，且將積層2層半導體記憶晶片2之積層體以旋轉180°而相向之方式配置於控制器晶片8上。對於第1實施形態與第3實施形態中共通之內容，省略其說明。
於第3實施形態中，控制器晶片8由DAF等接著性樹脂組成物14覆蓋。於接著性樹脂組成物14上，以旋轉180°而與由第1半導體記憶晶片2A與第2半導體記憶晶片2B積層之積層體相向之方式，設置有由第3半導體記憶晶片2C與第4半導體記憶晶片2D積層之積層體。由第1半導體記憶晶片2A與第2半導體記憶晶片2B積層之積層體及由第3半導體記憶晶片2C與第4半導體記憶晶片2D積層之積層體，除旋轉180°外皆相同。
基板1之端子3形成有與圖6左側之第1半導體記憶晶片2A及第2半導體記憶晶片2B連接之接合線6、7。另一方面，於基板1之與端子3側為相反之側設置有端子15。自基板1之端子15設置有與第3半導體記憶晶片2C之焊墊18及第4半導體記憶晶片2D之焊墊19連接之接合線18、19。接合線18與第1接合線6對應。接合線19與第2接合線7對應。接合線18與第3半導體記憶晶片2C及第4半導體記憶晶片2D之兩者連接，接合線19與相當於第2半導體記憶晶片2B之第2焊墊5A之第4半導體記憶晶片2D之焊墊17連接。接合線19與第2接合線7對應。接合線19相當於由第2接合線7電性連接之第1半導體記憶晶片2A及第2半導體記憶晶片2B之例如電源配線，且可與第3半導體記憶晶片2C及第4半導體記憶晶片2D電性連接而強化電源。
於如第3實施形態之半導體裝置300般具備複數個積層體之情形時，亦可與第1實施形態同樣地降低配線之電阻與電感。
第3實施形態之半導體裝置300使用較第1實施形態之半導體裝置100更多之半導體記憶晶片2，因謀求於高速動作之方面較為有利之電源強化，故兼顧高速動作與大電容。
(第4實施形態) 第4實施形態係關於一種半導體裝置。第4實施形態係第1實施形態之半導體裝置100、第2實施形態之半導體裝置200及第3實施形態之半導體裝置300之變化例。圖7顯示第4實施形態之半導體裝置400之剖視模式圖。於第4實施形態中，與第1實施形態之半導體裝置100至第3實施形態之半導體裝置300之不同在於如下配置：與第3實施形態同樣將控制器晶片8設置於下部，使2層之半導體記憶晶片2積層於控制器晶片8上，進而積層反轉後之2層之半導體記憶晶片2。對於第1實施形態至第3實施形態與第4實施形態中共通之內容，省略其說明。
於第3實施形態之半導體裝置300中，圖6左右兩側之半導體記憶晶片2之2層之積層體以按照相同之高度相向之方式設置於接著性樹脂組成物14上，但於第4實施形態之半導體裝置400中，將旋轉180°後之第3半導體記憶晶片2C及第4半導體記憶晶片2D之積層體設置於第1半導體記憶晶片2A與第2半導體記憶晶片2B之積層體上。該半導體裝置400之形態亦為第2實施形態之半導體裝置200之形態之變化例。
若使第3半導體記憶晶片2C與第4半導體記憶晶片2D以按照與第2半導體記憶晶片2B相同之方向於Y方向上偏移之方式積層，則變為4層之積層體，基於高速動作之觀點，較佳將積層且以1根接合線連接之半導體記憶晶片2之層數設為2層。若積層之半導體記憶晶片2之數量增加，則接合線之線長變長，配線之電阻與電感變大，基於高速動作之觀點欠佳。
第4實施形態之半導體裝置400使用較第2實施形態之半導體裝置200更多之半導體記憶晶片2，謀求於高速動作方面較為有利之電源強化，因而兼顧高速動作與大電容。
其它實施形態 (a)如圖8所示，可具備連接第2端子3B與焊墊4B之兩根接合線。再者，亦可具備連接焊墊4B與焊墊5B之兩根接合線。此時，當第1端子3A為電源用端子時，第2端子3B為接地用端子，當第1端子3A為接地用端子時，第2端子3B為電源用端子。端子3C為信號用端子。又，雖未圖示，但可於基板1中與所有用於IO輸入輸出之信號用端子相鄰配置有電源用端子或接地用端子。於半導體晶片2A、2B中，亦可與所有輸入輸出用信號焊墊相鄰配置有電源焊墊或接地焊墊。可於所有之該等電源焊墊、接地焊墊，各設2根如上述實施形態所示之用於電源強化之接合線。 (b)如圖9所示，當存在第1半導體晶片之IO輸入輸出用信號焊墊4C時，與其相鄰之電源用或接地用焊墊為4A、4B。與連接焊墊4C之第2半導體晶片之焊墊5C相鄰之電源用或接地用焊墊為5A、5B。如此，存在與某信號焊墊及與其連接之信號焊墊相鄰之複數個電源用焊墊或複數個接地用焊墊。 此時，相鄰之複數個電源用焊墊中之至少1者亦可以來自電源用端子之接合線強化，相鄰之複數個接地用焊墊中之至少1者亦可以來自接地用端子之接合線強化。 例如對於焊墊5A，自第1端子(設為電源用端子)3A以線接合強化電壓。對於焊墊4B，自第2端子3B(設為接地用端子)以線接合強化電壓。然而，對於4A、5B，未自基板直接強化電源。 即，只要與某信號焊墊及與其連接之信號焊墊相鄰之複數個電源焊墊之至少1者在與電源用端子之間形成電路環路即可。只要與某信號焊墊及與其連接之信號焊墊相鄰之複數個接地焊墊之至少1者在與接地用端子之間形成電路環路即可。又，若將第1端子設為基板，則基板與複數個電源焊墊中之至少1者以線接合形成環路。又，若將第3端子設為基板，則基板與複數個接地焊墊中之至少1者以線接合形成環路。
以上，雖已對本發明之若干實施形態進行說明，但該等實施形態係作為例子而提示者，並未意圖限定發明之範圍。該等新穎的實施形態可以其它各種形態實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變化例包含於發明之範圍及主旨，且包含於專利申請範圍所記載之發明及與其均等之範圍內。
相關申請案之引用 本申請案基於2020年08月28日提出申請之先前之日本專利申請案第2020-144745號之優先權而主張優先權利益，且藉由引用將其全部內容包含於本文中。
1:基板 2A:半導體記憶晶片 2B:半導體記憶晶片 2C:第3半導體記憶晶片 2D:第4半導體記憶晶片 3:端子 3A:端子 3B:端子 3C:端子 3x:端子 4:焊墊 4A:第1焊墊 4B:第3焊墊 4C:第4焊墊 4x:焊墊 5:焊墊 5A:第2焊墊 5B:焊墊 5C:焊墊 5x:焊墊 6:第1接合線 6A:第1接合線 6B:第3接合線 6C:第4接合線 6x:接合線 7:第2接合線 8:控制器晶片 9:密封材 10:焊料球 11:端子 11A:第4端子 11B:端子 11C:端子 12:接合線 12A:第5接合線 12B:接合線 12C:接合線 13:接合線 14:接著性樹脂組成物 15:端子 17:焊墊 18:接合線 19:接合線 100:半導體裝置 200:半導體裝置 400:半導體裝置
圖1係實施形態之半導體裝置之模式性剖視圖。 圖2係實施形態之半導體裝置之俯視圖。 圖3係實施形態之半導體裝置之俯視圖。 圖4係實施形態之半導體裝置之模式性剖視圖。 圖5係實施形態之半導體裝置之俯視圖。 圖6係實施形態之半導體裝置之模式性剖視圖。 圖7係實施形態之半導體裝置之模式性剖視圖。 圖8係實施形態之半導體裝置之模式性剖視圖。 圖9係實施形態之半導體裝置之模式性剖視圖。
1:基板
2A:半導體記憶晶片
2B:半導體記憶晶片
3:端子
4:焊墊
5:焊墊
6:第1接合線
7:第2接合線
8:控制器晶片
9:密封材
10:焊料球
100:半導體裝置

Claims (10)

  1. 一種半導體裝置，其具備：基板，其設置有第1端子；第1半導體晶片，其設置於上述基板上，具有第1焊墊；第2半導體晶片，其設置於上述第1半導體晶片上，具有第2焊墊；第1接合線，其連接上述第1端子與上述第1焊墊；第2接合線，其連接上述第1焊墊與上述第2焊墊；及第3接合線，其連接上述基板與上述第1焊墊或第2焊墊；其中上述基板設置有第2端子及第3端子，上述第3端子設置於上述第1端子與上述第2端子之間；上述第1半導體晶片設置有第3焊墊及第4焊墊，上述第4焊墊設置於上述第1焊墊與上述第3焊墊之間；上述半導體裝置進而具有連接上述第2端子與上述第3焊墊之第4接合線、及連接上述第3端子與上述第4焊墊之第5接合線；上述第1焊墊與上述第1半導體晶片之第1配線連接；上述第2焊墊與上述第2半導體晶片之第2配線連接；上述第3焊墊與上述第1半導體晶片之第3配線連接；上述第4焊墊與上述第1半導體晶片之第4配線連接；上述第1配線及上述第2配線、與上述第3配線之一者為電源配線，另一者為接地配線；上述第4配線係信號配線。
  2. 如請求項1之半導體裝置，其中上述第5接合線之形狀與相鄰之上述第1接合線及上述第4接合線不同。
  3. 如請求項2之半導體裝置，其中上述第2半導體晶片設置有第5焊墊；且上述半導體裝置具備連接上述基板與上述第3焊墊或第5焊墊之第6接合線。
  4. 如請求項3之半導體裝置，其中上述第6接合線之一端部連接於上述第2端子。
  5. 如請求項3之半導體裝置，其具備連接上述第3焊墊與上述第5焊墊之第7接合線；上述基板與上述第1焊墊或第2焊墊形成環路；上述基板與上述第3焊墊或第5焊墊形成環路。
  6. 如請求項2之半導體裝置，其中上述第5接合線達到最大高度之處，較相鄰之上述第1接合線及上述第4接合線更靠近晶片側，或者，上述第5接合線達到最大高度之處，較相鄰之上述第1接合線及上述第4接合線距晶片側更遠。
  7. 如請求項2之半導體裝置，其中上述第5接合線以正向接合形成，且上述第1接合線及上述第4接合線以反向接合形成，或者，上述第5接合線 以反向接合形成，且上述第1接合線及上述第4接合線以正向接合形成。
  8. 一種半導體裝置，其具備：基板，其設置有第1端子；第1半導體晶片，其設置於上述基板上，具有第1焊墊；第2半導體晶片，其設置於上述第1半導體晶片上，具有第2焊墊；第1接合線，其連接上述第1端子與上述第1焊墊；第2接合線，其連接上述第1焊墊與上述第2焊墊；及第3接合線，其連接上述基板與上述第1焊墊或第2焊墊；其中上述基板設置有上述第2端子及第3端子，上述第3端子設置於上述第1端子與上述第2端子之間；上述第1半導體晶片設置有第3焊墊及第4焊墊，上述第4焊墊設置於上述第1焊墊與上述第3焊墊之間；上述半導體裝置進而具有連接上述第2端子與上述第3焊墊之第4接合線、及連接上述第3端子與上述第4焊墊之第5接合線；上述第1端子與上述第3端子之一者可施加第1電壓，另一者可施加低於第1電壓之第2電壓；可對上述第2端子施加將資料輸入輸出之信號。
  9. 如請求項1至8中任一項之半導體裝置，其中上述第3接合線之一端部連接於上述第1端子。
  10. 如請求項1至8中任一項之半導體裝置，其中上述第1焊墊與上述第1 半導體晶片之第1配線連接；上述第2焊墊與上述第2半導體晶片之第2配線連接；上述第1配線及第2配線兩者係電源配線或接地配線中之一者。
TW110106307A 2020-08-28 2021-02-23 半導體裝置 TWI780598B (zh)

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