TWI825373B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI825373B
TWI825373B TW109145245A TW109145245A TWI825373B TW I825373 B TWI825373 B TW I825373B TW 109145245 A TW109145245 A TW 109145245A TW 109145245 A TW109145245 A TW 109145245A TW I825373 B TWI825373 B TW I825373B
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Taiwan
Prior art keywords
bonding wire
pad
mentioned
pads
bonding
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TW109145245A
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English (en)
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TW202145521A (zh
Inventor
佐野努
丸山一哉
高久悟
鈴谷信人
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日商鎧俠股份有限公司
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Publication of TW202145521A publication Critical patent/TW202145521A/zh
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Publication of TWI825373B publication Critical patent/TWI825373B/zh

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Abstract

實施方式之半導體裝置具有：基板，其設置有第1端子、第2端子、及複數個第3端子；1個以上之半導體記憶體晶片，其等具有複數個第1墊、複數個第2墊、及複數個第3墊；第1接合線，其將第1端子與複數個第1墊電性連接；第2接合線，其將第2端子與複數個第2墊電性連接；複數條第3接合線，其等將複數個第3端子與複數個第3墊電性連接；第4接合線，其跨複數條第3接合線中之至少1條，於複數個第1墊上與第1接合線連接；或/及第5接合線，其跨複數條第3接合線中之至少1條，於複數個第2墊上與第2接合線連接。

Description

半導體裝置
本發明之實施方式係關於一種半導體裝置。
於積層有NAND(與非)快閃記憶體晶片之先前之半導體裝置(封裝)中，考慮到電氣特性，存在藉由使信號與電源之配線並排配置來降低電感並使動作穩定之方法。為了進一步使動作穩定化，而增加包含接地配線之電源之配線等來強化電源。
本發明之實施方式提供一種電氣特性得以提高之半導體裝置。
實施方式之半導體裝置具有：基板，其設置有第1端子、第2端子、及複數個第3端子；1個以上之半導體記憶體晶片，其等具有複數個第1墊、複數個第2墊、及複數個第3墊；第1接合線(bonding wire)，其將第1端子與複數個第1墊電性連接；第2接合線，其將第2端子與複數個第2墊電性連接；複數條第3接合線，其等將複數個第3端子與複數個第3墊電性連接；第4接合線，其跨複數條第3接合線中之至少1條，於複數個第1墊上與第1接合線連接；或/及第5接合線，其跨複數條第3接合線中之至少1條，於複數個第2墊上與第2接合線連接。
根據上述構成，能夠提供一種電氣特性得以提高之半導體裝置。
以下，參照圖式對實施方式進行說明。
於本說明書中，對幾個要素附加複數個表達方式之示例。再者，該等表達方式之示例僅為例示，不否定上述要素可藉由其他表達方式來表達。又，對於未附加複數個表達方式之要素，亦可藉由其他表達方式來表達。
又，圖式為示意圖，存在厚度與平面尺寸之關係或各層之厚度之比率等與實物不同之情形。又，圖式相互之間亦可能包含彼此之尺寸關係或比率不同之部分。又，於圖式中省略一部分符號。
(第1實施方式)第1實施方式係關於一種半導體裝置。將半導體裝置100之模式性剖視圖示於圖1。將半導體裝置100之主要部分之放大立體概念圖示於圖2。更具體而言，實施方式之半導體裝置100係搭載有NAND快閃記憶體晶片等之半導體封裝。再者，X方向、Y方向及Z方向較佳為彼此交叉且彼此正交。
半導體裝置100係記憶裝置之一例。半導體裝置100具有基板1、半導體記憶體晶片2(2A、2B、2C、2D、2E)、第1接合線9(9A、9B、9C)、第2接合線10(10A、10B、10C)、第3接合線11(11A、11B、11C、11D、11E)、第4接合線12(12A、12B、12C)、第5接合線13(13A、13B)、控制器晶片21、密封材料22及焊球23。
基板1係半導體記憶體晶片2之支持基板。更具體而言，基板1係多層之配線基板。於基板1之第1面側設置有半導體記憶體晶片2。於基板1中之與第1面對向之第2面側，設置有用以與半導體裝置100之外部進行連接之焊球23等半球狀電極。
基板1經由接合線而與半導體記憶體晶片2電性連接。基板1設置有作為與半導體記憶體晶片2連接之「第1端子」之電源墊6(6A、6B、6C)、作為「第2端子」之電源墊7(7A、7B、7C)及作為「第3端子」之信號用墊8(8A、8B、8C、8D、8E)。電源墊6、電源墊7及信號用墊8於X方向上排列。雖省略了圖示，但較佳為於基板1上進而設置有與半導體記憶體晶片2等電性連接之墊。電源墊6具有第1基準電位。電源墊7具有第2基準電位。
1個以上之半導體記憶體晶片2設置於基板1上。半導體記憶體晶片2係進行資料讀寫之半導體晶片。作為非揮發性記憶體晶片，可使用NAND記憶體晶片、相變記憶體晶片、阻變記憶體晶片、鐵電記憶體晶片、磁性記憶體晶片等。作為揮發性記憶體晶片，可使用DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)等。於包含2個以上半導體記憶體晶片2之情形時，較佳為除個體差異以外為同一電路且為同一結構之半導體晶片。又，於本實施方式中，可使用非揮發性記憶體晶片、揮發性記憶體晶片作為半導體記憶體晶片2。
如圖1所示，於包含2個以上半導體記憶體晶片2之情形時，半導體記憶體晶片2較佳為一面於Y方向上錯開一面於Z方向上積層。於包含複數個半導體記憶體晶片2之情形時，例如，如圖1等所示，自基板1側起依次積層有半導體記憶體晶片2A、半導體記憶體晶片2B、半導體記憶體晶片2C、半導體記憶體晶片2D及半導體記憶體晶片2E。
較佳為於半導體記憶體晶片2之間或半導體記憶體晶片2與基板1之間藉由未圖示之接著性樹脂膜進行固定。
半導體記憶體晶片2A具有複數個作為「第1墊」之第1電源墊3(3A、3B、3C)、複數個作為「第2墊」之第2電源墊4(4A、4B、4C)、及複數個作為「第3墊」之信號用墊5(5A、5B、5C、5D、5E)。第1電源墊3、第2電源墊4及信號用墊5於X方向上排列。於半導體記憶體晶片2中，除第1電源墊3、第2電源墊4及信號用墊5以外亦具有其他墊，但省略其說明及圖示。關於半導體記憶體晶片2B、2C、2D、2E，於自Z方向觀察時與半導體晶片2A之第1電源墊(3A、3B、3C)在X方向上大致相同之位置處分別具有第1電源墊3(3A、3B、3C)。
關於半導體記憶體晶片2B、2C、2D、2E，於自Z方向觀察時與半導體晶片2A之第2電源墊4(4A、4B、4C)在X方向上大致相同之位置處分別具有第2電源墊4(4A、4B、4C)。關於半導體記憶體晶片2B、2C、2D、2E，於自Z方向觀察時與半導體晶片2A之信號用墊5(5A、5B、5C、5D、5E)在X方向上大致相同之位置處分別具有信號用墊5(5A、5B、5C、5D、5E)。
經由第1電源墊3、第2電源墊4向半導體記憶體晶片2施加電壓。施加至第1電源墊3之第1基準電位為負電位、接地電位或正電位之任一種。施加至第2電源墊4之第2基準電位為負電位、接地電位或正電位之任一種。第1電源墊3較佳為與半導體記憶體晶片2之接地配線或驅動半導體記憶體晶片2之各種電路之電源配線連接。又，若第1電源墊3連接於接地配線，則第2電源墊4較佳為連接於電源配線，若第1電源墊3連接於電源配線，則第2電源墊4較佳為連接於接地配線。施加至電源配線之電壓例如存在Vcc、VccQ、Vpp三種電源電壓。電源電壓Vcc係由動作電源通常自外部供給之電路電源電壓，例如輸入3.3 V左右之電壓。電源電壓VccQ例如輸入1.2 V之電壓。電源電壓VccQ於收發半導體記憶體晶片2之信號時使用。電源電壓Vpp係高於電源電壓Vcc之電源電壓，例如輸入12 V之電壓。施加至接地配線之電壓Vss為接地電位，例如為0 V。又，信號用墊5較佳為與半導體記憶體晶片2之信號之I/O(Input/Output，輸入輸出)用配線連接。
複數個信號用墊5設置於第1電源墊3彼此之間、第2電源墊4彼此之間、第1電源墊3與第2電源墊4之間之任一位置。藉由以隔著信號用墊5之方式配置電源墊，能夠提高半導體裝置100之動作速度。雖然信號用墊5可以連續地排列2個之方式進行配置，但考慮到半導體裝置100之動作特性，與信號用墊5相鄰之墊之至少1個墊、更具體而言信號用墊5左右之任一個或兩個墊較佳為第1電源墊或第2電源墊。
第1接合線9(9A、9B、9C)以如下方式設置複數條：自基板1側朝著複數個第1電源墊3之各墊平行地排列並延伸，且將基板1與複數個第1電源墊3電性連接。自Z方向觀察時，第1接合線9於Y方向上延伸。圖2中，基板1上之電源墊6A與半導體記憶體晶片2A之第1電源墊3A經由第1接合線9A連接。電源墊6B與第1電源墊3B經由第1接合線9B連接。電源墊6C與第1電源墊3C經由第1接合線9C連接。
圖1之半導體裝置100中，第1接合線9A將積層成5層之半導體記憶體晶片2(2A～2E)之第1電源墊3A與基板1上之電源墊6A連接。又，第1接合線9B將積層成5層之半導體記憶體晶片2(2A～2E)之第1電源墊3B與基板1上之電源墊6B連接。又，第1接合線9C將積層成5層之半導體記憶體晶片2(2A～2E)之第1電源墊3C與基板1上之電源墊6C連接。
第2接合線10(10A～10C)以如下方式設置複數條：自基板1側朝著複數個第2電源墊4之各墊平行地排列並延伸，且將基板1與複數個第2電源墊4電性連接。自Z方向觀察時，第2接合線10於Y方向上延伸。圖1中，基板1上之電源墊7A與半導體記憶體晶片2A之第2電源墊4A經由第2接合線10A連接。電源墊7B與第2電源墊4B經由第2接合線10B連接。電源墊7C與第2電源墊4C經由第2接合線10C連接。
圖1之半導體裝置100中，第2接合線10A將積層成5層之半導體記憶體晶片2(2A～2E)之第2電源墊4A與基板1上之電源墊7A連接。又，第2接合線10B將積層成5層之半導體記憶體晶片2(2A～2E)之第2電源墊4B與基板1上之電源墊7B連接。又，第2接合線10C將積層成5層之半導體記憶體晶片2(2A～2E)之第2電源墊4C與基板1上之電源墊7C連接。
第3接合線11(11A～11E)以如下方式設置複數條：自基板1側朝著複數個信號用墊5之各墊平行地排列並延伸，且將基板1與複數個信號用墊5電性連接。自Z方向觀察時，第3接合線11於Y方向上延伸。圖1中，基板1上之信號用墊8A與半導體記憶體晶片2A之信號用墊5A經由第3接合線11A連接。信號用墊8B與信號用墊5B經由第3接合線11B連接。信號用墊8C與信號用墊5C經由第3接合線11C連接。信號用墊8D與信號用墊5D經由第3接合線11D連接。信號用墊8E與信號用墊5E經由第3接合線11E連接。
電源墊6為第1基準電位。電源墊7為第2基準電位。電源墊6之第1基準電位經由第1接合線9傳輸至第1電源墊3。電源墊7之第2基準電位經由第2接合線10傳輸至第2電源墊4。
圖1之半導體裝置100中，第3接合線11A將積層成5層之半導體記憶體晶片2(2A～2E)之信號用墊5A與基板1上之電源墊8A連接。第3接合線11B將積層成5層之半導體記憶體晶片2(2A～2E)之信號用墊5B與基板1上之電源墊8B連接。第3接合線11C將積層成5層之半導體記憶體晶片2(2A～2E)之信號用墊5C與基板1上之電源墊8C連接。第3接合線11D將積層成5層之半導體記憶體晶片2(2A～2E)之信號用墊5D與基板1上之電源墊8D連接。第3接合線11E將積層成5層之半導體記憶體晶片2(2A～2E)之信號用墊5E與基板1上之電源墊8E連接。
連接形態並不限定於圖1之形態，實施方式中亦包含如下形態等：於基板與任意半導體記憶體晶片2之間設置再配線層，再配線層上之墊與半導體記憶體晶片2之第1電源墊3(3A～3C)經由第1接合線9(9A～9C)連接。
平行排列之接合線之延伸角度之差可為不與相鄰之接合線發生短路之程度，例如可存在±3°以內之偏差。
當配線長度變長時，會使電源電感增加。於積層有複數個半導體記憶體晶片2之情形時，配線長度變得更長，使得電源阻抗之Q值上升，而導致響應性變差。因此，第1接合線9、第2接合線10及第3接合線11較佳為不使用凸塊而與各墊連接。藉由採用無凸塊之配線，能夠縮短配線長度。
根據上述觀點，第1接合線9較佳為於所連接之複數個第1電源墊3上不中斷之線。根據相同觀點，第2接合線10較佳為於所連接之複數個第2電源墊4上不中斷之線。根據相同觀點，第3接合線11較佳為於所連接之複數個信號用墊5上不中斷之線。該結構係藉由楔形焊接(wedge bonding)而非球形焊接所實現，上述楔形焊接係藉由將線壓接於墊電極，使線之第1端接合於墊而不熔融，上述球形焊接係使熔融成球狀之接合線之第1端與墊接合。當利用楔形焊接形成鏈狀且不中斷之線時，該線與墊之接合部分成為平面形狀。可進一步藉由楔形焊接或球形焊接將線連接於平面形狀之部分，因此就形成下述第4接合線12(12A、12B、12C)及第5接合線13(13A、13B)之觀點而言，第1接合線9及第2接合線10較佳為藉由楔形焊接而形成之接合線。第4接合線12與第5接合線13較佳為藉由楔形焊接而形成之接合線。
藉由採用無球狀體(凸塊)之配線，使得第1接合線9與第1電源墊3直接連接，第2接合線10與第2電源墊4直接連接，第3接合線11與信號用墊5直接連接。由於接合線與墊之間未介置球狀體，因此能夠縮短配線長度。
第4接合線12A將半導體晶片2A之第1電源墊3A、第1電源墊3B及第1電源墊3C之間連接起來。第4接合線12B將半導體晶片2C之第1電源墊3A、第1電源墊3B及第1電源墊3C之間連接起來。第4接合線12C將半導體晶片2E之第1電源墊3A、第1電源墊3B及第1電源墊3C之間連接起來。第4接合線12跨第2接合線10與第3接合線11，於第1電源墊3上與第1接合線9連接，從而能夠降低第1基準電位之電感。
第5接合線13A將半導體晶片2B之第2電源墊4A、第2電源墊4B及第2電源墊4C之間連接起來。第5接合線13B將半導體晶片2D之第2電源墊4A、第2電源墊4B及第2電源墊4C之間連接起來。第5接合線13跨第1接合線9與第3接合線11，於第2電源墊4上與第2接合線10連接，從而能夠降低第2基準電位之電感。
自Z方向觀察時，第4接合線12及第5接合線13係於X方向上延伸之配線。由於接合線之配線較半導體記憶體晶片2內之第1基準電位及第2基準電位電路之配線更粗，因此就降低電源之Q值之觀點而言，較佳為藉由第4接合線12及第5接合線13來降低電感。
將表示半導體裝置之配線形態之概念圖示於圖3。第1接合線9、第2接合線10及第3接合線11與重疊之墊電性連接或直接連接。關於第4接合線12及第5接合線13之連接，係於黑色圓點之部分與重疊之接合線電性連接或直接連接。第4接合線12之配線中，無黑色圓點之部分跨第2接合線10及第3接合線11。第5接合線12之配線中，無黑色圓點之部分跨第1接合線9及第3接合線11。
以垂直於基板1且與第1接合線9之延伸方向平行之剖面之概念圖之形式，將半導體裝置100之配線形態之一例示於圖4。藉由楔形焊接形成第1至第5所有之接合線。於半導體記憶體晶片2上之第1電源墊3上形成之第1接合線9之與第1電源墊3之連接部中，存在大致平坦之平坦面(第1上表面)，於該平坦面上形成有第4接合線12，第1接合線9與第4接合線12於第1上表面處連接。又，於半導體記憶體晶片2上之第2電源墊4上形成之第2接合線10之與第2電源墊4之連接部中，存在大致平坦之平坦面(第2上表面)，於該平坦面上形成有第5接合線13，第2接合線10與第5接合線13於第2上表面處連接。
以垂直於基板1且垂直於第1接合線9之延伸方向之剖面之概念圖之形式，將配線形態之一例示於圖5。如圖5所示，以與半導體記憶體晶片2上之第1電源墊3上形成之第1接合線9上之平坦面接合之方式設置有第4接合線12。
就縮短配線長度之觀點而言，較佳為利用第4接合線12與第1電源墊3夾住第1接合線，即，第1接合線9位於第1電源墊3與第4接合線12之間。若增大第1電源墊3，並於第1電源墊3上之不同位置處與第1接合線9及第4接合線12連接，則配線長度會隨著第1電源墊3上之第1接合線9與第4接合線12之距離而相應地變長。就縮短配線長度之觀點而言，第4接合線12較佳為不使用凸塊而連接於第1接合線9上。藉由採用不使用凸塊之配線，使得第1接合線9與第4接合線12直接連接。由於第1接合線9與第4接合線12直接連接，因此能夠縮短經由第4接合線12之配線長度。
當第4接合線12與第1接合線9交叉時，可利用1條第4接合線12連接3條以上之第1接合線9。例如，由於第4接合線12A與3條第1接合線9連接，因此於第1電源墊3B上，第4接合線12中之第4接合線12A與第1接合線9B交叉。藉由改變第4接合線12之長度，能夠於不使配線結構複雜化之情形時，利用1條第4接合線12連接複數條第1接合線9，從而能夠有效地降低電源之Q值。
對於第4接合線12與第5接合線13，可僅使用任一條，但更佳為使用第4接合線12與第5接合線13兩者。由於第3接合線11係信號用配線，因此無需形成繞過第3接合線11之接合線。
就縮短配線長度之觀點而言，較佳為利用第5接合線13與第2電源墊4夾住第2接合線，即，第2接合線10位於第2電源墊4與第5接合線13之間。若增大第2電源墊4，並於第2電源墊4上之不同位置處與第2接合線10及第5接合線13連接，則配線長度會隨著第2電源墊4上之第2接合線10與第5接合線13之距離而相應地變長。就縮短配線長度之觀點而言，第5接合線13較佳為不使用凸塊而連接於第2接合線10上。藉由採用不使用凸塊之配線，使得第1接合線9與第4接合線12直接連接。由於第1接合線9與第4接合線12直接連接，因此能夠縮短經由第4接合線12之配線長度。
當第5接合線13與第2接合線10交叉時，可利用1條第5接合線13連接3條以上之第2接合線10。例如，由於第5接合線13A與3條第2接合線10連接，因此於第2電源墊4B上，第5接合線13中之第5接合線13A與第2接合線10B交叉。藉由改變第5接合線13之長度，能夠於不使配線結構複雜化之情形時利用1條第5接合線13連接複數條第2接合線10，從而能夠有效地降低電源之Q值。
對於第4接合線12與第5接合線13，可僅使用任一條，但更佳為使用第4接合線12與第5接合線13兩者。
控制器晶片22係控制半導體記憶體晶片2之讀寫及抹除等之半導體晶片。
密封材料22將半導體記憶體晶片2、第1～第5接合線9～13及控制器晶片21密封。密封材料22例如為塑模樹脂。
焊球23係與半導體裝置100之外部進行電性連接之端子。
藉由至少於一處使用第4接合線12或第5接合線13，能夠降低電源之Q值，從而可謀求電源之強化。藉由於複數個部位使用第4接合線12或第5接合線13，能夠進一步降低電源之Q值，從而可謀求電源之強化。
當半導體記憶體晶片2成為多級時，於配線變長之上級側阻抗容易上升，因此較佳為於半導體記憶體晶片2之上級側設置第4接合線12或/及第5接合線13。更佳為於複數個半導體記憶體晶片2之所有半導體記憶體晶片2設置第4接合線12或/及第5接合線13。
(第2實施方式)第2實施方式係關於一種半導體裝置。第2實施方式係第1實施方式之半導體裝置100之變化例。將表示第2實施方式之半導體裝置之配線形態之概念圖示於圖6。第2實施方式中，與第1實施方式之半導體裝置100之不同之處在於，第4接合線12連接於不同之半導體記憶體晶片2之第1電源墊3。對於第1實施方式與第2實施方式中共通之內容，省略其說明。
第2實施方式中，第4接合線12A將半導體晶片2B之第1電源墊3A、半導體晶片2A之電源墊3B、及半導體晶片2A之電源墊3C連接。換言之，沿著X方向將不同之半導體晶片2之間連接起來。藉此，能夠提高第4接合線12及第5接合線13之配線佈局之自由度。
第5接合線13亦可與第4接合線12同樣地，於不同之半導體記憶體晶片2之間，沿著X方向連接第2電源墊4。
(第3實施方式)第3實施方式係關於一種半導體裝置。第3實施方式係第1實施方式之半導體裝置100之變化例。將表示第3實施方式之半導體裝置之配線形態之概念圖示於圖7。第3實施方式中，與第1實施方式之半導體裝置100之不同之處在於，第4接合線12C連接於基板1上之電源墊14，第5接合線13B連接於基板1上之電源墊15。對於第1實施方式與第3實施方式中共通之內容，省略其說明。
由於第4接合線12C及第5接合線13B與基準電位之電源連接，因此能夠進一步使電位穩定化。電源墊14具有第1基準電位，電源墊15具有第2基準電位。例如，當於電源墊14、15之正下方或正下方附近設置與第1基準電位或第2基準電位之電源連接之焊球23時，能夠進一步縮短電源配線之配線長度，從而成為就降低電源之Q值之觀點而言更佳之構成。
(第4實施方式)第4實施方式係關於一種半導體裝置。第4實施方式係第1實施方式之半導體裝置100之變化例。將表示第4實施方式之半導體裝置之配線形態之概念圖示於圖8。第4實施方式中，與第1實施方式之半導體裝置100之不同之處在於，半導體記憶體晶片2為1層，第4接合線12與第5接合線13並排配置。對於第1實施方式與第4實施方式中共通之內容，省略其說明。
於1個半導體記憶體晶片2中，亦可使第4接合線12與第5接合線13並排配置。藉由採用本構成，能夠高密度地將第4接合線12與第5接合線13配線，從而有助於降低電源之Q值。第4實施方式中，較佳為採用能夠縮短配線長度之楔形焊接。
亦可於具有複數個半導體記憶體晶片2之半導體裝置中，使第4接合線12與第5接合線13並排配置。
(第5實施方式)第5實施方式係關於一種半導體裝置。第5實施方式係第3實施方式之半導體裝置100之變化例。將表示第5實施方式之半導體裝置之配線形態之概念圖示於圖9。第5實施方式中，省略了基板1上之信號用墊8之間之電源墊。對於第3實施方式與第5實施方式中共通之內容，省略其說明。
藉由省略基板1上之信號用墊8旁邊之電源墊，能夠消除回程線路(return path)。當存在回程線路時，相互之間電感增大，因此可藉由採用第5實施方式之構成來進一步強化電源。進而，就減少基板1上之信號用墊8周圍之配線，使得配線之自由度提高之方面而言，也是以第5實施方式之構成之半導體裝置較佳。
以上，對本發明之幾個實施方式進行了說明，但該等實施方式係作為示例而提出者，並不意圖限定發明之範圍。該等新穎之實施方式可藉由其他各種形態來實施，且可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施方式及其變化例包含於發明之範圍及主旨中，並包含於申請專利範圍中記載之發明及其均等之範圍內。  [相關申請案之引用]
本申請案基於2020年03月13日提出申請之先前之日本專利申請案第2020-043946號之優先權而主張優先權利益，藉由引用將其全部內容併入本文中。
1:基板2,2A,2B,2C,2D,2E:半導體記憶體晶片3,3A,3B,3C:第1電源墊4,4A,4B,4C:第2電源墊5,5A,5B,5C,5D,5E:信號用墊6A,6B,6C:電源墊7A,7B,7C:電源墊8A,8B,8C,8D,8E:信號用墊9,9A,9B,9C:第1接合線10,10A,10B,10C:第2接合線11,11A,11B,11C,11D,11E:第3接合線12,12A,12B,12C:第4接合線13,13A,13B:第5接合線14:電源墊15:電源墊21:控制器晶片22:密封材料23:焊球100:半導體裝置
圖1係實施方式之半導體裝置之模式性剖視圖。  圖2係實施方式之半導體裝置之立體概念圖  圖3係實施方式之半導體裝置之配線概念圖。  圖4係表示實施方式之半導體裝置之配線形態之概念圖。  圖5係表示實施方式之半導體裝置之配線形態之概念圖。  圖6係實施方式之半導體裝置之配線概念圖。  圖7係實施方式之半導體裝置之配線概念圖。  圖8係實施方式之半導體裝置之配線概念圖。  圖9係實施方式之半導體裝置之配線概念圖。
1:基板
2A,2B,2C,2D,2E:半導體記憶體晶片
9:第1接合線
10:第2接合線
11:第3接合線
12A,12B,12C:第4接合線
13A,13B:第5接合線
21:控制器晶片
22:密封材料
23:焊球
100:半導體裝置

Claims (10)

  1. 一種半導體裝置，其具備：基板，其設置有第1端子、第2端子、及複數個第3端子；複數個半導體晶片，其等包含複數個第1墊、複數個第2墊、及複數個第3墊；第1接合線，其將上述第1端子與上述複數個第1墊電性連接；第2接合線，其將上述第2端子與上述複數個第2墊電性連接；複數條第3接合線，其等將上述複數個第3端子與上述複數個第3墊電性連接；及第4接合線，其跨上述複數條第3接合線中之至少1條，於上述複數個第1墊上與上述第1接合線連接，或/及第5接合線，其跨上述複數條第3接合線中之至少1條，於上述複數個第2墊上與上述第2接合線連接；其中，上述第4接合線或/及上述第5接合線所跨之上述複數條第3接合線中之至少1條線係設置在上述第1接合線與上述第2接合線之間，上述複數條第3接合線中之其餘各者分別設置於鄰近上述第1接合線或上述第2接合線。
  2. 如請求項1之半導體裝置，其中設置複數個上述第1端子，設置複數個上述第2端子，設置複數條上述第1接合線，設置複數條上述第2接合線。
  3. 如請求項1之半導體裝置，其中上述第1接合線於較上述第4接合線更靠近上述半導體晶片之位置處連接於上述第1墊，上述第2接合線於較上述第5接合線更靠近上述半導體晶片之位置處連接於上述第2墊。
  4. 如請求項1之半導體裝置，其中上述複數條第1接合線與上述複數個第1墊直接連接，上述複數條第2接合線與上述複數個第2墊直接連接，上述複數條第3接合線與上述複數個第3墊直接連接，上述複數條第1接合線與上述第4接合線直接連接，上述複數條第2接合線與上述第5接合線直接連接。
  5. 如請求項1之半導體裝置，其中上述複數條第1接合線係於所連接之上述複數個第1墊上不中斷之線，上述複數條第2接合線係於所連接之上述複數個第1墊上不中斷之線。
  6. 如請求項1之半導體裝置，其中上述複數個第1墊與上述半導體晶片之接地配線連接，上述複數個第2墊與上述半導體晶片之電源配線連接。
  7. 如請求項2至6中任一項之半導體裝置，其中上述半導體晶片積層2個以上，上述複數條第1接合線、上述複數條第2接合線及上述複數條第3接合線將上述積層有2個以上之半導體記憶體晶片電性連接。
  8. 如請求項1至6中任一項之半導體裝置，其中上述第1接合線於其與上述第1墊之連接部處具有大致平坦之第1上表面，且與上述第4接合線於上述第1上表面處連接；或/及上述第2接合線於其與上述第2墊之連接部處具有大致平坦之第2上表面，且與上述第5接合線於上述第1上表面處連接。
  9. 如請求項1之半導體裝置，其中上述半導體晶片於周緣部依次配置第一個上述第1墊、第一個上述第3墊、第一個上述第2墊、第二個上述第3墊、第二個上述第1墊、第三個上述第3墊、第二個上述第2墊，上述第4接合線將上述第一個上述第1墊與上述第二個上述第1墊連接，及/或上述第5接合線將上述第一個上述第2墊與上述第二個上述第2墊連接。
  10. 如請求項9之半導體裝置，其中於上述基板依次配置第一個上述第1端子、第一個上述第3端子、第一個上述第2端子、第二個上述第3端子、第二個上述第1端子、第三個上 述第3端子、第二個上述第2端子，第一條上述第1接合線將第一個上述第1端子與上述第一個上述第1墊連接，第二條上述第1接合線將第二個上述第1端子與上述第二個上述第1墊連接，第一條上述第2接合線將第一個上述第2端子與上述第一個上述第2墊連接，第二條上述第2接合線將第二個上述第2端子與上述第二個上述第2墊連接，第一條上述第3接合線將第一個上述第3端子與上述第一個上述第3墊連接，第二條上述第3接合線將第二個上述第3端子與上述第二個上述第3墊連接，第三條上述第3接合線將第三個上述第3端子與上述第三個上述第3墊連接。
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987357A (en) * 1997-07-30 1999-11-16 Intermedics Inc. Stackable microelectronic components with self-addressing scheme
US6621105B2 (en) * 2001-04-18 2003-09-16 Oki Data Corporation Array of light-emitting elements with multilayer wiring
US20080088005A1 (en) * 2006-10-16 2008-04-17 Powertech Technology Inc. SIP package with small dimension
US20090091043A1 (en) * 2007-06-18 2009-04-09 Nguk Chin Lai Die offset die to die bonding
US20090273096A1 (en) * 2008-05-05 2009-11-05 Super Talent Electronics, Inc. High Density Memory Device Manufacturing Using Isolated Step Pads
US20110068449A1 (en) * 2009-09-24 2011-03-24 Kook Joong-Kyo Semiconductor package and method of manufacturing the semiconductor package
TW201112384A (en) * 2009-09-24 2011-04-01 Powertech Technology Inc Multi-chip stacked device without loop height and its manufacturing method
US20120080806A1 (en) * 2010-10-05 2012-04-05 In-Sang Song Semiconductor package
US20140027919A1 (en) * 2012-07-30 2014-01-30 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
TW201418151A (zh) * 2012-11-08 2014-05-16 Ind Tech Res Inst 氫氣回收系統與發電系統
TW201440197A (zh) * 2013-02-27 2014-10-16 Invensas Corp 具有堅固晶片結構的微電子封裝
US20160093599A1 (en) * 2014-03-18 2016-03-31 Renesas Electronics Corporation Semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4052697B2 (ja) 1996-10-09 2008-02-27 富士通株式会社 信号伝送システム、および、該信号伝送システムのレシーバ回路
JP2005085829A (ja) 2003-09-05 2005-03-31 Renesas Technology Corp 半導体装置
JP2007134486A (ja) 2005-11-10 2007-05-31 Toshiba Corp 積層型半導体装置及びその製造方法
JP4707548B2 (ja) 2005-12-08 2011-06-22 富士通セミコンダクター株式会社 半導体装置、及び半導体装置の製造方法
JP2008311589A (ja) * 2007-06-18 2008-12-25 Kawasaki Microelectronics Kk 半導体集積回路およびその製造方法
US7696631B2 (en) * 2007-12-10 2010-04-13 International Business Machines Corporation Wire bonding personalization and discrete component attachment on wirebond pads
KR20100109243A (ko) * 2009-03-31 2010-10-08 삼성전자주식회사 반도체 패키지
CN103098206A (zh) * 2010-03-18 2013-05-08 莫塞德技术公司 具有偏移裸片叠层的多芯片封装及其制造方法
KR20150122273A (ko) 2011-05-18 2015-10-30 샌디스크 세미컨덕터 (상하이) 컴퍼니, 리미티드 워터폴 와이어 본딩
KR102108325B1 (ko) * 2013-10-14 2020-05-08 삼성전자주식회사 반도체 패키지
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
KR102365682B1 (ko) * 2017-11-13 2022-02-21 삼성전자주식회사 반도체 패키지

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987357A (en) * 1997-07-30 1999-11-16 Intermedics Inc. Stackable microelectronic components with self-addressing scheme
US6621105B2 (en) * 2001-04-18 2003-09-16 Oki Data Corporation Array of light-emitting elements with multilayer wiring
US20080088005A1 (en) * 2006-10-16 2008-04-17 Powertech Technology Inc. SIP package with small dimension
US20090091043A1 (en) * 2007-06-18 2009-04-09 Nguk Chin Lai Die offset die to die bonding
US20090273096A1 (en) * 2008-05-05 2009-11-05 Super Talent Electronics, Inc. High Density Memory Device Manufacturing Using Isolated Step Pads
US20110068449A1 (en) * 2009-09-24 2011-03-24 Kook Joong-Kyo Semiconductor package and method of manufacturing the semiconductor package
TW201112384A (en) * 2009-09-24 2011-04-01 Powertech Technology Inc Multi-chip stacked device without loop height and its manufacturing method
US20120080806A1 (en) * 2010-10-05 2012-04-05 In-Sang Song Semiconductor package
US20140027919A1 (en) * 2012-07-30 2014-01-30 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
TW201418151A (zh) * 2012-11-08 2014-05-16 Ind Tech Res Inst 氫氣回收系統與發電系統
TW201440197A (zh) * 2013-02-27 2014-10-16 Invensas Corp 具有堅固晶片結構的微電子封裝
US20160093599A1 (en) * 2014-03-18 2016-03-31 Renesas Electronics Corporation Semiconductor device

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