TWI775319B - 半導體封裝件 - Google Patents

半導體封裝件 Download PDF

Info

Publication number
TWI775319B
TWI775319B TW110105758A TW110105758A TWI775319B TW I775319 B TWI775319 B TW I775319B TW 110105758 A TW110105758 A TW 110105758A TW 110105758 A TW110105758 A TW 110105758A TW I775319 B TWI775319 B TW I775319B
Authority
TW
Taiwan
Prior art keywords
wiring pattern
solder bumps
semiconductor package
semiconductor
solder
Prior art date
Application number
TW110105758A
Other languages
English (en)
Other versions
TW202145475A (zh
Inventor
金玹植
申承桓
權容台
徐東勳
金熙喆
李東洙
Original Assignee
韓商Ｎｅｐｅｓ股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 韓商Ｎｅｐｅｓ股份有限公司 filed Critical 韓商Ｎｅｐｅｓ股份有限公司
Publication of TW202145475A publication Critical patent/TW202145475A/zh
Application granted granted Critical
Publication of TWI775319B publication Critical patent/TWI775319B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)

Abstract

本發明涉及一種半導體封裝件。本發明的一實施例的半導體封裝件包括：半導體晶片，在一面配置至少一個晶片焊盤；布線圖案，配置在所述半導體晶片的上部，並且至少一部分與所述晶片焊盤接觸，以與所述晶片焊盤電連接；及焊錫凸塊，配置在所述布線圖案的外面上，以通過所述布線圖案與所述晶片焊盤電連接。

Description

半導體封裝件
本發明涉及半導體封裝件，更詳細地說涉及可縮短工藝的半導體封裝件。
通常，針對在晶片執行各種半導體工藝製造的半導體晶片執行半導體封裝工藝來製造半導體封裝件。近來，為了節省半導體封裝件的生產成本，在晶片級執行半導體封裝工藝，將經過半導體封裝工藝的晶片級的半導體封裝件以單個單位個別化的晶片級封裝(Wafer Level Package)技術。
這種半導體封裝件通過在半導體封裝件的外側凸出形成的外部連接端子貼裝於基板。具體地說，在半導體晶片上形成絕緣層的鈍化(passivation)工藝之後形成布線圖案，接着反覆執行用於形成絕緣層的鈍化工藝。另外，在每個鈍化工藝後面都跟着形成可暴露半導體晶片的至少一部分的開口部來電連接晶片焊盤和布線圖案的工藝。
然而，因為如此反覆的鈍化工藝和布線圖案連接工藝，存在增加成本及時間的問題。所以，處於需要改善該問題可縮短工藝的半導體封裝件的實情。
為了解決如上所述的以往的技術問題，本發明的一實施例提供一種可省略一部分的鈍化及布線圖案連接工藝的半導體封裝件。
另外，本發明的一實施例提供一種將結構及工藝簡單化的 同時提高電連接的半導體封裝件。
用於解決上述課題的本發明的一實施例的半導體封裝件包括：半導體晶片，在一面配置至少一個晶片焊盤；布線圖案，配置在所述半導體晶片的上部，並且至少一部分與所述晶片焊盤接觸，以與所述晶片焊盤電連接；及焊錫凸塊，配置在所述布線圖案的外面上，以通過所述布線圖案與所述晶片焊盤電連接。
本發明的另一實施例的半導體封裝件包括：半導體晶片，在一面配置至少一個晶片焊盤；布線圖案，配置在所述半導體晶片的上部，並且至少一部分與所述晶片焊盤接觸，以與所述晶片焊盤電連接；焊錫凸塊，配置在所述布線圖案的外面上，以通過所述布線圖案與所述晶片焊盤電連接；PCB基板，與所述焊錫凸塊的上部電連接；及底部填充料，在所述半導體晶片和所述PCB基板之間形成的空間填充，以包圍所述布線圖案和所述焊錫凸塊。
此時，所述布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸；其中，相對於所述焊錫凸塊的線寬，所述引導部的線寬可以是1%至15%。
此時，所述布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸；其中，所述凸出凸起從所述焊錫凸塊凸出的長度可以是0.1um至20um。
此時，所述布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸；其中，所述焊錫凸塊在中心 部可包括芯球。
此時，所述布線圖案形成墊片形狀。所述布線圖案包括：多個狹縫，貫通所述布線圖案，並且相互間隔，包圍所述焊錫凸塊的下部；內側空間部，支撐所述焊錫凸塊，並且配置在所述多個狹縫的內側；及外側空間部，配置在所述多個狹縫的外側；其中，在所述多個狹縫之間形成至少一個通道，以使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起；相對於所述焊錫凸塊的線寬，所述至少一個通道的線寬總和可以是1%至15%。
此時，所述半導體封裝件還包括絕緣圖案，所述絕緣圖案配置在所述半導體晶片的上部，並且配置成使所述晶片焊盤的至少一部分暴露。所述布線圖案為配置在所述絕緣圖案上部，並且至少一部分與所述晶片焊盤的暴露的一部分接觸，以與所述晶片焊盤電連接；在所述布線圖案的所述外面中，除了配置有所述焊錫凸塊的部分以外的至少一部分可形成有機被膜層，所述有機被膜層包含與通過與所述布線圖案的材料的化學反應生成的氧化層或者與所述布線圖案的材料選擇性結合的有機化合物。
此時，所述半導體晶片以上面一部分開放的狀態被密封部掩埋，所述布線圖案可配置在所述半導體晶片和所述密封部的上部。
此時，在所述晶片焊盤的上部配置導電柱，所述半導體晶片在配置所述導電柱的狀態下被密封部掩埋，所述布線圖案可配置在所述密封部的上部，配置成與所述導電柱電連接。
此時，在所述布線圖案的側面和所述布線圖案的上面中除了與所述焊錫凸塊接觸的部分以外的部分可與底部填充料接觸。
此時，所述布線圖案的下側面和所述底部填充料的至少一部分可配置在同一平面上。
本發明的其他一實施例的半導體封裝件包括：絕緣體；上部布線圖案，配置在所述絕緣體上；下部布線圖案，配置在所述絕緣體下部的下部；連接布線圖案，配置在所述絕緣體內部，並且連接所述上 部布線圖案和所述下部布線圖案；半導體晶片，包括晶片焊盤，所述晶片焊盤配置在所述絕緣體上部並且與所述上部布線圖案電連接；及焊錫凸塊，配置在所述下部布線圖案的外面上，以與所述半導體晶片電連接。
此時，所述下部布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸；其中，相對於所述焊錫凸塊的線寬，所述引導部的線寬為1%至15%，所述凸出凸起從所述焊錫凸塊凸出的長度為0.1um至20um，所述焊錫凸塊在中心部可包括芯球。
如上述構成的本發明的一實施例的半導體封裝件為具有空間性孤立焊錫凸塊且只以設計流動方向開放一部分的結構的布線圖案，進而沒有另外的工藝也可有效保持焊錫凸塊的球形狀。
另外，本發明的一實施例的半導體封裝件為在布線圖案形成氧化層或者有機被膜層來代替附加的鈍化，進而可縮短半導體封裝件製造工藝。
另外，本發明的一實施例的半導體封裝件為包括焊錫凸塊內特有的芯球，進而可更加有效保持焊錫凸塊的球形狀。
100、200、300、400、500:半導體封裝件
10:PCB基板
110:半導體晶片
111:晶片焊盤
112:導電柱
130:絕緣圖案
131:第一絕緣層
132:第二絕緣層
140:布線圖案
140a、140b:布線圖案
140a’:第一布線圖案
140a”:第二布線圖案
141:孤立部
142:引導部
143:狹縫
144:內側空間部
145:外側空間部
146:通道
150:氧化層
152:掩膜圖案
160:外部連接端子(焊錫凸塊)
161:芯球
162:凸出凸起
170:有機被膜層
180:密封部
190:底部填充料
510:半導體芯片
511:晶片焊盤
513:焊錫
530:絕緣體
540:下部布線圖案
550:上部布線圖案
560:焊錫凸塊
570:布線圖案
L1、L2:線寬
圖1是示出本發明的一實施例的半導體封裝件的剖面的圖。
圖2是示出本發明的另一實施例的半導體封裝件的剖面的圖。
圖3a至圖3f作為用於依次說明本發明的一實施例的半導體封裝件的製造方法的圖，是按各步驟示出半導體封裝件的剖面的圖。
圖4a至圖4g作為用於依次說明本發明的另一實施例的半導體封裝件的製造方法的圖，是按各步驟示出半導體封裝件的剖面的圖。
圖5是示出本發明的第三實施例的半導體封裝件的剖面的圖。
圖6至圖8是示出在本發明的各種實施例的半導體封裝件適用的布線圖案的一示例的圖。圖6右上方所示的截面圖是沿圖6左圖中線A-A截取的截面圖，圖6右下方所示的截面圖是沿圖6左圖中線B-B截取的截面圖。
圖9及圖10是示出在本發明的各種實施例的半導體封裝件適用的布線圖案的另一示例的圖。圖9右上方所示的截面圖是沿圖9左圖中線A-A截取的截面圖，圖9右下方所示的截面圖是沿圖9左圖中線B-B截取的截面圖。
圖11是示出本發明的第四實施例的半導體封裝件的剖面的圖。
圖12是示出本發明的各種實施例的半導體封裝件貼裝於PCB基板的狀態的剖面。
圖13及圖14是示出本發明的各種實施例的半導體封裝件適用於FOWLP工序的狀態的圖。
圖15是示出本發明的第五實施例的半導體封裝件的剖面的圖。
以下，參照附圖詳細說明本發明的實施例，以使在本發明所屬技術領域中具有常規知識的人可容易實施。本發明可由各種不同的形狀實現，不限於在此說明的實施例。為了明確說明本發明，在附圖中省略與說明無關的部分，並且在說明書全文中對於相同或者類似的構成元素賦予相同的附圖標記。
在本說明書中，對於「包括」或者「具有」等的用語，應該理解為是要指定在說明書上記載的特徵、數字、步驟、動作、構成元素、零部件或者這些的組合的存在，並不提前排除一個或者一個以上的其他特徵或者數字、步驟、動作、構成元素、零部件或者這些的組合的存在或者附加可能性。
作為本發明的各種實施例的半導體封裝件的各個構成元素層疊的方向的z軸方向稱為「第一方向」，作為垂直於z軸的平面方向的x軸方向或者y軸方向稱為「第二方向」。另外，對於本發明的各種實施例的半導體封裝件的各個構成元素，將第一方向(z軸方向)的長度稱為該構成元素的「厚度」、「深度」或者「高度」，將第二方向(x軸方向及y軸方向)的各個長度稱為該構成元素的「寬度」。
圖1是示出本發明的一實施例的半導體封裝件的剖面的圖。圖2是示出本發明的另一實施例的半導體封裝件的剖面的圖。
如圖1及圖2所示，本發明的第一及第二實施例的半導體封裝件100、200可包括半導體晶片110、絕緣圖案130、布線圖案140、氧化層150及外部連接端子160。
半導體晶片110作為半導體元件，可包括各種種類的一個或者多個個別元件。例如，多個個別元件可包括微電子元件(microelectronic devices)、CMOS晶體管(complementary metalinsulatorsemiconductor transistor，互補金屬氧化物半導體晶體管)、MOSFET(metal-oxidesemiconductor field effect 39-9 2019-09-20 transistor，金屬-氧化物半導體場效應晶體管)、系統LSI(large scale integration，大規模集成化)、CIS(CMOS imaging sensor)等的光電元件、MEMS(micro-electro-mechanical system，微機電系統)、聲波濾波器元件、能動元件、手動元件等，但是不限於此。
半導體晶片110可以是存儲器半導體晶片。例如，存儲器半導體晶片可以是諸如DRAM(Dynamic Random Access Memory，動態隨機存儲器)或者SRAM(Static Random Access Memory，靜 態隨機存儲器)的易失性存儲器，或者諸如PRAM(Phase-change Random Access Memory，相變隨機存儲器)、MRAM(Magneto-resistive Random Access Memory磁阻隨機存儲器)、FeRAM(Ferroelectric Random Access Memory，鐵電隨機存儲器)或者RRAM(Resistive Random Access Memory阻變式隨機存儲器)的非易失性存儲器的半導體晶片，但是不限於此。
半導體晶片110也可以是邏輯晶片。例如，邏輯晶片可以是CPU(Central Processor Unit，中央處理單元)、MPU(Micro Processor Unit，微處理單元)、GPU(Graphic Processor Unit，圖形處理單元)或者AP(Application Processor，應用處理器)，但是不限於此。
在圖1等示出了半導體封裝件100、200包括一個半導體晶片110，但是半導體封裝件100、200也可包括多個半導體晶片110。半導體封裝件100、200包括的多個半導體晶片110可舉例相同種類的半導體晶片，也可以舉例不同種類的半導體晶片。另外，半導體封裝件100、200可以是相互電連接不同種類的半導體晶片以作為一個單一的系統運行的系統級封裝件(system in package,SIP)。
半導體晶片110的寬度可以是約2mm至約10mm。更具體地說，半導體晶片110的寬度可以是約4mm至約7mm。但是，半導體晶片110的寬度不限於此，而是可具有更加多樣的值。另外，半導體晶片110的厚度可以是約100μm至約400μm。更具體地說，半導體晶片110的厚度可以是約150μm至約350μm。但是，半導體晶片110的厚度不限於此，而是可具有更加多樣的值。
半導體晶片110可包括第一面和與第一面相對的第二面。在半導體晶片110的第一面可形成晶片焊盤111。晶片焊盤111可與形成在半導體晶片110的各種種類的多個個別元件電連接。晶片焊盤111可具有約0.5μm至約1.5μm之間的厚度。但是，晶片焊盤111的厚度不限於此，而是也可具有更加多樣的值。
晶片焊盤111可輸出/入半導體晶片110的輸出/入信號。即，晶片焊盤111與半導體晶片110的集成電路電連接，進而可向外部擴張半導體晶片110的功能。例如，晶片焊盤111可由諸如鋁、銅的低電阻金屬構成，但是不限於此。在圖1等示出了2個晶片焊盤111，但是晶片焊盤111個數不限於此，而是個數可以更多。
絕緣圖案130作為包含非導電性材料的結構，配置在半導體晶片110的第一面上保護半導體晶片110，可防止不必要的電短路。
此時，絕緣圖案130也可用絕緣性聚合物、環氧膠(epoxy)、氧化矽膜、氮化矽膜(SiN)或者這些的組合構成。或者，絕緣圖案130分別可用非光敏性物質或者光敏性物質構成。
此時，絕緣性聚合物可包含諸如PMMA(Polymethylmethacrylate，聚甲基丙烯酸甲酯)、PS(Polystylene，聚苯乙烯)、PBO(Polybenzoxazoles，聚苯并
Figure 110105758-A0305-02-0009-1
唑)等常規的通用聚合物、丙烯酸類聚合物、醯亞胺類聚合物(聚醯亞胺(PI，polyimide))、芳醚類聚合物、醯胺類聚合物、氟類聚合物、對二甲苯類聚合物、乙烯醇類聚合物、具有苯酚組的聚合物衍生物或者這些的組合等。
但是，在圖1及圖2的情況下，示出了絕緣圖案130包含聚醯亞胺(PI)或者氮化矽膜(SiN)，但是絕緣圖案130的材料當然不限於在附圖示出的，也不限於上述的示例，而是可用更加多樣的物質構成。
另一方面，絕緣圖案130也可具有層疊多個絕緣層的結構。即，如圖2所示，在本發明的第一及第二實施例的半導體封裝件200中，絕緣圖案130可包括依次層疊的第一絕緣層131及第二絕緣層132。舉一示例，包括：配置在半導體晶片110的第一面上並且用氮化矽膜(SiN)形成的第一絕緣層131；及配置在第一絕緣層131上並且用聚醯亞胺(PI，Polyimide)形成的第二絕緣層132。
布線圖案140作為包含導電性物質的結構，能夠以第一 方向及第二方向傳輸晶片焊盤111或者外部裝置(例如，基板)等電信號。即，布線圖案140電連接於半導體晶片110的晶片焊盤111，可提供用於將該晶片焊盤111電連接於外部裝置的電連接路徑。此時，布線圖案140配置在絕緣圖案130內，並且根據絕緣圖案130的厚度可包括各種結構。例如，布線圖案140可用W、Cu、Zr、Ti、Ta、Al、Ru、Pd、Pt、Co、Ni或者這些的組合構成。
在布線圖案140的最上部面和外側中的至少一部分可存在氧化層150。氧化層150是指構成布線圖案140的物質中的至少一部分通過特殊工藝發生化學反應而形成的層。如此的氧化層150起到與塗層布線圖案140外面一樣的作用，進而可加強布線圖案140的耐蝕性及耐磨性。
據此，代替以往在形成布線圖案140之後反覆形成絕緣圖案並且開放外部焊盤連接外部連接端子的工藝，只通過用於形成氧化層150的化學工藝可有效保護布線圖案140。
另一方面，作為形成氧化層150的一示例，可利用黑化(black oxide)工藝，結果可由黑化處理層形成氧化層150。此時，通過黑化處理工藝生成的氧化層150在布線圖案140用Cu形成的情況下可包含諸如CuO、Cu2O等的氧化銅。對於利用黑化處理(black oxide)工藝形成氧化層150將通過後續的部分進行更加詳細的說明。
重新參照圖1及圖2，只對於布線圖案140的一部分區域通過氧化反應形成氧化層150，而布線圖案140的剩餘一部分可不發生金屬氧化反應，以使待後述的外部連接端子160與布線圖案140相互接觸。對此將在下文中進行說明。
外部連接端子160作為從半導體封裝件100、200向外部裝置傳輸電信號的端子，可配置在布線圖案140上。即，外部連接端子160可與布線圖案140電連接。據此，外部連接端子160可構成為通過布線圖案140可電連接於半導體晶片110的晶片焊盤111，並且電連接半導體封裝件100、200和外部裝置(例如，基板等)。即，外部連 接端子160可以是用於將半導體封裝件100、200貼裝於作為外部裝置的印刷電路板(printed circuit board)等的基板(board)上的連接端子。
例如，外部連接端子160可包括焊錫凸塊(solderbump)，並且可包含Sn、Au、Ag、Ni、In、Bi、Sb、Cu、Zn、Pb或者這些的組合，但是不限於此。另外，焊錫凸塊可以是球形狀，但是不限於此，也可以是圓柱、多邊形柱、多面體等的各種形狀。
在本發明的第一及第二實施例的半導體封裝件100、200中，在半導體晶片110產生的電信號依次經過晶片焊盤111、布線圖案140及外部連接端子160可傳輸於連接於外部連接端子160的外部裝置。另外，在外部裝置產生的電信號依次經過外部連接端子160、布線圖案140及晶片焊盤111可傳輸於半導體晶片110。在這種電信號傳輸過程中，絕緣圖案130和氧化層150防止在晶片焊盤111、布線圖案140發生不必要的電短路，並且可防止對這些結構的物理性/化學性損壞。
以下，參照附圖說明本發明的第一及第二實施例的半導體封裝件100、200的製造方法。
圖3a至圖3f作為用於依次說明在圖1示出的本發明的一實施例的半導體封裝件的製造方法的圖，是按各步驟示出半導體封裝件的剖面的圖。圖4a至圖4g作為用於依次說明在圖2示出的本發明的第二實施例的半導體封裝件的製造方法的圖，是按各步驟示出半導體封裝件的剖面的圖。如上所述，在圖1示出的實施例和在圖2示出的實施例只是在絕緣圖案130的層疊方法存在差異，而其他結構的形成則相同或者類似，因此避免重複的說明，只對區別點進行強調和說明。
本發明的第一及第二實施例的半導體封裝件的製造方法為，首先在具有晶片焊盤111的半導體晶片110的第一面可形成絕緣圖案130(參照圖3(a)及圖4(a))。此時，通過回蝕刻(etch back)工藝或者拋光工藝等去除絕緣圖案130的上面一部分，進而可降低絕緣 圖案130的高度，並且可增加這上面的表面粗糙度。如此，通過絕緣圖案130的上面的表面粗糙度增加，可加強通過後續工藝形成的布線圖案140和絕緣圖案130之間的粘合力。
另一方面，絕緣圖案130可通過利用固態(solid state)絕緣膜的薄膜層合(film lamination)工藝形成。例如，塗敷半固化狀態(即，B-stage)的絕緣膜，執行預固化(pre-cure)工藝，可形成絕緣圖案130。但是，不限於上述的，而是也可利用液態的物質形成絕緣圖案130。在該情況下，在液態物質的熱收縮過程中在絕緣圖案130也可產生殘餘應力。即，在利用固態的絕緣膜形成絕緣圖案130的情況下，不僅可將因為熱收縮發生殘餘應力最小化，還可容易形成厚度相對大的絕緣圖案130。
另一方面，如圖2所示，在絕緣圖案130具有層疊多個絕緣層的結構的情況下，在半導體晶片110的第一面形成第一絕緣層131，之後可在第一絕緣層131上形成第二絕緣層132(參照圖4(a)及4(b))。例如，在半導體晶片110的第一面首先形成氮化矽膜(SiN)，之後在氮化矽膜的上面可層疊形成聚醯亞胺(PI)。在該情況下，與上述相同也通過回蝕刻(etch back)工藝或者拋光工藝等去除第一絕緣層131或者第二絕緣層132的上面一部分，進而當然可降低高度並且可增加各個上面的表面粗糙度。此時，增加的第一絕緣層131的表面粗糙度可大於通過後續工藝形成的第二絕緣層132的上面及下面的表面粗糙度。
之後，在絕緣圖案130的上面通過蝕刻工藝形成暴露晶片焊盤111的一部分的開口部，之後在絕緣圖案130上可形成布線圖案140(參照圖3(b)及4(c))。即，布線圖案140沿着絕緣圖案130的上面延伸並且可與半導體晶片110的晶片焊盤111電連接。此時，絕緣圖案130的開口部可具有錐形狀或者階梯形狀等，在絕緣圖案130的開口部上形成的布線圖案140的部位也可形成錐形狀或者階梯形狀，但是不限於此。例如，絕緣圖案130的開口部可通過衝壓 (stamping)、蝕刻(Etching)、拋光(Polishing)、化學機械拋光(Chemical Mechanical Polishing，CMP)、打磨(Grinding)或者這些工藝的組合等形成，但是不限於此。
另外，為了形成布線圖案140，形成對絕緣圖案130的上面覆蓋至少一部分的籽晶金屬層，可執行將該籽晶金屬層作為籽晶(seed)的鍍金工藝。例如，布線圖案140可通過浸漬鍍(immersion plating)、無電鍍(electroless plating)、電鍍(electroplating)或者這些的組合等形成，但是不限於此。
然後，在布線圖案140的上面中，對於外部連接端子160待接觸的一部分區域可配置掩膜圖案(參照圖3(c)及圖4(d))。此時，掩膜圖案152可以是用具有耐化學性或者耐熱性(Chemical-Resist and Thermal-Resist)的物質形成的覆蓋材料。在此，具有耐化學性或者耐熱性的物質可包含Sn、Au、Ag、Ni、In、Bi、Sb、Cu、Zn、Pb或者這些的組合等，但是不限於此。掩膜圖案152是為了在待後述的用於形成氧化層150的工藝時(參照圖3(d)及4(e))從腐蝕等的化學反應中保護與外部連接端子160待連接的布線圖案140的上面一部分而使用。為了形成掩膜圖案152，可進行將上述的具有耐化學性或者耐熱性的物質以熔融狀態塗敷於布線圖案140表面的至少一部分，或者在布線圖案140表面的至少一部分鍍覆諸如金(Au)的具有耐化學性的材料的工藝。
然後，在布線圖案140的外面中至少一部分可形成氧化層150(參照圖3(d)及4(e))。如上所述，為了加強布線圖案140的耐蝕性及耐磨性，將構成布線圖案140的物質中的至少一部分通過特殊工藝進行化學反應，進而可形成氧化層150。此時，對於布線圖案140的上面中配置有掩膜圖案152的區域，因為被掩膜圖案152保護，所以不發生化學反應。從而，若在之後去除掩膜圖案152，則沒有因為化學反應而受損的布線圖案140的上面一部分與外部連接端子160可相互連接。
此時，作為形成氧化層150的一示例，可利用黑化處理(black oxide)工藝。對於黑化處理工藝進行更加細分化，可包括：布線圖案表面的清洗步驟、表面粗糙度形成步驟、預浸漬(Pre-Dip)步驟、氧化層形成步驟及乾燥步驟等。舉一示例，在布線圖案包含Cu的情況下，黑化處理工藝為氧化Cu表面可形成氧化銅層(CuO或者Cu2O)。更詳細地說，在布線圖案140表面形成氧化銅層可通過鹼性處理執行。作為鹼性處理，可使用氫氧化鈉、氫氧化鉀等。另外，為了均勻地形成氧化銅層，優選為添加添加劑。作為添加劑可使用諸如硫酸鈉、檸檬酸鈉和乙酸鈉等的鹽或者表面活性劑。在這些處理液浸漬布線圖案140，或者將這些處理液噴射於布線圖案140，進而可形成氧化銅層。
然後，可去除曾在布線圖案140的上面一部分配置的掩膜圖案152(參照(圖3(e)及圖4(f))。配置掩膜圖案152是為了向外部暴露在黑化處理工藝中受到保護的布線圖案140區域。此時，去除阻焊劑可通過衝壓(stamping)、蝕刻(Etching)、拋光(Polishing)、化學機械拋光(Chemical Mechanical Polishing，CMP)、打磨(Grinding)或者這些工藝的組合等進行，但是不限於此。
最後，在布線圖案140上可形成外部連接端子160。即，去除掩膜圖案152，進而可形成與向外部暴露的布線圖案140電連接的外部連接端子160(參照圖3(f)及圖4(g))。如圖所示，在配置球形狀等的焊錫凸塊之後執行迴流焊工藝可形成外部連接端子160。
另一方面，在覆蓋層上塗敷助焊劑(flux)，在塗敷有助焊劑的覆蓋層上配置球形狀等的焊錫凸塊，之後執行迴流焊工藝可形成外部連接端子160。例如，迴流焊工藝可在200℃至280℃的溫度下執行數十秒至數分鐘。在進行迴流焊工藝的期間，可擴散覆蓋層，並且在覆蓋層所包含的第三金屬物質與在布線圖案140所包含的第一金屬物質及在外部連接端子160所包含的第二金屬物質在高溫下進行反應，結果可生成金屬間化合物層。這種金屬間化合物層可沿着布線圖案140的 表面形成。例如，在布線圖案140包含Cu及/或者Ni、外部連接端子160包含Sn及/或者Cu、覆蓋層包含Au時，金屬間化合物層可包含Cu-Ni-Sn-Au。但是，金屬間化合物層的物質或者組成不限於此，而是根據布線圖案140的物質、外部連接端子160的物質、覆蓋層的物質、迴流焊工藝的溫度及時間等可有所不同。
但是，對於上述的覆蓋層及外部連接端子160的具體數值、工藝方法等的內容不限於此，而是可更加多樣。
然後，可最終加工處理成半導體封裝件100、200。即，在製造諸如晶片等級封裝等的相互連接的多個半導體封裝件100、200的情況下，沿着劃線(scribe line)等進行切割，進而可個別化成個別單位的半導體封裝件100、200。
另一方面，與利用掩膜圖案152的上述的方法不同，布線圖案140上首先形成球形狀等的焊錫凸塊，之後(為了形成外部連接端子160)也可形成氧化層150。即，在上述的方法中省略配置掩膜圖案的步驟，而是直接配置焊錫凸塊，之後執行例如黑化處理工藝，可氧化布線圖案140的外面。在該情況下，由於省略了配置及去除掩膜圖案的步驟，進而可謀求更加有效的工藝縮短。
以下，說明本發明的第三及第四實施例的半導體封裝件300、400。本發明的第三及第四實施例的半導體封裝件300、400為同樣地包括上述的本發明的第一及第二實施例的結構中的一部分結構的形狀的半導體封裝件，因此與上述的半導體封裝件100、200相比，避免對相同構成元素的重複說明，以區別點為中心進行說明。
首先，如圖5所示，本發明的第三實施例的半導體封裝件300可包括半導體晶片110、布線圖案140及外部連接端子160。
此時，相比於上述的第一實施例及第二實施例，半導體封裝件300可省略絕緣圖案130，以將工藝上的過程最少化並將經濟性最大化。即，在半導體晶片110上可形成布線圖案140。
如此，可省略絕緣圖案130是因為在本發明的第三實施 例的半導體封裝件300貼裝於PCB基板10時在半導體晶片110和PCB基板10之間填充底部填充料190，對此將在下文中進行說明。
然後，如圖5所示，本發明的第三實施例的半導體封裝件300為在布線圖案140上無需附加單獨的UBM(Under Bump Metallurgy，凸塊底部金屬化)層，而是可直接形成外部連接端子160。
根據以往的技術，為了在布線圖案上配置焊錫凸塊等的外部連接端子160，需要用於防止焊錫凸塊擴散的另外的UBM層。然而，另外形成這種UBM層需要附加的工作，因此可成為製作工藝的負擔。據此，本發明的發明人發明了沒有UBM層的附加也可有效防止焊錫凸塊的擴散保持球(sphere)形狀的半導體封裝件300、400。
具體地說，本發明的第三實施例的半導體封裝件300可包括特有的布線圖案140，以使焊錫凸塊160沒有UBM層也可有效保持球形狀。但是，在本說明書中，球形狀不代表在數學意義上的完整的球形，而是大致具有與球形類似的形狀，據此與布線圖案140接觸的焊錫凸塊160的一部分可部分性地包括平面。
此時，布線圖案140可形成為允許熔融狀態的焊錫凸塊160以設計流動方向流動，並限制了除了所述設計流動方向以外的其他方向的流動。
即，在本發明的第三實施例中，布線圖案140可形成為空間性孤立焊錫凸塊160且只以所述設計流動方向空間性開放的結構。
作為具體的一示例，如圖6所示，布線圖案140a可包括：支撐焊錫凸塊160的孤立部141；從孤立部141延伸形成的引導部142。
此時，孤立部141作為在布線圖案140a中放置熔融狀態的焊錫凸塊160的一部分，可具有預定面積，以限制焊錫凸塊160的流動範圍。例如，如圖6所示，孤立部141可形成球形狀，以與形成球形狀的焊錫凸塊160下部相對應。
如上所述，熔融狀態的焊錫凸塊160因為在具有預定面積的孤立部141和配置在下部的半導體晶片110之間形成的階梯可被 限制以水平方向流動。結果，在有限面積的孤立部141內可生成要形成小面積的表面張力(surface tension)，以使液體狀態的焊錫凸塊160的表面自動收縮，據此焊錫凸塊160無需另外的UBM層也可有效保持球形狀。
即，孤立部141可空間性孤立焊錫凸塊160，以有效生成熔融狀態的焊錫凸塊160內表面張力。
重新參照圖6，在本發明的第三實施例中，布線圖案140a可包括引導部142，所述引導部142從孤立部141的一側部以水平方向凸出延伸預定長度。
此時，熔融狀態的焊錫凸塊160被上述的孤立部141限制流動範圍，而引導部142是用於針對預先設定的設計流動方向允許流動預定的量。
如上所述，通過引導部142允許焊錫凸塊160流動一部分是在只配置有孤立部141的情況下用於防止基於構成焊錫凸塊160的分子間距離非常接近而增加的引力導致生成分子間排斥力。即，在分子間排斥力過大的情況下，焊錫凸塊160無法再保持球形狀，而是能夠以與孤立部141相鄰的半導體晶片110方向流動。
為了防止這一現象，引導部142可形成從焊錫凸塊160向外側方向凸出的形狀的凸出凸起162，以引導焊錫凸塊160，使焊錫凸塊160隻以有限的方向少量流動。據此，焊錫凸塊160可使分子間保持適當的距離。
此時，引導部142可具有小於焊錫凸塊160的線寬L1的線寬L2。在此，如圖所示，焊錫凸塊的線寬L1由焊錫凸塊160的兩端部之間的距離規定，引導部的線寬L2由以與引導部的凸出方向垂直的方向測量的引導部的寬度規定。
如上所述，在本發明的第三實施例中，引導部142具有小於焊錫凸塊160線寬L1的線寬L2是因為如果在引導部的線寬L2大於焊錫凸塊的線寬L1的情況下焊錫凸塊160並不在孤立部141上保持 球形狀，而是大部分可向引導部142側流動。
作為與此相關的示例，相對於焊錫凸塊的線寬L1，引導部的線寬L2可在15%以下。相反。若對比焊錫凸塊引導部的線寬L2過小，則存在導電性低的問題。綜合考慮上述內容，對比焊錫凸塊的線寬L1，引導部的有效線寬L2在3%至7%。如果，在形成多個引導部的情況下，相對於焊錫凸塊的線寬，多個引導部的線寬的總和數值可在3%至7%。
在本發明的第三實施例中，根據設計，所述引導部142也可形成為沿着孤立部141的外周面間隔配置多個。
此時，多個引導部為以孤立部141為基準對稱配置，進而焊錫凸塊160以均勻的量以水平方向流動，可形成多個凸出凸起162。據此，將焊錫凸塊160內表面張力方向均勻化，進而焊錫凸塊160能夠更加穩定地保持球形狀。
另一方面，如上所述，通過引導部142以設計流動方向流動熔融狀態的焊錫凸塊160，而且因為在焊錫凸塊160內形成的表面張力可限制最大流動範圍。更詳細地說，如圖6所示，通過引導部142流動的焊錫凸塊160最大可達範圍，即凸出凸起162的最大凸出長度可以是0.1um至20um。此時，優選為，凸出凸起162不超出焊錫凸塊160的最外側部。據此，即使焊錫凸塊160通過引導部142流動一部分，焊錫凸塊160也可最大限度地保持球形狀。然而，本發明的實施例不限於此，而是根據設計凸出凸起162也可超出焊錫凸塊160的最外側部。
在本發明的第三實施例中，根據設計，引導部142可形成各種形狀。
作為非限制性一示例，如圖8所示，也可形成為從連接於孤立部141的部分向外側方向逐漸增加線寬的形狀，也可與此相反地形成。除此之外，引導部142的形狀不限於在附圖示出的，而是可形成各種形狀。
在本發明的第三實施例中，如圖7所示，布線圖案140a可包括：第一布線圖案140a’；及與所述第一布線圖案140a’連接的第二布線圖案140a”。
具體地說，第一布線圖案140a’的第一引導部142和第二布線圖案140a”的第二引導部142相互連接，進而整體可形成具有左右對稱結構的諸如啞鈴的形狀。
此時，第一布線圖案140a’和第二布線圖案140a”可形成一體。
如此，在引入相互連接形成一體的第一布線圖案140a’和第二布線圖案140a”的情況下，可將多個布線圖案一次性形成在半導體晶片110上，因此可得到工藝更快速及更加經濟的效果。
但是，上述的啞鈴形狀的布線圖案140a僅是一示例，第一布線圖案140a’和第二布線圖案140a”可連接成各種形狀，除此之外在除了第一布線圖案140a’及第二布線圖案140a”之外，還包括第三布線圖案、第四布線圖案等可進行各種連接。
在本發明的第三實施例中，如圖9所示，作為布線圖案140的另一示例，布線圖案140b可形成以水平方向具有預定面積的平板形狀。
此時，在布線圖案140b可形成貫通所述布線圖案140b的多個狹縫143。這種多個狹縫143可相互間隔配置，並且可配置成包圍焊錫凸塊160和布線圖案140b的區域。即，球形狀的焊錫凸塊160的情況下，如圖所示可使多個狹縫143整體構成圓形，以與焊錫凸塊160的下部對應。
此時，在相互間隔配置的多個狹縫143之間可形成通道146。
另一方面，所述多個狹縫143形成包圍焊錫凸塊160的閉合曲線形狀，因此可空間性區劃布線圖案140b。具體地說，多個狹縫143對平板形狀的布線圖案140b可區劃成形成在多個狹縫143內側 的內側空間部144和形成在外側的外側空間部145。據此，多個狹縫143可執行在平板形狀的布線圖案140b上空間性孤立焊錫凸塊160的功能。
更詳細地說，在內側空間部144放置有焊錫凸塊160，而熔融狀態的焊錫凸塊160可被多個狹縫143限制以水平方向流動。據此，焊錫凸塊160在有限面積的內側空間部144內以與上述相同的原理生成表面張力，進而可有效保持球形狀。
此時，如上所述，在多個狹縫143之間可形成通道146，據此焊錫凸塊160的一部分進行流動可形成上述的凸出凸起162。間隔配置多個狹縫143來形成通道146與上述的引導部142相同，是為了使焊錫凸塊160中的少量焊錫凸塊160通過通道146流動來形成凸出凸起162以適當保持焊錫凸塊160內分子間距離。即，形成通道146是為了在分子間距離不充分的情況下防止因為分子間排斥力導致焊錫凸塊160無法再保持球形狀而流動到狹縫143的區域。
另一方面，參照圖10，在形成平板形狀的布線圖案140b上可固定多個焊錫凸塊160。此時，在各個焊錫凸塊160的相鄰的區域可形成為使多個狹縫143分別個別地包圍焊錫凸塊160。如此，利用平板形狀的布線圖案140b對於與多個焊錫凸塊160對應的位置分別一次性形成多個狹縫143，進而可謀求工藝效率。
在本發明的第三實施例中，焊錫凸塊160在內部可包括芯球161。
更詳細地說，參照圖5，芯球161可形成直徑小於焊錫凸塊160的球形，並且可配置在焊錫凸塊160的中心部。
此時，芯球161可用塑料或者銅形成，並且在焊錫凸塊160的內側佔據空間，進而對於熔融狀態的焊錫凸塊160可向外側方向施加壓力。據此，熔融狀態的焊錫凸塊160為可更加鄰近地形成分子間距離，基於此更加穩定地形成表面張力，進而可有效保持球形狀。
另一方面，芯球161的材料不限於上述的塑料或者銅，而 是只要是可有效生成焊錫凸塊160內表面張力的材料，則可適用任何材料。
在本發明的第三實施例中，在布線圖案140的外面中除了配置所述焊錫凸塊160的部分以外的至少一部分也可形成本發明的第一及第二實施例說明的氧化層150。
此時，氧化層150作為構成布線圖案140的物質中的至少一部分通過特殊工藝發生化學反應而形成的層，是用於加強布線圖案的耐蝕性及耐磨性的。作為非限制性一示例，與上述相同可通過黑化處理工藝形成氧化層150。除此之外，與形成氧化層150的相關說明與上述實施例的相關說明重複，因此省略說明。
在本發明的第三實施例中，在布線圖案140的外面中除了配置有所述焊錫凸塊160的部分以外的至少一部分也可形成有機被膜(OSP，Organic Solderability Preservative)層170，以代替上述的氧化層150。
此時，有機被膜層170是用於表面處理並塗層布線圖案140的，可包含與所述布線圖案140的材料選擇性結合的有機化合物。
舉一示例，形成有機被膜層的有機化合物可以是烷基苯并咪唑(Alkylbenzimidazole)，如此的有機被膜層與布線圖案140的表面發生化學反應，進而在布線圖案140的表面可形成薄且均勻的被摸。據此，可從外部的空氣及濕氣中有效保護布線圖案140的表面的同時在迴流焊及待後述的固化底部填充料190的高濕度環境下也可有效防止布線圖案140的氧化。
以下，參照圖11說明本發明的第四實施例的半導體封裝件400。但是，省略與本發明的第三實施例的半導體封裝件300重複的說明。
相比於上述的本發明的第三實施例的半導體封裝件300，本發明的第四實施例的半導體封裝件400的特徵為，在半導體晶片110和布線圖案140之間形成另外的絕緣圖案130。
此時，如圖10所示，絕緣圖案130配置在半導體晶片110上部，並且可配置成使晶片焊盤111的至少一部分暴露。然後，舉一示例，配置在半導體晶片110上的絕緣圖案130可用聚醯亞胺PI形成。
此時，布線圖案140配置在絕緣圖案130上部，只是在至少一部分與晶片焊盤111的暴露的一部分接觸以與晶片焊盤111電連接的這一點上存在區別，布線圖案140的主要功能及結構與上述的本發明的第三實施例的半導體封裝件300的布線圖案140相同，因此省略對此說明。
另一方面，如圖12所示，本發明的各種實施例的半導體封裝件100、200、300、400可貼裝於PCB基板10。在所述半導體封裝件100、200、300、400貼裝於PCB基板10之後在所述半導體封裝件100、200、300、400和PCB基板10之間填充底部填充料190可形成電絕緣層。
此時，所述半導體封裝件100、200、300、400的絕緣圖案130、布線圖案140、外部連接端子160與所述底部填充料190直接接觸，可被底部填充料190掩埋。
此時，所述底部填充料190可使用公知的材料，或者也可使用與成型半導體晶片110的環氧膠成型化合物相同的材料。
通過如上所述的底部填充料190執行SMT(Surface Maunt Technology，表面貼裝技術)工藝，進而本發明的各種實施例的半導體封裝件100、200、300、400可省略上述的UBM工藝或者鈍化工藝。據此，可得到將工藝簡單化並且節省半導體封裝件的成本的效果。
如上所述，在以上說明的半導體封裝件100、200、300、400的優點如下：不僅可適用於WLP(Wafer Level Packaging，晶片級封裝)，還可適用於FOWLP(Fan-out wafer-level packaging扇出晶片級封裝)，並且由氧化層150或者有機被膜層代替或者可省略在布線圖案的上部附加的鈍化工藝及用於打開外部焊盤的工藝。
具體地說，參照圖12，如下說明本發明的各種實施例的半導體封裝件適用於FOWLP工藝的示例。
如圖13所示，根據FOWLP工藝，半導體晶片110被密封部180覆蓋，並且在所述半導體晶片110和密封部180上可形成絕緣圖案130。此時，密封部180是用於從熱、水分或者外部衝擊中保護半導體晶片110的，舉一示例可用環氧膠成型化合物(Epoxy Molding Compound)保護半導體晶片110。
然後，在所述絕緣圖案130中去除位於晶片焊盤111上的絕緣圖案130的一部分，形成布線圖案140，之後可將焊錫凸塊160直接放置在所述布線圖案140上。但是，在該情況下，根據需求，不形成另外的絕緣圖案130，而是在半導體晶片110和密封部180上直接形成布線圖案140，並且也可形成焊錫凸塊160。
此時，如上所述，無需另外的UBM工藝可將焊錫凸塊160直接形成在布線圖案140上是通過為使焊錫凸塊160孤立而形成的布線圖案140及芯球161等實現。
另一方面，根據其他的半導體封裝工藝，如圖14所示，在半導體晶片110上形成導電柱112，之後用上述的密封部180包圍成型之後可形成絕緣圖案130。然後，在絕緣圖案130中開放與導電柱112對應的區域，如圖所示形成布線圖案140，之後通過如上所述為使焊錫凸塊160孤立而形成的布線圖案140及芯球161等可將焊錫凸塊160直接放在布線圖案140上。
以下，說明本發明的第五實施例的半導體封裝件。
參照圖15，本發明的第五實施例的半導體封裝件500包括絕緣體530、上部布線圖案550、下部布線圖案540、連接布線圖案570、半導體晶片510及焊錫凸塊560。
如圖所示，絕緣體530可由板狀結構形成，並且可用介電常數(Dk)及介電損耗角正切(Df)材料構成。據此，半導體封裝件500可用於傳輸高速RF信號。
此時，絕緣體530可由絕緣性聚合物、環氧膠(epoxy)、氧化矽膜、氮化矽膜(SiN)或者這些的組合構成。另外，絕緣體530可用非光敏性物質或者光敏性物質構成。舉一示例，絕緣體530可用聚醯亞胺(PI，polyimide)構成。
在此，絕緣性聚合物可包含諸如PMMA(Polymethylmethacrylate，聚甲基丙烯酸甲酯)、PS(Polystylene，聚苯乙烯)、PBO(Polybenzoxzoles，聚苯并
Figure 110105758-A0305-02-0024-2
唑)等的常規的通用聚合物、丙烯酸類聚合物、醯亞胺類聚合物(聚醯亞胺(PI，polyimide))、芳醚類聚合物、醯胺類聚合物、氟類聚合物、對二甲苯類聚合物、乙烯醇類聚合物、具有苯酚組的聚合物衍生物或者這些的組合等。
然後，上部布線圖案550可用導電性材料構成，舉一示例可用W、Cu、Zr、Ti、Ta、Al、Ru、Pd、Pt、Co、Ni或者這些的組合構成。
在本發明的第五實施例中，如圖所示，上部布線圖案550配置在絕緣體530上，可與半導體晶片510的晶片焊盤511電連接。此時，半導體晶片510可通過焊錫513連接。
下部布線圖案540可用與上部布線圖案550相同的材料形成，並且可配置在絕緣體530的下面上。即，下部布線圖案540為以絕緣體530為準可配置上部布線圖案550的相反側。
此時，如上所示，在下部布線圖案540上可放置焊錫凸塊560。
具體地說，與上述的實施例類似，下部布線圖案540可包括：孤立部，具有預定面積以限制熔融狀態的所述焊錫凸塊560的流動範圍，並且支撐所述焊錫凸塊；引導部，從所述孤立部的一側部以水平方向凸出延伸，以使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起。
此時，下部布線圖案540包括的孤立部和引導部的結構及功能與在上述的實施例說明的孤立部141及引導部142相同。另外， 放在下部布線圖案540上的焊錫凸塊560的形狀或者流動也與上述的實施例相同。即，相對於所述焊錫凸塊的線寬，所述引導部的線寬可以是1%至15%，焊錫凸塊的凸出凸起從焊錫凸塊凸出的長度可以是0.1um至20um。然後，在焊錫凸塊的內部也可包括芯球。省略除此之外重複的說明。
如上所述，下部布線圖案540通過包括孤立部和引導部的特有的結構及芯球可使焊錫凸塊560最大限度地保持球或者橢圓形狀。
另一方面，重新參照附圖，在絕緣體530的內部能夠以被絕緣體掩埋的形式配置相互連接上部布線圖案550和下部布線圖案540的連接布線圖案570。據此，半導體晶片510可與以後與焊錫凸塊560待連接的PCB基板電連接。
包括如上所述的結構的本發明的第五實施例的半導體封裝件500作為iP(System-in-Package技術)，可具有包括不同種類的半導體晶片的多晶片結構。即，半導體封裝件500可包括多個半導體晶片。同時，半導體封裝件500可包括多個手動元件。
以上，說明了本發明的各種實施例，但是本發明的思想不限於在本說明書提出的實施例，而是理解本發明的思想的技術人員在相同的思想範圍內通過構成元素的附加、改變、刪除、增加等可容易提出其他實施例，而且這也包括在本發明的思想範圍內。
300:半導體封裝件
110:半導體晶片
111:晶片焊盤
140:布線圖案
150:氧化層
160:外部連接端子
161:芯球
162:凸出凸起
170:有機被膜層

Claims (13)

  1. 一種半導體封裝件，包括：半導體芯片，在一面配置至少一個芯片焊盤；布線圖案，配置在所述半導體芯片的上部，並且至少一部分與所述芯片焊盤電連接；及焊錫凸塊，配置在所述布線圖案的外面上，以通過所述布線圖案與所述芯片焊盤電連接；其中，所述布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸。
  2. 如請求項1所述之半導體封裝件，更包括：PCB基板，與所述焊錫凸塊的上部電連接；及底部填充料，在所述半導體芯片和所述PCB基板之間形成的空間填充，以包圍所述布線圖案和所述焊錫凸塊。
  3. 如請求項1所述之半導體封裝件，其特徵在於，相對於所述焊錫凸塊的線寬，所述引導部的線寬為1%至15%。
  4. 如請求項1所述之半導體封裝件，其特徵在於，所述凸出凸起從所述焊錫凸塊凸出的長度為0.1um至20um。
  5. 如請求項1所述之半導體封裝件，其特徵在於，所述焊錫凸塊在中心部包括芯球。
  6. 如請求項1所述之半導體封裝件，其特徵在於，所述布線圖案形成墊片形狀；所述布線圖案包括：多個狹縫，貫通所述布線圖案，並且相互間隔，包圍所述焊錫凸塊的下部；內側空間部，支撐所述焊錫凸塊，並且配置在所述多個狹縫的內側；及 外側空間部，配置在所述多個狹縫的外側；其中，在所述多個狹縫之間形成至少一個通道，以使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起；相對於所述焊錫凸塊的線寬，所述至少一個通道的線寬總和為1%至15%。
  7. 如請求項1所述之半導體封裝件，其特徵在於，更包括：絕緣圖案，配置在所述半導體芯片的上部，並且配置成使所述芯片焊盤的至少一部分暴露；所述布線圖案為配置在所述絕緣圖案上部，並且至少一部分與所述芯片焊盤的暴露的一部分接觸，以與所述芯片焊盤電連接；在所述布線圖案的所述外面中，除了配置有所述焊錫凸塊的部分以外的至少一部分形成有機被膜層或氧化層，所述氧化層是通過與所述布線圖案的材料中的化學反應而形成的層，所述有機被膜層包含與所述布線圖案的材料選擇性結合的有機化合物。
  8. 如請求項1所述之半導體封裝件，其特徵在於，所述半導體芯片以上面一部分開放的狀態被密封部掩埋，所述布線圖案配置在所述半導體芯片和所述密封部的上部。
  9. 如請求項1所述之半導體封裝件，其特徵在於，在所述芯片焊盤的上部配置導電柱，所述半導體芯片在配置所述導電柱的狀態下被密封部掩埋，所述布線圖案配置在所述密封部的上部，配置成與所述導電柱電連接。
  10. 一種半導體封裝件，包括：半導體芯片，在一面配置至少一個芯片焊盤；布線圖案，配置在所述半導體芯片的上部，並且至少一部分與所述芯片焊盤電連接；焊錫凸塊，配置在所述布線圖案的外面上，以通過所述布線圖案與所述芯片焊盤電連接； PCB基板，與所述焊錫凸塊的上部電連接；及底部填充料，在所述半導體芯片和所述PCB基板之間形成的空間填充，以包圍所述布線圖案和所述焊錫凸塊；其中，在所述布線圖案的側面和所述布線圖案的上面中除了與所述焊錫凸塊接觸的部分以外的部分與底部填充料接觸。
  11. 如請求項10所述之半導體封裝件，其特徵在於，所述布線圖案的下側面和所述底部填充料的至少一部分配置在同一平面上。
  12. 一種半導體封裝件，包括：絕緣體；上部布線圖案，配置在所述絕緣體上；下部布線圖案，配置在所述絕緣體下部的下部；連接布線圖案，配置在所述絕緣體內部，並且連接所述上部布線圖案和所述下部布線圖案；半導體芯片，包括芯片焊盤，所述芯片焊盤配置在所述絕緣體上部並且與所述上部布線圖案電連接；及焊錫凸塊，配置在所述下部布線圖案的外面上，以與所述半導體芯片電連接；其中，所述下部布線圖案包括：孤立部，具有預定的面積以限制熔融狀態的所述焊錫凸塊的流動範圍，並且支撐所述焊錫凸塊；及引導部，為使熔融狀態的所述焊錫凸塊流動預定距離以形成凸出凸起，從所述孤立部的一側部以水平方向凸出延伸。
  13. 如請求項12所述之半導體封裝件，其特徵在於，相對於所述焊錫凸塊的線寬，所述引導部的線寬為1%至15%，所述凸出凸起從所述焊錫凸塊凸出的長度為0.1um至20um，所述焊錫凸塊在中心部包括芯球。
TW110105758A 2020-02-19 2021-02-19 半導體封裝件 TWI775319B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2020-0020556 2020-02-19
KR20200020556 2020-02-19
KR10-2021-0022404 2021-02-19
KR1020210022404A KR102520474B1 (ko) 2020-02-19 2021-02-19 반도체 패키지

Publications (2)

Publication Number Publication Date
TW202145475A TW202145475A (zh) 2021-12-01
TWI775319B true TWI775319B (zh) 2022-08-21

Family

ID=77504703

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110105758A TWI775319B (zh) 2020-02-19 2021-02-19 半導體封裝件

Country Status (3)

Country Link
US (1) US11545451B2 (zh)
KR (1) KR102520474B1 (zh)
TW (1) TWI775319B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546620B1 (en) * 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US20090096098A1 (en) * 2007-10-15 2009-04-16 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor package and method of the same
US20160141213A1 (en) * 2014-11-19 2016-05-19 Deca Technologies Inc. Automated optical inspection of unit specific patterning
US9385100B1 (en) * 2014-03-21 2016-07-05 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with surface treatment and method of manufacture thereof
US10224270B1 (en) * 2009-03-30 2019-03-05 Amkor Technology, Inc. Fine pitch copper pillar package and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388203B1 (en) * 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
KR100764055B1 (ko) * 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
US8035226B1 (en) * 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US9576919B2 (en) * 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
JP5991915B2 (ja) * 2012-12-27 2016-09-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546620B1 (en) * 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US20090096098A1 (en) * 2007-10-15 2009-04-16 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor package and method of the same
US10224270B1 (en) * 2009-03-30 2019-03-05 Amkor Technology, Inc. Fine pitch copper pillar package and method
US9385100B1 (en) * 2014-03-21 2016-07-05 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with surface treatment and method of manufacture thereof
US20160141213A1 (en) * 2014-11-19 2016-05-19 Deca Technologies Inc. Automated optical inspection of unit specific patterning

Also Published As

Publication number Publication date
US11545451B2 (en) 2023-01-03
KR102520474B1 (ko) 2023-04-11
US20210288005A1 (en) 2021-09-16
KR20210105842A (ko) 2021-08-27
TW202145475A (zh) 2021-12-01

Similar Documents

Publication Publication Date Title
US10269778B2 (en) Package on package (PoP) bonding structures
US11031347B2 (en) Semiconductor packages
TWI718314B (zh) 具有虛設晶粒的封裝結構、半導體裝置及其形成方法
US10930625B2 (en) Semiconductor package and method of fabricating the same
TWI514542B (zh) 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ）
TWI501327B (zh) 三維積體電路及其製造方法
TWI721225B (zh) 封裝結構及其製造方法
CN105895616A (zh) 金属氧化物层状结构及其形成方法
TWI534971B (zh) 半導體裝置及其製造方法
TW201637138A (zh) 半導體元件的堆疊結構
JP2011097034A (ja) 再配線構造を有する半導体素子とパッケージ、及びその製造方法
TWI775319B (zh) 半導體封裝件
CN108074895B (zh) 堆叠封装结构及其制造方法
KR102457349B1 (ko) 반도체 패키지들 및 이의 제조 방법들
TWI831749B (zh) 封裝件基板及其製造方法
US11756869B2 (en) Semiconductor package having UBM pad with gap separating central portion from peripheral portion
US20240014095A1 (en) Semiconductor package and method
US20230039094A1 (en) Semiconductor package and method of manufacturing semiconductor package
KR20240083953A (ko) 반도체 패키지 및 그 제조 방법
TW202339170A (zh) 半導體封裝
KR20220089686A (ko) 재배선 구조물 및 이를 포함하는 반도체 패키지
TW202310292A (zh) 半導體封裝結構及其形成方法
KR20110137195A (ko) 인터커넥션 배선방법 및 이를 이용한 실장형 솔레노이드 제조방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent