TWI765874B - 用以改善晶圓平面性之方法及由其所製造之接合晶圓總成 - Google Patents

用以改善晶圓平面性之方法及由其所製造之接合晶圓總成 Download PDF

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TWI765874B
TWI765874B TW105141940A TW105141940A TWI765874B TW I765874 B TWI765874 B TW I765874B TW 105141940 A TW105141940 A TW 105141940A TW 105141940 A TW105141940 A TW 105141940A TW I765874 B TWI765874 B TW I765874B
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semiconductor wafer
strain
layer
curvature
warpage
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TW105141940A
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Chinese (zh)
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TW201732874A (zh
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葛雷高里 巴提尼卡
凱密希瓦 耶達維利
范謙
班傑明 A 哈斯寇
葛洛力 哈森 S 艾爾
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美商傲思丹度科技公司
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/18Preparing bulk and homogeneous wafers by shaping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50Physical imperfections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0428Apparatus for mechanical treatment or grinding or cutting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6328Deposition from the gas or vapour phase
    • H10P14/6334Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/694Inorganic materials composed of nitrides
    • H10P14/6943Inorganic materials composed of nitrides containing silicon
    • H10P14/69433Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/121Arrangements for protection of devices protecting against mechanical damage
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00Direct bonding of chips, wafers or substrates
    • H10W80/301Bonding techniques, e.g. hybrid bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00Direct bonding of chips, wafers or substrates
    • H10W80/301Bonding techniques, e.g. hybrid bonding
    • H10W80/312Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00Direct bonding of chips, wafers or substrates
    • H10W80/301Bonding techniques, e.g. hybrid bonding
    • H10W80/327Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Recrystallisation Techniques (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Physical Vapour Deposition (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
TW105141940A 2015-12-16 2016-12-16 用以改善晶圓平面性之方法及由其所製造之接合晶圓總成 TWI765874B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562268262P 2015-12-16 2015-12-16
US62/268,262 2015-12-16
US15/379,759 2016-12-15
US15/379,759 US9978582B2 (en) 2015-12-16 2016-12-15 Methods for improving wafer planarity and bonded wafer assemblies made from the methods

Publications (2)

Publication Number Publication Date
TW201732874A TW201732874A (zh) 2017-09-16
TWI765874B true TWI765874B (zh) 2022-06-01

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Country Link
US (1) US9978582B2 (https=)
JP (2) JP6952697B2 (https=)
KR (1) KR20180095609A (https=)
CN (1) CN108604572A (https=)
TW (1) TWI765874B (https=)
WO (1) WO2017106788A1 (https=)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015084851A1 (en) * 2013-12-04 2015-06-11 3M Innovative Properties Company Flexible light emitting semiconductor device with large area conduit
US10847419B2 (en) * 2018-03-14 2020-11-24 Raytheon Company Stress compensation and relief in bonded wafers
CN108649021B (zh) * 2018-07-19 2024-07-26 长江存储科技有限责任公司 晶圆翘曲调整结构及其形成方法
WO2020034138A1 (en) * 2018-08-16 2020-02-20 Yangtze Memory Technologies Co., Ltd. Wafer flatness control using backside compensation structure
JP2020047617A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 基板処理装置、半導体装置の製造方法、および被加工基板
WO2020068254A1 (en) * 2018-09-25 2020-04-02 Applied Materials, Inc. Methods and apparatus to eliminate wafer bow for cvd and patterning hvm systems
KR102491768B1 (ko) * 2018-09-28 2023-01-26 램 리써치 코포레이션 비대칭 웨이퍼 보우 보상
US10896821B2 (en) * 2018-09-28 2021-01-19 Lam Research Corporation Asymmetric wafer bow compensation by physical vapor deposition
JP2020161685A (ja) * 2019-03-27 2020-10-01 東京エレクトロン株式会社 成膜装置および成膜方法
JP7259527B2 (ja) * 2019-04-26 2023-04-18 富士電機株式会社 半導体基板の製造方法および半導体装置の製造方法
US10790296B1 (en) 2019-05-21 2020-09-29 Sandisk Technologies Llc Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer
KR102767982B1 (ko) * 2019-10-15 2025-02-14 에스케이하이닉스 주식회사 웨이퍼 지지 구조체
CN111048429B (zh) * 2019-12-23 2022-05-27 武汉新芯集成电路制造有限公司 一种晶圆键合方法
WO2021138018A1 (en) 2020-01-03 2021-07-08 Lam Research Corporation Station-to-station control of backside bow compensation deposition
KR20260029373A (ko) * 2020-01-30 2026-03-04 램 리써치 코포레이션 국부적인 응력 변조를 위한 uv 경화
FR3121548B1 (fr) * 2021-03-30 2024-02-16 Soitec Silicon On Insulator Procede de preparation d’un substrat avance, notamment pour des applications photoniques
CN115812345A (zh) 2021-06-30 2023-03-17 长江存储科技有限责任公司 三维存储器装置及其形成方法
WO2023272627A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
CN116058100B (zh) 2021-06-30 2025-12-30 长江存储科技有限责任公司 三维存储器装置及其形成方法
CN115836387B (zh) 2021-06-30 2026-01-23 长江存储科技有限责任公司 三维存储器装置及其形成方法
CN116018889B (zh) 2021-06-30 2026-01-23 长江存储科技有限责任公司 三维存储器装置及其形成方法
WO2023272625A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
WO2023272614A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
CN116368952A (zh) 2021-06-30 2023-06-30 长江存储科技有限责任公司 三维存储器装置及其形成方法
CN113906542A (zh) * 2021-08-30 2022-01-07 长江存储科技有限责任公司 使用背面膜层沉积和激光退火的晶圆应力控制
CN115036204A (zh) * 2022-05-07 2022-09-09 上海华力集成电路制造有限公司 通过降低晶圆翘曲度提高bsi工艺稳定性的方法
TW202431354A (zh) * 2022-09-28 2024-08-01 美商應用材料股份有限公司 應力管理期間全域曲率的校正
US20240266174A1 (en) * 2023-02-08 2024-08-08 Applied Materials, Inc. Mitigation of saddle deformation of substrates using film deposition and edge ion implantation
KR20240168145A (ko) * 2023-05-22 2024-11-29 에스케이하이닉스 주식회사 반도체 장치의 제조 방법
CN117373908A (zh) * 2023-10-09 2024-01-09 物元半导体技术(青岛)有限公司 调整晶圆翘曲度的方法、光刻方法及半导体结构
US12435964B2 (en) 2023-11-16 2025-10-07 Tokyo Electron Limited Contactless capacitive measurement tool with improved throughput and accuracy
CN118263137B (zh) * 2024-05-29 2025-07-25 浙江创芯集成电路有限公司 半导体结构的形成方法
DE102024117104A1 (de) * 2024-06-18 2025-12-18 Ligentec Sa Photonisch integrierte Schaltung und Verfahren zur Herstellung
US20260068690A1 (en) * 2024-09-04 2026-03-05 Tokyo Electron Limited Fill shape optimization for substrate bonding

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314725A1 (en) * 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
US20140374879A1 (en) * 2013-06-25 2014-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with backside structures to reduce substrate wrap

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4790920A (en) 1985-12-20 1988-12-13 Intel Corporation Method for depositing an al2 O3 cap layer on an integrated circuit substrate
US4830984A (en) * 1987-08-19 1989-05-16 Texas Instruments Incorporated Method for heteroepitaxial growth using tensioning layer on rear substrate surface
JPH01256126A (ja) * 1988-04-06 1989-10-12 Sumitomo Electric Ind Ltd 半導体装置の製造方法
US5286671A (en) 1993-05-07 1994-02-15 Kulite Semiconductor Products, Inc. Fusion bonding technique for use in fabricating semiconductor devices
JPH08111409A (ja) * 1994-10-12 1996-04-30 Rohm Co Ltd 半導体装置の製法
JPH08227834A (ja) * 1995-02-21 1996-09-03 Sony Corp 半導体ウェーハ及びその製造方法
US6652356B1 (en) 1999-01-20 2003-11-25 Shin-Etsu Handotai Co., Ltd. Wire saw and cutting method
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US20070194342A1 (en) 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8557681B2 (en) * 2006-10-30 2013-10-15 International Rectifier Corporation III-nitride wafer fabrication
US8664747B2 (en) * 2008-04-28 2014-03-04 Toshiba Techno Center Inc. Trenched substrate for crystal growth and wafer bonding
WO2012043616A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイス、圧電デバイスの製造方法
WO2012043615A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイスの製造方法
CN103109350A (zh) * 2010-09-30 2013-05-15 飞思卡尔半导体公司 处理半导体晶片的方法、半导体晶片以及半导体器件
JP5642628B2 (ja) * 2011-05-27 2014-12-17 東京エレクトロン株式会社 基板反り除去装置、基板反り除去方法及び記憶媒体
JP5418564B2 (ja) * 2011-09-29 2014-02-19 信越半導体株式会社 貼り合わせsoiウェーハの反りを算出する方法、及び貼り合わせsoiウェーハの製造方法
US8900969B2 (en) * 2012-01-27 2014-12-02 Skyworks Solutions, Inc. Methods of stress balancing in gallium arsenide wafer processing
KR20140104062A (ko) * 2013-02-15 2014-08-28 삼성전자주식회사 P형 질화물 반도체 제조방법 및 이를 이용한 질화물 반도체 발광소자 제조방법
CN105448762A (zh) * 2014-08-28 2016-03-30 中国科学院微电子研究所 一种衬底翘曲度的调整方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314725A1 (en) * 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
US20140374879A1 (en) * 2013-06-25 2014-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with backside structures to reduce substrate wrap

Also Published As

Publication number Publication date
JP6952697B2 (ja) 2021-10-20
TW201732874A (zh) 2017-09-16
JP2019504490A (ja) 2019-02-14
JP2022008584A (ja) 2022-01-13
WO2017106788A1 (en) 2017-06-22
US9978582B2 (en) 2018-05-22
JP7025589B2 (ja) 2022-02-24
CN108604572A (zh) 2018-09-28
US20170178891A1 (en) 2017-06-22
KR20180095609A (ko) 2018-08-27

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