TWI764986B - 使用選擇性二氧化矽沉積以形成自我對準接觸窗的方法 - Google Patents
使用選擇性二氧化矽沉積以形成自我對準接觸窗的方法 Download PDFInfo
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- TWI764986B TWI764986B TW107105503A TW107105503A TWI764986B TW I764986 B TWI764986 B TW I764986B TW 107105503 A TW107105503 A TW 107105503A TW 107105503 A TW107105503 A TW 107105503A TW I764986 B TWI764986 B TW I764986B
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- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
- H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
- H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
- H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Electrodes Of Semiconductors (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical Vapour Deposition (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762458858P | 2017-02-14 | 2017-02-14 | |
| US62/458,858 | 2017-02-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201841215A TW201841215A (zh) | 2018-11-16 |
| TWI764986B true TWI764986B (zh) | 2022-05-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107105503A TWI764986B (zh) | 2017-02-14 | 2018-02-14 | 使用選擇性二氧化矽沉積以形成自我對準接觸窗的方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10453749B2 (https=) |
| JP (1) | JP7097713B2 (https=) |
| KR (1) | KR102445015B1 (https=) |
| TW (1) | TWI764986B (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10586734B2 (en) | 2017-11-20 | 2020-03-10 | Tokyo Electron Limited | Method of selective film deposition for forming fully self-aligned vias |
| US11335596B2 (en) * | 2018-10-30 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective deposition for integrated circuit interconnect structures |
| US10957579B2 (en) | 2018-11-06 | 2021-03-23 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via and methods of forming the same |
| CN110010460B (zh) * | 2019-03-26 | 2021-03-16 | 贵阳学院 | 一种低维材料形成方法 |
| TWI801614B (zh) * | 2019-06-21 | 2023-05-11 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
| KR102833589B1 (ko) | 2019-08-23 | 2025-07-15 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
| US11227792B2 (en) * | 2019-09-19 | 2022-01-18 | International Business Machines Corporation | Interconnect structures including self aligned vias |
| US11361989B2 (en) * | 2020-02-11 | 2022-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing interconnect structures including air gaps |
| KR20230135603A (ko) * | 2021-02-08 | 2023-09-25 | 도쿄엘렉트론가부시키가이샤 | 액상 컨포멀 실리콘 산화물 스핀-온 증착 |
| US11482454B2 (en) * | 2021-02-17 | 2022-10-25 | Tokyo Electron Limited | Methods for forming self-aligned contacts using spin-on silicon carbide |
| US11756790B2 (en) | 2021-03-09 | 2023-09-12 | Tokyo Electron Limited | Method for patterning a dielectric layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030173671A1 (en) * | 2002-03-13 | 2003-09-18 | Nec Corporation | Semiconductor device and manufacturing method for the same |
| US7271112B1 (en) * | 2004-12-30 | 2007-09-18 | Novellus Systems, Inc. | Methods for forming high density, conformal, silica nanolaminate films via pulsed deposition layer in structures of confined geometry |
| US20080111239A1 (en) * | 2006-11-15 | 2008-05-15 | International Business Machines Corporation | Interconnect structure having enhanced electromigration reliabilty and a method of fabricating same |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0362571A3 (en) * | 1988-10-07 | 1990-11-28 | International Business Machines Corporation | Method for forming semiconductor components |
| JP3469251B2 (ja) * | 1990-02-14 | 2003-11-25 | 株式会社東芝 | 半導体装置の製造方法 |
| US7294593B2 (en) | 2002-11-21 | 2007-11-13 | Kimberly-Clark Worldwide, Inc. | Absorbent article material with elastomeric borders |
| US6867152B1 (en) | 2003-09-26 | 2005-03-15 | Novellus Systems, Inc. | Properties of a silica thin film produced by a rapid vapor deposition (RVD) process |
| US8158488B2 (en) | 2004-08-31 | 2012-04-17 | Micron Technology, Inc. | Method of increasing deposition rate of silicon dioxide on a catalyst |
| US7625820B1 (en) | 2006-06-21 | 2009-12-01 | Novellus Systems, Inc. | Method of selective coverage of high aspect ratio structures with a conformal film |
| JP2010225899A (ja) * | 2009-03-24 | 2010-10-07 | Elpida Memory Inc | 半導体装置の製造方法 |
| JP2013080861A (ja) * | 2011-10-05 | 2013-05-02 | Toshiba Corp | 半導体装置 |
| US9419097B2 (en) * | 2014-11-24 | 2016-08-16 | International Business Machines Corporation | Replacement metal gate dielectric cap |
| US20170092533A1 (en) | 2015-09-29 | 2017-03-30 | Applied Materials, Inc. | Selective silicon dioxide deposition using phosphonic acid self assembled monolayers as nucleation inhibitor |
| US10049913B2 (en) | 2016-04-12 | 2018-08-14 | Tokyo Electron Limited | Methods for SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces |
| KR20170135115A (ko) * | 2016-05-30 | 2017-12-08 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
-
2018
- 2018-02-13 US US15/895,736 patent/US10453749B2/en active Active
- 2018-02-14 JP JP2018023873A patent/JP7097713B2/ja active Active
- 2018-02-14 TW TW107105503A patent/TWI764986B/zh active
- 2018-02-14 KR KR1020180018268A patent/KR102445015B1/ko active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030173671A1 (en) * | 2002-03-13 | 2003-09-18 | Nec Corporation | Semiconductor device and manufacturing method for the same |
| US7271112B1 (en) * | 2004-12-30 | 2007-09-18 | Novellus Systems, Inc. | Methods for forming high density, conformal, silica nanolaminate films via pulsed deposition layer in structures of confined geometry |
| US20080111239A1 (en) * | 2006-11-15 | 2008-05-15 | International Business Machines Corporation | Interconnect structure having enhanced electromigration reliabilty and a method of fabricating same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2018133568A (ja) | 2018-08-23 |
| US10453749B2 (en) | 2019-10-22 |
| JP7097713B2 (ja) | 2022-07-08 |
| US20180233407A1 (en) | 2018-08-16 |
| TW201841215A (zh) | 2018-11-16 |
| KR102445015B1 (ko) | 2022-09-19 |
| KR20180093833A (ko) | 2018-08-22 |
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