KR102445015B1 - 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 - Google Patents

선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 Download PDF

Info

Publication number
KR102445015B1
KR102445015B1 KR1020180018268A KR20180018268A KR102445015B1 KR 102445015 B1 KR102445015 B1 KR 102445015B1 KR 1020180018268 A KR1020180018268 A KR 1020180018268A KR 20180018268 A KR20180018268 A KR 20180018268A KR 102445015 B1 KR102445015 B1 KR 102445015B1
Authority
KR
South Korea
Prior art keywords
metal
layer
sio
dielectric layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020180018268A
Other languages
English (en)
Korean (ko)
Other versions
KR20180093833A (ko
Inventor
칸다바라 엔 타필리
상철 한
수 두 채
Original Assignee
도쿄엘렉트론가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 도쿄엘렉트론가부시키가이샤 filed Critical 도쿄엘렉트론가부시키가이샤
Publication of KR20180093833A publication Critical patent/KR20180093833A/ko
Application granted granted Critical
Publication of KR102445015B1 publication Critical patent/KR102445015B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H01L21/76897—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H01L21/02164—
    • H01L21/76819—
    • H01L21/76829—
    • H01L21/76856—
    • H01L21/76877—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Chemical Vapour Deposition (AREA)
KR1020180018268A 2017-02-14 2018-02-14 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 Active KR102445015B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762458858P 2017-02-14 2017-02-14
US62/458,858 2017-02-14

Publications (2)

Publication Number Publication Date
KR20180093833A KR20180093833A (ko) 2018-08-22
KR102445015B1 true KR102445015B1 (ko) 2022-09-19

Family

ID=63105410

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020180018268A Active KR102445015B1 (ko) 2017-02-14 2018-02-14 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법

Country Status (4)

Country Link
US (1) US10453749B2 (https=)
JP (1) JP7097713B2 (https=)
KR (1) KR102445015B1 (https=)
TW (1) TWI764986B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10586734B2 (en) 2017-11-20 2020-03-10 Tokyo Electron Limited Method of selective film deposition for forming fully self-aligned vias
US11335596B2 (en) * 2018-10-30 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Selective deposition for integrated circuit interconnect structures
US10957579B2 (en) 2018-11-06 2021-03-23 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
CN110010460B (zh) * 2019-03-26 2021-03-16 贵阳学院 一种低维材料形成方法
TWI801614B (zh) * 2019-06-21 2023-05-11 聯華電子股份有限公司 半導體元件及其製作方法
KR102833589B1 (ko) 2019-08-23 2025-07-15 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11227792B2 (en) * 2019-09-19 2022-01-18 International Business Machines Corporation Interconnect structures including self aligned vias
US11361989B2 (en) * 2020-02-11 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing interconnect structures including air gaps
KR20230135603A (ko) * 2021-02-08 2023-09-25 도쿄엘렉트론가부시키가이샤 액상 컨포멀 실리콘 산화물 스핀-온 증착
US11482454B2 (en) * 2021-02-17 2022-10-25 Tokyo Electron Limited Methods for forming self-aligned contacts using spin-on silicon carbide
US11756790B2 (en) 2021-03-09 2023-09-12 Tokyo Electron Limited Method for patterning a dielectric layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225899A (ja) 2009-03-24 2010-10-07 Elpida Memory Inc 半導体装置の製造方法
JP2013080861A (ja) 2011-10-05 2013-05-02 Toshiba Corp 半導体装置
US20160293731A1 (en) 2014-11-24 2016-10-06 International Business Machines Corporation Replacement metal gate dielectric cap

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0362571A3 (en) * 1988-10-07 1990-11-28 International Business Machines Corporation Method for forming semiconductor components
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
JP4063619B2 (ja) * 2002-03-13 2008-03-19 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7294593B2 (en) 2002-11-21 2007-11-13 Kimberly-Clark Worldwide, Inc. Absorbent article material with elastomeric borders
US6867152B1 (en) 2003-09-26 2005-03-15 Novellus Systems, Inc. Properties of a silica thin film produced by a rapid vapor deposition (RVD) process
US8158488B2 (en) 2004-08-31 2012-04-17 Micron Technology, Inc. Method of increasing deposition rate of silicon dioxide on a catalyst
US7271112B1 (en) * 2004-12-30 2007-09-18 Novellus Systems, Inc. Methods for forming high density, conformal, silica nanolaminate films via pulsed deposition layer in structures of confined geometry
US7625820B1 (en) 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
US7569475B2 (en) * 2006-11-15 2009-08-04 International Business Machines Corporation Interconnect structure having enhanced electromigration reliability and a method of fabricating same
US20170092533A1 (en) 2015-09-29 2017-03-30 Applied Materials, Inc. Selective silicon dioxide deposition using phosphonic acid self assembled monolayers as nucleation inhibitor
US10049913B2 (en) 2016-04-12 2018-08-14 Tokyo Electron Limited Methods for SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces
KR20170135115A (ko) * 2016-05-30 2017-12-08 삼성전자주식회사 반도체 장치 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225899A (ja) 2009-03-24 2010-10-07 Elpida Memory Inc 半導体装置の製造方法
JP2013080861A (ja) 2011-10-05 2013-05-02 Toshiba Corp 半導体装置
US20160293731A1 (en) 2014-11-24 2016-10-06 International Business Machines Corporation Replacement metal gate dielectric cap

Also Published As

Publication number Publication date
JP2018133568A (ja) 2018-08-23
US10453749B2 (en) 2019-10-22
JP7097713B2 (ja) 2022-07-08
TWI764986B (zh) 2022-05-21
US20180233407A1 (en) 2018-08-16
TW201841215A (zh) 2018-11-16
KR20180093833A (ko) 2018-08-22

Similar Documents

Publication Publication Date Title
KR102445015B1 (ko) 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법
US10453681B2 (en) Method of selective vertical growth of a dielectric material on a dielectric substrate
TWI540678B (zh) 接觸插塞及其製作方法與半導體元件
JP5308414B2 (ja) 半導体デバイスおよびその構造体の製造方法
TWI694501B (zh) 防止銅擴散的介電/金屬阻障集成
US20090087981A1 (en) Void-free copper filling of recessed features for semiconductor devices
JP2008532271A (ja) 原子層堆積のための表面のプラズマ前処理
TW200834815A (en) Interconnect structure and method of manufacturing a damascene structure
TW200303599A (en) Manufacturing method of semiconductor device
US11170992B2 (en) Area selective deposition for cap layer formation in advanced contacts
KR102545882B1 (ko) 역행 프로파일들을 갖는 리세스된 피처들을 보이드 없이 충전하는 방법
US10825720B2 (en) Single trench damascene interconnect using TiN HMO
US6828236B2 (en) Method for forming silicide wires in a semiconductor device
US6876078B2 (en) Semiconductor interconnection structure with TaN and method of forming the same
US20050184288A1 (en) Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
KR100667905B1 (ko) 반도체 소자의 구리 금속배선 형성방법
JP4457884B2 (ja) 半導体装置
KR101103550B1 (ko) 반도체 소자의 금속배선 형성방법
JP2015133382A (ja) 半導体装置の製造方法
KR20040051189A (ko) 루테늄 비트라인을 구비하는 반도체 소자 및 그의 제조 방법
JP2009266999A (ja) 半導体装置、およびその製造方法
KR102553120B1 (ko) 레트로그레이드 리세스된 피처를 충전하는 방법
KR20040001993A (ko) 구리 금속 배선 형성방법 및 이를 이용한 반도체 소자의다층 배선 형성방법
KR100464652B1 (ko) 반도체 소자의 캐패시터 형성방법
KR20050097060A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000