TWI745558B - 半導體封裝、半導體裝置及半導體裝置之製造方法 - Google Patents

半導體封裝、半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TWI745558B
TWI745558B TW107107816A TW107107816A TWI745558B TW I745558 B TWI745558 B TW I745558B TW 107107816 A TW107107816 A TW 107107816A TW 107107816 A TW107107816 A TW 107107816A TW I745558 B TWI745558 B TW I745558B
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TW
Taiwan
Prior art keywords
semiconductor package
protrusion
electrodes
electrode
semiconductor
Prior art date
Application number
TW107107816A
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English (en)
Chinese (zh)
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TW201903978A (zh
Inventor
島藤貴行
Original Assignee
日商富士電機股份有限公司
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Publication of TW201903978A publication Critical patent/TW201903978A/zh
Application granted granted Critical
Publication of TWI745558B publication Critical patent/TWI745558B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)
TW107107816A 2017-06-05 2018-03-08 半導體封裝、半導體裝置及半導體裝置之製造方法 TWI745558B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-111214 2017-06-05
JP2017111214A JP6984183B2 (ja) 2017-06-05 2017-06-05 半導体パッケージ、半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201903978A TW201903978A (zh) 2019-01-16
TWI745558B true TWI745558B (zh) 2021-11-11

Family

ID=64460337

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107107816A TWI745558B (zh) 2017-06-05 2018-03-08 半導體封裝、半導體裝置及半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US10607906B2 (enExample)
JP (1) JP6984183B2 (enExample)
CN (1) CN108987353B (enExample)
TW (1) TWI745558B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7287085B2 (ja) * 2019-04-18 2023-06-06 富士電機株式会社 組立冶具セットおよび半導体モジュールの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020043711A1 (en) * 2000-06-08 2002-04-18 Salman Akram Stereolithographic method and apparatus for fabricating stabilizers for flip-chip type semiconductor devices and resulting structures

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147353A (ja) 1989-11-02 1991-06-24 New Japan Radio Co Ltd 表面実装型半導体パッケージ
US5220200A (en) * 1990-12-10 1993-06-15 Delco Electronics Corporation Provision of substrate pillars to maintain chip standoff
US5186383A (en) * 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
US5269453A (en) * 1992-04-02 1993-12-14 Motorola, Inc. Low temperature method for forming solder bump interconnections to a plated circuit trace
JPH07249707A (ja) 1994-03-09 1995-09-26 Fujitsu Ltd 半導体パッケージ
JP2944449B2 (ja) * 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
JP2006210956A (ja) 1997-02-27 2006-08-10 Fujitsu Ltd 半導体装置
US6118182A (en) * 1998-06-25 2000-09-12 Intel Corporation Integrated circuit package with rectangular contact pads
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6531335B1 (en) * 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP3942457B2 (ja) * 2002-02-27 2007-07-11 Ｎｅｃエレクトロニクス株式会社 電子部品の製造方法
US20060108678A1 (en) * 2002-05-07 2006-05-25 Microfabrica Inc. Probe arrays and method for making
CN100587930C (zh) * 2005-05-17 2010-02-03 松下电器产业株式会社 倒装片安装体及倒装片安装方法
US20090085227A1 (en) * 2005-05-17 2009-04-02 Matsushita Electric Industrial Co., Ltd. Flip-chip mounting body and flip-chip mounting method
US20090039495A1 (en) * 2005-10-05 2009-02-12 Sharp Kabushiki Kaisha Wiring substrate and display device including the same
JP2007123443A (ja) * 2005-10-26 2007-05-17 Shinko Electric Ind Co Ltd 回路基板、半導体装置、及び半導体装置の製造方法
JP4752586B2 (ja) * 2006-04-12 2011-08-17 ソニー株式会社 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020043711A1 (en) * 2000-06-08 2002-04-18 Salman Akram Stereolithographic method and apparatus for fabricating stabilizers for flip-chip type semiconductor devices and resulting structures

Also Published As

Publication number Publication date
CN108987353A (zh) 2018-12-11
US20180350705A1 (en) 2018-12-06
JP2018206977A (ja) 2018-12-27
US10607906B2 (en) 2020-03-31
TW201903978A (zh) 2019-01-16
CN108987353B (zh) 2023-10-24
JP6984183B2 (ja) 2021-12-17

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