1249824 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種具被動元件之半導體封裝件，更 詳而言之，係關於一種於模壓作業中防止被動元件與晶片 承載件間產生氣洞之半導體封裝件。 【先前技術】 基於電性及性能上的要求，於一半導體封裝件 (Semiconductor Package)中置有如電容、電阻或電感 等被動元件乃一趨勢。 如第1 ( A)圖所示，係習知具被動元件之半導體封裝 件之剖視圖。如圖所示，在基板丨〇上之一預設位置上形成 ♦ 有一對間隔開的銲墊11，該兩銲墊係分別外露出用以覆蓋 該基板10上之拒銲劑層（Solder Mask Layer) 12;當銲 塾1 1上塗佈適當之錫膏（Solder Paste) 1 3後，即可供一 被動元件1 4之兩端部1 4 〇分別接黏至錫膏1 3上，再予以回 銲銲接（Reflow Soldering)處理，該被動元件14便可藉 錫嘗1 3與銲墊1 1適當地電性連接。 由於錫膏1 3塗佈之量及其經回銲銲接處理後之高度難 以精準控制’加以拒銲劑層丨2之表面亦難以完全平整，故 往往在被動元件14與拒銲劑層丨2間形成空隙（Clearance )1 5，因此’在形成封裝膠體丨6之模壓作業（&丨d丨ng) 4 完成後’在空隙1 5中，若無法為封裝樹脂所充填將因此 產生氣洞（Void) 150，如此，在後續之植球（Solder Ball Implantation)或表面黏著處理（Surface Mounting Processing)時，因高溫之狀態下錫膏13將軟1249824 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to a semiconductor package having a passive component, and more particularly to preventing a passive component from being interposed between a passive component and a wafer carrier during molding operations. A semiconductor package that creates a cavity. [Prior Art] Based on electrical and performance requirements, it is a tendency to have passive components such as capacitors, resistors or inductors in a semiconductor package. As shown in Fig. 1(A), a cross-sectional view of a semiconductor package having a passive component is known. As shown, a pair of spaced apart pads 11 are formed on a predetermined position on the substrate, and the pads are exposed to cover the solder resist layer on the substrate 10 (Solder Mask Layer). 12; After the appropriate solder paste (Solder Paste) 1 3 is applied on the soldering iron 1 1 , the two ends of the passive component 14 are respectively adhered to the solder paste 13 and then applied. The Reflow Soldering process allows the passive component 14 to be electrically connected to the pad 1 1 by soldering. Since the amount of the solder paste 13 and the height after the reflow soldering process are difficult to precisely control, the surface of the solder resist layer 2 is also difficult to be completely flattened, so it is often formed between the passive component 14 and the solder resist layer 2 Clearance 15 5, therefore 'after the molding operation (&丨d丨ng) 4 of forming the encapsulant colloid 6 is completed, 'in the void 15 , if it is not filled for the encapsulating resin, a void (Void) is generated. 150, so, in the subsequent Solder Ball Implantation or Surface Mounting Processing, the solder paste 13 will be soft due to the high temperature.
17296 矽品.ptd 第7頁 1249824 五、發明說明（2) 化，從而在氣洞1 5 0之微小空間中為毛細現象的作用造成 兩相對銲塾1 1形成橋接（B r i dg i n g)，如第1 ( B )圖所示， 錫膏1 3—旦橋接，則造成被動元件1 4的短路，而影響至製 成品的良率。 美國專利第6，5 2 1，9 9 7號案之「可設置被動元件之晶 片承載件」提出一種解決錫膏1 3軟化造成兩相對銲墊形成 橋接問題之方案，如第2圖所示，係於兩相對銲墊1 1間之 拒銲劑層1 2上形成凹部1 2 0，藉由凹部1 2 0之填滿的封裝樹 脂，即可防止因錫膏1 3軟化所造成的橋接現象，惟凹部 1 2 0之形成大小係需以不影響至晶片承載件之導電跡線的 佈設為原則，故會增加圖案化（Pattern)製程上的複雜 度，從而造成製造成本的提高。 因此，如何防止被動元件與基板間產生氣洞因而影響 製成品良率即是待解決的問題。 【發明内容】 鑒於上述習知技術之缺點，本發明之主要目的在於提 供一種具被動元件之半導體封裝件，用以避免該被動元件 與基板間產生氣洞。 為達上揭及其它目的，本發明所提供之具被動元件之 半導體封裝件係包括：一具有一晶片接置區及一環設於該 晶片接置區外以佈設多數導電跡線之導線形成區之晶片承 載件，該導線形成區至少具有一對間隔開之銲墊，用以接 置一被動元件；至少一接置於該晶片接置區内之半導體晶 片，其並與該晶片承載件電性連接；以及一形成該晶片承17296 .品.ptd Page 7 1249824 V. Description of the invention (2), so that in the tiny space of the cavity 150, the effect of the capillary phenomenon causes the two opposing welds 1 1 to form a bridge (B ri dg ing), As shown in Figure 1 (B), the solder paste 13 is bridged, causing a short circuit in the passive component 14 and affecting the yield of the finished product. U.S. Patent No. 6,5 2,9,9,7, "Chip Carriers with Passive Components", proposes a solution to the problem of bridging the two solder pads caused by solder paste 13 softening, as shown in Fig. 2. The recessed portion 1 2 0 is formed on the solder resist layer 1 2 between the two opposing pads 1 , and the encapsulation resin filled by the recess 1 120 prevents the bridging phenomenon caused by the softening of the solder paste 13 However, the formation of the recessed portion 120 is set to a principle that does not affect the conductive traces to the wafer carrier, so that the complexity of the patterning process is increased, resulting in an increase in manufacturing cost. Therefore, how to prevent a gas hole between the passive component and the substrate and thus affect the yield of the finished product is a problem to be solved. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, it is a primary object of the present invention to provide a semiconductor package having a passive component to avoid the creation of a gas hole between the passive component and the substrate. For the purpose of achieving the above, the semiconductor package with passive components provided by the present invention comprises: a wire forming region having a wafer receiving region and a ring disposed outside the wafer receiving region for routing a plurality of conductive traces a wafer carrier having at least one pair of spaced apart pads for receiving a passive component; at least one semiconductor wafer disposed within the wafer receiving region, and electrically coupled to the wafer carrier Sexual connection; and forming a wafer carrier
17296 矽品.ptd 第8頁 1249824 五、發明說明（3) 載件之封裝膠體，用以包覆該半導體晶片及被動元件；其 中，該被動元件設置位置係與模壓作業之封裝樹脂注入方 向成非平行，以供用以包覆半導體晶片與被動元件之封裝 膠體的封裝樹脂順利流通該被動元件底面所形成之空隙， 不致於模壓作業中使被動元件與晶片承載件間產生氣洞， 如此受到高溫軟化之錫膏不致發生橋接現象從而避免被動 元件短路之問題。 其中，該被動元件設置位置與模壓作業之封裝樹脂注 入方向互為垂直。 【實施方式】 ♦ 如第3圖所示，本發明一實施例之晶片承載件2具有一 供晶片接置之晶片接置區2 0及一環設於該晶片接置區2 0外 以佈設多數導電跡線（為求簡化，故未予以圖示）之導線 形成區2 1。於該導線形成區2 1上則塗佈有一拒銲劑層（未 圖示）以將該導電跡線覆蓋，且該導線形成區2 1上並成有 至少一對間隔開之銲墊2 1 0以供一被動元件2 2與之銲接 (詳細於后）。 該對銲墊2 1 0上分別塗佈以習知之錫膏（未圖示） 後，即可供一被動元件2 2之兩端部2 2 0、2 2 1接置於該錫膏 上，然後進行習知之回銲銲接作業，俾使該被動元件2 2藉 錫膏銲接至銲墊上並形成電性藕接關係。該被動元件2 2銲 接至銲墊2 1 0上後，該被動元件2 2之底面對應至該銲墊2 1 0 間之拒銲劑層（未圖示）的部位即與該拒銲劑層部位共同 定義出一空隙，亦即如第1 ( Α)圖所示之空隙1 5，於後續17296 .品.ptd Page 8 1249824 V. INSTRUCTIONS (3) The encapsulant of the carrier is used to cover the semiconductor wafer and the passive component; wherein the passive component is disposed in the direction in which the encapsulating resin is injected into the molding operation. Non-parallel, the encapsulating resin for encapsulating the encapsulant of the semiconductor wafer and the passive component smoothly circulates the gap formed by the bottom surface of the passive component, so that a gas hole is not generated between the passive component and the wafer carrier during the molding operation, and thus is subjected to high temperature. The softened solder paste does not cause bridging and thus avoids the problem of short-circuiting of passive components. Wherein, the passive component is disposed at a position perpendicular to the direction in which the encapsulating resin of the molding operation is injected. [Embodiment] As shown in FIG. 3, a wafer carrier 2 according to an embodiment of the present invention has a wafer connection region 20 for wafer connection and a ring disposed outside the wafer connection region 20 to lay a majority. The wire forming region 21 is a conductive trace (not shown for simplicity). A solder resist layer (not shown) is coated on the wire forming region 21 to cover the conductive trace, and the wire forming region 2 1 is formed with at least one pair of spaced apart pads 2 1 0 For a passive component 2 2 to be soldered (detailed in the back). After the solder pads 2 1 0 are respectively coated with a conventional solder paste (not shown), the two ends 2 2 0 and 2 2 1 of a passive component 2 2 are placed on the solder paste. Then, a conventional reflow soldering operation is performed, and the passive component 22 is soldered to the pad by a solder paste to form an electrical splicing relationship. After the passive component 22 is soldered to the pad 2 10 , the bottom surface of the passive component 22 corresponds to the portion of the solder resist layer (not shown) between the pads 2 10 , that is, the portion of the solder resist layer. Define a gap, that is, the gap 1 5 as shown in the first (Α) diagram.
17296 矽品.ptd 第9頁 1249824 五、發明說明（4) 之模壓作業中，該被動元件2 2位置係與封膠樹脂模流方向 A互為垂直，如此，足以供用以包覆晶片（未圖示）與被 動元件2 2之封裝膠體的封裝樹脂順利流通，使該被動元件 2 2底面所形成之空隙不致於模壓作業中產生氣洞，故在模 壓作業完成時，該空隙間即能為封裝樹脂所充分填充，俾 在續行之植球作業或表面黏著作業進行時，因封裝樹脂充 填並固化於被動元件2 2底面與該拒銲劑層部位所定義出的 空隙中，故受到高溫軟化之錫膏不致發生橋接現象從而避 免被動元件2 2短路之問題。 如第4 ( A)及4 ( B)圖所示者為晶片承載件接置被動 4 元件並進行模壓作業之半導體封裝件的平面圖。如第4 ( A )圖所示，於模壓作業中，若該封膠樹脂模流方向B與被 動元件3 2位置為平行時，由於模流特性會同時從該被動元 件3 2兩邊流過，使用以包覆晶片（未圖示）與被動元件3 2 之封裝膠體的封裝樹脂3將無法順利流通該被動元件3 2底 面所形成之空隙（未圖示），且由於封膠樹脂3同時流入該 晶片承載件及被動元件3 2之間，因平行模流無法使該被動 元件3 2底面所形成之空隙内的空氣被模流推出，而於模壓 作業中產生氣洞3 3 0，如第4 ( B)圖所示。 如第5 ( A)及5 ( B)圖所示者為應用本發明之具被動 元件之晶片承載件進行模壓作業之半導體封裝件的平面 圖。如第5 ( A)圖所示，於模壓作業中，若該封膠樹脂模 流方向C與被動元件4 2位置為垂直時，由於模流流動方向 使該被動元件4 2底面所形成之空隙（未圖示）内的空氣會17296 .品.ptd Page 9 1249824 V. INSTRUCTION INSTRUCTION (4) In the molding operation, the position of the passive component 22 is perpendicular to the mold flow direction A of the sealant resin, so that it is sufficient for coating the wafer (not The package resin of the passive component of the passive component 22 is smoothly circulated, so that the gap formed by the bottom surface of the passive component 2 2 does not cause a cavity in the molding operation, so when the molding operation is completed, the gap can be The encapsulating resin is sufficiently filled, and the encapsulating resin is filled and solidified in the void defined by the bottom surface of the passive component 22 and the solder resist layer portion during the continuous ball-planting operation or the surface adhesive work, and is subjected to high temperature softening. The solder paste does not cause bridging to avoid the problem of short circuit of the passive component 2 2 . As shown in Figures 4 (A) and 4 (B), a plan view of a semiconductor package in which a passive carrier 4 is attached to a wafer carrier and molded. As shown in Fig. 4(A), in the molding operation, if the mold flow direction B of the sealant resin is parallel to the position of the passive element 32, the mold flow characteristics will flow from both sides of the passive element 32 at the same time. The use of the encapsulating resin 3 for encapsulating the encapsulant of the wafer (not shown) and the passive component 3 2 will not smoothly circulate the void (not shown) formed by the bottom surface of the passive component 32, and the encapsulating resin 3 simultaneously flows in. Between the wafer carrier and the passive component 32, the air in the gap formed by the bottom surface of the passive component 32 cannot be pushed out by the mold flow due to the parallel mold flow, and the air hole 3 3 0 is generated in the molding operation. 4 (B) shows the picture. A plan view of a semiconductor package in which a wafer carrier having a passive component of the present invention is subjected to a molding operation as shown in Figs. 5(A) and 5(B). As shown in Fig. 5(A), in the molding operation, if the mold flow direction C of the sealant resin is perpendicular to the position of the passive element 42, the gap formed by the bottom surface of the passive element 4 2 due to the flow direction of the mold flow The air inside (not shown) will
1ΙΒ|ρ 17296石夕品.ptd 第10頁 1249824 五、發明說明（5) 被模流順流推 4 2之封裝膠體 所形成之空隙 形成之空隙， 模壓作業中產 上述之實 用以限定本發 之模流流向而 )關係，其 係，亦即，端 露之精神與技 之修，飾或改變 蓋。 出，使用 的封裝樹 ，並使封 不致使該 生氣洞， 施例僅用 明之可實 言，其與 亦可與該 視實施形 術特徵下 ，均應仍 以包覆晶片（未圖示）與被動元件 脂4將順利流通該被動元件4 2底面 裝樹脂4充填該被動元件4 2底面所 具有被動元件4 2之半導體封裝件於 如第5 ( B)圖所示。 以例釋本發明之特點及功效，而非 施範疇，例如，如第5 ( A)圖所示 被動元件4 2位置不限定為垂直（9 0 被動元件4 2位置呈近似9 0°之關 態而定。故在未脫離本發明上述揭 ，任何運用本發明所揭示者而完成 為本發明下揭之申請專利範圍所涵 ❿1ΙΒ|ρ 17296石夕品.ptd Page 10 1249824 V. Description of the invention (5) The gap formed by the gap formed by the encapsulation colloid of the mold flow is pushed by the mold flow, and the above-mentioned utility is produced in the molding operation to define the mold of the present invention. The relationship flows, and the system, that is, the spirit and skill of the dew, the decoration or the change of the cover. Out, use the encapsulation tree, and make the seal not make the angry hole, the embodiment only uses the obvious, and it can also be coated with the wafer (not shown) The passive component 4 and the passive component 4 will flow smoothly. The passive component 4 2 is filled with a resin 4 to fill the passive component 42. The semiconductor package having the passive component 42 is shown in FIG. 5(B). To exemplify the features and functions of the present invention, rather than the scope of application, for example, as shown in Figure 5 (A), the position of the passive component 42 is not limited to vertical (9 0 passive component 4 2 position is approximately 90 °) Therefore, it is intended that the scope of the invention as disclosed in the present invention is covered by the disclosure of the present invention.
17296石夕品.ptd 第11頁 1249824 圖式簡單說明 【圖式簡單說明】 第1 ( A)及1 ( B)圖係習知具被動元件之半導體封裝 件之剖視圖； 第2圖係美國專利第6，5 2 1，9 9 7號揭露拒銲劑層形成凹 部之具被動元件之半導體封裝件之剖視圖； 第3圖係本發明之具被動元件之半導體封裝件平面示 意圖；以及 第4 ( A)及4 ( B)圖係習知之具被動元件之晶片承載 件進行模壓作業之半導體封裝件平面示意圖；以及 曰曰 第5 ( A)及5 ( B)圖係應用本發明之具被動元件之 片承載件進行模壓作業之半導體封裝件平面示意圖。 10 基 板 11 銲 墊 12 拒 銲 劑 層 120 凹 部 13 錫 膏 14 被 動 元 件 140 端 部 15 空 隙 150, 330 氣 洞 16 封 裝 膠 體 2 晶 片 承 載 件 20 晶 片 接 置區 21 導 線 形 成 區 210 銲 墊 2 2, 3 2, 4 2 被 動 元 件 220, 221 端 部 3, 4 封 裝 樹 脂 A，B，C 封 裝 樹 脂17296石夕品.ptd Page 11 1249824 Schematic description of the drawing [Simple description of the diagram] Sections 1 (A) and 1 (B) are a cross-sectional view of a semiconductor package with passive components; Figure 2 is a US patent a cross-sectional view of a semiconductor package having a passive component in which a solder resist layer is formed into a recess is disclosed in FIG. 6, 5 2 1, 9 9 7; FIG. 3 is a plan view of a semiconductor package having a passive component of the present invention; and a fourth (A) And 4 (B) are schematic plan views of a semiconductor package in which a wafer carrier having a passive component is molded; and FIGS. 5(A) and 5(B) are passive components used in the present invention A schematic plan view of a semiconductor package in which a sheet carrier is subjected to a molding operation. 10 substrate 11 pad 12 solder resist layer 120 recess 13 solder paste 14 passive component 140 end 15 gap 150, 330 cavity 16 encapsulant 2 wafer carrier 20 wafer connection area 21 wire formation area 210 pad 2 2, 3 2, 4 2 passive component 220, 221 end 3, 4 encapsulation resin A, B, C encapsulation resin
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