TWI744768B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI744768B
TWI744768B TW109100703A TW109100703A TWI744768B TW I744768 B TWI744768 B TW I744768B TW 109100703 A TW109100703 A TW 109100703A TW 109100703 A TW109100703 A TW 109100703A TW I744768 B TWI744768 B TW I744768B
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Taiwan
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layer
peeling
carrier
support substrate
resin plate
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TW109100703A
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TW202032737A (zh
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下川一生
田嶋尚之
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日商鎧俠股份有限公司
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    • H—ELECTRICITY
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/10—Removing layers, or parts of layers, mechanically or chemically
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Laminated Bodies (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明之實施形態係關於一種載體及半導體裝置之製造方法。根據一實施形態，載體包含：支持基板；剝離層，其設置於上述支持基板之上；第1密接層，其設置於上述支持基板與上述剝離層之間；及保護層，其設置於上述支持基板與上述第1密接層之間，且較上述剝離層之厚度、及上述第1密接層之厚度更厚。

Description

半導體裝置之製造方法
本發明之實施形態係關於一種載體及半導體裝置之製造方法。
作為新封裝技術，FO-WLP(Fan Out Wafer Level Package，扇出型晶圓級封裝)正在研發當中。FO-WLP中，於支持基板上實施配線之形成、晶片之覆載、密封等安裝步驟後，將密封品自支持基板剝離並加以單片化，至此封裝完成。
對於需要形成高精細配線間距之製品，會使用前工程裝置進行生產，因此所使用之支持基板係玻璃晶圓或矽晶圓。此等兩者於總成本中所占之比例均較高，因此要求支持基板能再利用。
本發明之實施形態提供一種支持基板能再利用之載體及半導體裝置之製造方法。
根據本發明之一實施形態，載體包含：支持基板；剝離層，其設置於上述支持基板之上；第1密接層，其設置於上述支持基板與上述剝離層 之間；及保護層，其設置於上述支持基板與上述第1密接層之間，且較上述剝離層之厚度、及上述第1密接層之厚度更厚。
10:載體
11:支持基板
12:保護層
13:第1密接層(密接層)
14:剝離層
15:金屬層
16:第2密接層
20:配線層
21:絕緣層
22:配線
30:半導體元件
31:半導體層
32:片上配線層
33:電極
40:樹脂材料
50:樹脂板
60:半導體裝置
100:治具
101:破斷部
圖1係本發明之實施形態之載體之模式剖視圖。
圖2(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖3(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖4(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖5(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖6(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖7(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖8(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖9(a)、(b)係表示本發明之實施形態之半導體裝置的製造方法之模式剖視圖。
圖10係表示本發明之實施形態之半導體裝置的製造方法之模式俯視 圖。
圖11係本發明之實施形態之載體之模式剖視圖。
以下，參照圖式對本發明之實施形態進行說明。於各圖中，對相同之要素標註相同之符號，並適當省略詳細之說明。再者，圖式係模式性者，各部分之厚度與寬度之關係、各部分之間之大小比例等未必與現實情況相同。又，即便表示相同之部分，有時亦會於不同之圖式中以不同之尺寸或比例等表示。
圖1係本發明之實施形態之載體10之模式剖視圖。
載體10具有支持基板11、保護層12、第1密接層(以下，簡稱密接層)13、剝離層14、金屬層15。保護層12、密接層13、剝離層14及金屬層15依序設置於支持基板11上。
支持基板11例如為矽基板或玻璃基板。支持基板11之厚度大於保護層12之厚度、密接層13之厚度、剝離層14之厚度、及金屬層15之厚度。支持基板11之厚度例如為1mm(毫米)左右。
密接層13之厚度為5μm(微米)以下，更佳為1μm以下，例如為0.5μm左右。剝離層14之厚度為1000nm(奈米)以下，較佳為100nm以下，更佳為10nm以下，例如為數奈米。金屬層15之厚度為5μm以下，更佳為 1μm以下，例如為0.5μm左右。
保護層12之厚度大於密接層13之厚度、剝離層14之厚度、及金屬層15之厚度。保護層12之厚度例如為1μm以上，較佳為5μm以上，更佳為10μm以上。又，保護層12亦可形成於支持基板11之兩面。藉此，能抑制由於保護層12較厚而導致晶圓翹曲之現象。
保護層12由金屬或氧化物構成，該金屬或氧化物含有選自由Al、Ti、V、Cr、Fe、Co、Ni、Cu、Ge、Rb、Y、Zr、Nb、Mo、Rh、Pd、Ag、Sn、Sm、Gd、Dy、Er、Hf、Ta、W、Re、Os、Ir、Pt、Au、Th及U所組成之群之至少一種元素。或者，保護層12為樹脂層。
密接層13與金屬層15亦可使用含有與保護層12相同之金屬之材料。又，密接層13至少為1層，亦可形成為2層以上。例如，密接層13可構成為包含由與剝離層14之密接性較高之材料構成之層、及由與保護層12之密接性較高之材料構成之層，藉此提高夾著密接層13之層構造之密接性。金屬層15同樣地，至少為1層，亦可形成為2層以上。
剝離層14例如含有碳作為主成分。密接層13提高了保護層12與剝離層14之間之密接性，例如為金屬層。
金屬層15例如作為鍍覆用晶種層而發揮功能。又，金屬層15亦作為覆蓋剝離層14之表面從而保護剝離層14之表面免受污染等之覆蓋層而發 揮功能。
於保護層12由含有金屬之材料構成之情形時，若採用例如鍍覆法形成，則容易厚膜化。或者，保護層12亦可採用濺鍍法或蒸鍍法形成。
若使保護層12之TTV(Total Thickness Variation，總厚度變化)為10μm以下，較佳為5μm以下，更佳為1μm以下，則於載體10上形成配線時便可無需分級切削。
由於剝離層14之厚度為奈米級，因此保護層12之表面粗糙度(例如Ra)為0.1μm以下，較佳為0.01μm以下，更佳為0.001μm以下。又，亦可於成膜出保護層12後對其進行表面研磨，從而確保所要求之TTV、Ra。
於保護層12為樹脂層之情形時，可採用壓縮成形、轉注成形、噴墨成形等方法形成熱塑性樹脂、熱硬化性樹脂。於此種情形時，同樣地，可於成膜出樹脂層後對其進行表面研磨，從而確保所要求之TTV、Ra。
又，保護層12、密接層13、剝離層14及金屬層15可採用例如改變靶之濺鍍法，於相同之腔室內連續地形成。
圖2(a)~圖5(b)係表示使用載體10之半導體裝置之製造方法之模式剖視圖。
首先，如圖2(a)所示，準備上述載體10。再者，於圖2(a)以後之表示製造方法之剖視圖中，省略了圖1所示之密接層13及金屬層15之圖示。
如圖2(b)所示，於載體10上形成配線層20。配線層20具有複數根配線22、及使複數根配線22之間絕緣之絕緣層21。配線22為金屬配線，例如含有Cu。配線22可為單層亦可為複數層。
於圖1所示之金屬層15上形成抗蝕劑。該抗蝕劑係藉由曝光及顯影加以圖案化，而形成鍍覆抗蝕劑。其次，藉由使用金屬層15作為晶種層之鍍覆法，於自鍍覆抗蝕劑露出之金屬層15上形成配線22。繼而，將鍍覆抗蝕劑去除。然後，形成絕緣層21。於需要形成複數層配線22之情形時，要繼續實施於絕緣層21形成通孔之步驟、及形成上層配線22之鍍覆步驟等。
如圖3(a)所示，於配線層20上安裝半導體元件30。半導體元件30具有半導體層31、片上配線層32、電極33。電極33與配線層20之配線22接合，半導體元件30與配線22電性連接。
將半導體元件30安裝至配線層20上後，如圖3(b)所示，以樹脂材料40覆蓋半導體元件30。於配線層20上，形成具有半導體元件30、及覆蓋半導體元件30之樹脂材料40之樹脂板50。
形成樹脂板50後，如圖4(a)所示，使用例如刀等治具100，將剝離層14之一部分破斷。
圖10係圖4(a)之構造體之模式俯視圖。
例如，於圓形晶圓狀態之載體10之外周部未形成樹脂板50。使用治具100於該外周部之一部分形成破斷部101。
藉由治具100，將配線層20、金屬層15、剝離層14及密接層13於厚度方向破斷，治具100之前端到達保護層12。破斷部止於保護層12，未達支持基板11。因此，治具100不會對支持基板11造成損傷。
形成破斷部後，以該破斷部為起點，將支持基板11自樹脂板50剝離。例如，於經由切割膠帶將樹脂板50側固定於平台上之狀態下，自靠近破斷部之側真空吸附支持基板11，藉此將支持基板11剝離。
如圖4(b)所示，支持基板11與樹脂板50以剝離層14為界而分離。例如，剝離層14被分成附於樹脂板50側之部分、及附於支持基板11側之部分。
藉由例如蝕刻，將附於樹脂板50側之配線層20之剝離層14去除。然後，藉由例如蝕刻亦將金屬層15去除。將支持基板11剝離後，如圖5(a)所示，配線層20之與形成有樹脂板50之面為相反側之面露出。藉由電解鍍 覆或無電解鍍覆，於露出於該面之配線22之一部分(焊墊)，形成用以與外部連接之金屬膜。進而，視需要，亦可形成焊球或金屬凸塊。
然後，將樹脂板50及配線層20切斷，如圖5(b)所示，單片化成複數個半導體裝置60。
目前，作為支持基板之剝離方法，研發對剝離層照射雷射進行材料改質而加以剝離之方法、及使用刀等於剝離層形成剝離開端(破斷部)而機械性剝離之方法日益進展。
機械剝離由於不使用高價之雷射裝置，因此基於成本觀點而備受關注，但於形成剝離開端(破斷部)時，支持基板會受到損傷，從而支持基板無法再利用，因此仍有低成本化之課題。
根據本實施形態，支持基板11與剝離層14之間形成有用以擋止形成剝離開端之破斷部所使用之刀刃之前端的保護層12，因此可不損傷支持基板11地將支持基板11剝離。因此，支持基板11可再利用，而可降低工藝成本。
即，將被剝離之支持基板11上殘存之剝離層14、金屬層15去除後，再形成剝離層14及金屬層15，而再次準備圖1所示之載體10。視情況，亦可再形成保護層12及密接層13。或者，保護層12亦可為於對上次使用時留下損傷之表面進行研磨後再利用，而無需再形成。然後，藉由上述步 驟，於上述再製作之載體10上，再次形成樹脂板50。
圖6(a)~圖7(b)係表示使用載體10之半導體裝置之製造方法的又一例之模式剖視圖。
如圖6(a)所示，於載體10之剝離層14上安裝半導體元件30。半導體元件30之片上配線層32與剝離層14對向。
於該例中，亦可去掉剝離層14上之鍍覆用晶種層。再者，亦可形成用以保護剝離層14之表面之覆蓋層(絕緣膜或金屬膜)、或用以黏接、黏貼半導體元件30之樹脂層，以代替鍍覆用晶種層。
將半導體元件30安裝至載體10上後，如圖6(b)所示，以樹脂材料40覆蓋半導體元件30，形成樹脂板50。
然後，以與上述步驟相同之方法，於剝離層14形成破斷部後，以該破斷部為起點，將支持基板11自樹脂板50剝離。此時，同樣地，破斷部止於保護層12，未達支持基板11。
將支持基板11剝離後，如圖7(a)所示，半導體元件30之片上配線層32露出。於該例中，將支持基板11剝離後藉由蝕刻等將形成於剝離層14上之金屬層或樹脂層去除。如圖7(b)所示，於該片上配線層32、及樹脂材料40之片上配線層32側之面，形成配線層20。然後，與上述例同樣地， 單片化成複數個半導體裝置。
圖8(a)~圖9(b)係表示使用載體10之半導體裝置之製造方法的進而又一例之模式剖視圖。
如圖8(a)所示，於載體10之剝離層14上安裝半導體元件30。半導體元件30之安裝使用樹脂材料或焊接材料。半導體元件30之片上配線層32及電極33面向載體10之相反側。
於該例中，亦可省去剝離層14上之鍍覆用晶種層。再者，亦可形成用以保護剝離層14之表面之覆蓋層(絕緣膜或金屬膜)，以代替鍍覆用晶種層。
將半導體元件30安裝至載體10上後，以樹脂材料40覆蓋半導體元件30，形成樹脂板50。其次，對樹脂材料40之表面進行例如研磨後，如圖8(b)所示，半導體元件30之電極33自樹脂材料40露出。
如圖9(a)所示，於樹脂材料40之電極33露出之面，形成配線層20。電極33與配線層20之配線22連接。
然後，以與上述步驟相同之方法，於剝離層14形成破斷部後，以該破斷部為起點，將支持基板11自樹脂板50剝離。此時亦同樣地，破斷部止於保護層12，未達支持基板11。
將支持基板11剝離後之圖9(b)所示之構造體與上述例同樣地，單片化成複數個半導體裝置。
圖11係載體10之又一例之模式剖視圖。
於圖11所示之例中，於支持基板11與保護層12之間設置有第2密接層16。藉由該第2密接層16，能提高支持基板11與保護層12之間之密接性，保護層12本身之材料選擇自由度提升。
再者，若形成較治具100硬之層(例如超硬合金層)作為保護層12，可將保護層12薄化。
對本發明之若干實施形態進行了說明，但該等實施形態僅作為示例提出，並非意欲限定發明之範圍。該等新穎之實施形態可採用其他各種形態實施，於不脫離發明主旨之範圍內，可進行各種省略、替換、變更。該等實施形態及其變化皆包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其等同之範圍內。
相關申請案
本申請案基於2019年2月20日提出申請之先行之日本專利申請案第2019-28074號的優先權之利益，且要求該利益，其全部內容藉由引用包含於此。
10:載體
11:支持基板
12:保護層
13:第1密接層(密接層)
14:剝離層
15:金屬層

Claims (4)

  1. 一種半導體裝置之製造方法，其包含如下步驟：準備載體，該載體具有支持基板、設置於上述支持基板之上之剝離層、及設置於上述支持基板與上述剝離層之間之保護層；於上述剝離層上，形成具有半導體元件、及覆蓋上述半導體元件之樹脂材料之樹脂板；於上述載體形成破斷部，該破斷部將上述剝離層於厚度方向破斷，到達上述保護層但未達上述支持基板；及以上述破斷部為起點，將上述支持基板自上述樹脂板剝離；上述載體具有設置於上述剝離層上之金屬層，該製造方法進而包含如下步驟：於上述剝離層上，形成包含將上述金屬層圖案化而形成之配線之配線層；上述樹脂板形成於上述配線層上。
  2. 一種半導體裝置之製造方法，其包含如下步驟：準備載體，該載體具有支持基板、設置於上述支持基板之上之剝離層、及設置於上述支持基板與上述剝離層之間之保護層；於上述剝離層上，形成具有半導體元件、及覆蓋上述半導體元件之樹脂材料之樹脂板；於上述載體形成破斷部，該破斷部將上述剝離層於厚度方向破斷，到達上述保護層但未達上述支持基板；及以上述破斷部為起點，將上述支持基板自上述樹脂板剝離；於自上述樹脂板被剝離之上述支持基板上，再形成上述保護層及上述剝離層，而再次準備上述載體；及於上述再形成之剝離層上再次形成上述樹脂板。
  3. 如請求項1或2之半導體裝置之製造方法，其進而包含如下步驟：於 上述樹脂板之藉由將上述支持基板剝離而露出之面，形成配線層。
  4. 如請求項1或2之半導體裝置之製造方法，其進而包含如下步驟：於上述樹脂板之與受上述載體支持之面相反之面，形成配線層；且於形成上述配線層後，將上述支持基板自上述樹脂板剝離。
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