TWI739399B - 電阻式隨機存取記憶體裝置及其形成方法 - Google Patents

電阻式隨機存取記憶體裝置及其形成方法 Download PDF

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TWI739399B
TWI739399B TW109113288A TW109113288A TWI739399B TW I739399 B TWI739399 B TW I739399B TW 109113288 A TW109113288 A TW 109113288A TW 109113288 A TW109113288 A TW 109113288A TW I739399 B TWI739399 B TW I739399B
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access memory
random access
resistive random
semiconductor fins
semiconductor
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達 陳
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華邦電子股份有限公司
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Abstract

提供一種電阻式隨機存取記憶體裝置。電阻式隨機存取記憶體裝置包括位於基底上的閘極結構，以及源極區和汲極區，其配置於此基底上的此閘極結構之兩側。此源極區包括半導體塊體，且此汲極區包括鄰近此半導體塊體的複數個半導體鰭片，其中此些半導體鰭片彼此被隔離層分隔。電阻式隨機存取記憶體裝置更包括複數個電阻式隨機存取記憶體單元，其中每一個電阻式隨機存取記憶體單元都與此些半導體鰭片的其中之一電性連接。

Description

電阻式隨機存取記憶體裝置及其形成方法
本發明實施例是關於半導體裝置及其形成方法，特別是一種電阻式隨機存取記憶體裝置及其形成方法。
電阻式隨機存取記憶體(resistive random access memory, RRAM)是一種非揮發性記憶體。由於電阻式隨機存取記憶體具有低操作電壓、快速操作時間、多位元儲存、低成本、以及耐用性等諸多優點，近期已被廣泛地開發。一般使用的電阻式隨機存取記憶體之基本結構是由一個電晶體和一個電阻器構成(1T1R)。電阻器的電阻值可由變更施加的偏壓改變，因此裝置可處於高電阻狀態或低高電阻狀態，由此可辨識數位訊號的0或1。
透過增加電容，1TnR結構的電阻式隨機存取記憶體可有效地降低單元(cell)尺寸。然而，潛洩電流(sneak current)可能從一電阻器流到另一電阻器，兩個電阻器連接至同一電晶體時會互相影響，因此損及裝置的可靠度。
雖然現有的電阻式隨機存取記憶體裝置及其形成方法已足以符合原本的目的，但並非在所有方面都令人滿意。 因此，關於電阻式隨機存取記憶體裝置的技術，至今仍有一些問題待克服。
一種電阻式隨機存取記憶體裝置，包括：閘極結構，其位於基底上；源極區和汲極區，其配置於此基底上的此閘極結構之兩側上，其中此源極區包括半導體塊體，且此汲極區包括鄰近此半導體塊體的複數個半導體鰭片，及其中此些半導體鰭片彼此被隔離層分隔；以及複數個電阻式隨機存取記憶體單元，其中每一個此些電阻式隨機存取記憶體單元都與此些半導體鰭片的其中之一電性連接。
一種電阻式隨機存取記憶體裝置之形成方法，包括：提供基底，其具有源極區和鄰近此源極區的汲極區；凹蝕此基底，以形成半導體塊體於此源極區中且形成複數個彼此平行的半導體鰭片於此汲極區中，其中此些半導體鰭片鄰近此半導體塊體；形成閘極結構於此基底上，其中此源極區與此汲極區位於此閘極結構的兩側上；以及形成複數個電阻式隨機存取記憶體單元，其中每一個此些電阻式隨機存取記憶體單元都與此些半導體鰭片的其中之一電性連接。
以下提供電阻式隨機存取記憶體裝置及其形成方法的實施例，特別是具有1TnR結構的電阻式隨機存取記憶體裝置。本發明的一些實施例中，將電阻部分加到電阻式隨機存取記憶體單元間的汲極區，以減少潛洩電流且改善電阻式隨機存取記憶體裝置效能。以下揭露將討論根據本發明實施例所形成電阻式隨機存取記憶體裝置之方法。
第1-3和8圖是根據本發明的一些實施例，繪示出形成第8圖中的電阻式隨機存取記憶體裝置10的例示方法之中間階段的透視圖。此外，第4A、4B、和5-7圖是根據本發明的一些實施例，沿第3圖的直線I-I’，繪示出形成第8圖中的電阻式隨機存取記憶體裝置10的例示方法之中間階段的剖面示意圖。
第1圖是根據本發明實施例，繪示出形成電阻式隨機存取記憶體裝置10之方法的初始步驟。如第1圖所示，提供基底100，其中此基底100具有源極區100S及鄰近此源極區100S的汲極區100D。本發明的一些實施例中，基底100可具有井區(未繪示於第1圖中，而在第4A及4B圖繪示及描述如下)。一些實施例中，井區可為p型井區。其他實施例中，井區可為n型井區。
第2圖繪示出在基底100上形成半導體鰭片120及半導體塊體130。半導體鰭片120形成於基底100的汲極區100D中，並具有各自的隔離層140，位於基底100上的半導體鰭片120之間。半導體塊體130形成於基底100的源極區100S中，且半導體鰭片120鄰近半導體塊體130。相較於具有平面汲極區的電阻式隨機存取記憶體裝置，在具有多鰭片汲極區的電阻式隨機存取記憶體裝置中，其電阻式隨機存取記憶體單元之間的導電路徑較長(舉例而言，導電路徑為U型)，因此可減少潛洩電流。
一些實施例中，相鄰半導體鰭片120之間的鰭片間距D1約50-150nm，例如約100nm。半導體鰭片120的高度H1約250-400nm，例如約300nm。半導體鰭片120的寬度W1約50nm-250nm，例如約150nm。若半導體鰭片120太寬，則電阻可能不夠大而無法減少潛洩電流，若半導體鰭片120太窄，則開關電流(switching current)可能太過限制而效能不佳。
一些實施例中，形成半導體鰭片120和半導體塊體130的方法包括進行蝕刻製程，在基底100的汲極區100D中產生凹入的溝槽，以在汲極區100D中形成彼此平行的半導體鰭片120，由此將半導體塊體130留在源極區100S中。第2圖所示的兩個半導體鰭片120僅是為了例示目的，本發明實施例並不侷限於此。也就是半導體鰭片120的數量可依成品所需的特性調整。
隔離層140形成於相鄰半導體鰭片120間的每一個溝槽中，其在電阻式隨機存取記憶體單元間的汲極區100D作為電阻部分，以減少潛洩電流且改善電阻式隨機存取記憶體裝置10的效能。絕緣材料可透過過度填充(overfill)溝槽而形成，然後將其凹入以露出半導體鰭片120的頂部表面及部分側壁，使半導體鰭片120從剩餘的絕緣材料之間突出，由此形成隔離層140。可實施其他製程及材料以形成半導體鰭片120、半導體塊體130、及隔離層140。雖然圖中並未示出，可沿相鄰半導體鰭片120間的溝槽形成一或多個襯層(liner)。
然後如第3圖所示，形成閘極結構200於基底100上，且源極區100S和汲極區100D位於閘極結構200的兩側。一些實施例中，閘極結構200包覆部分半導體鰭片120且可選擇性地(optionally)覆蓋部分半導體塊體130。在閘極結構200覆蓋部分半導體塊體130的實施例中，閘極結構200中靠近源極區100S的側邊200E可不對準半導體塊體130之側壁，如第3圖所示。在閘極結構200未覆蓋部分半導體塊體130的實施例中，閘極結構200中靠近源極區100S的側邊可對準半導體塊體130之側壁(未繪示)。
一些實施例中，閘極結構200包括閘極介電層與閘極電極(未繪示)。一些實施例中，形成閘極結構200的步驟可包括依序順應地形成閘極介電層的材料層及閘極電極的材料層於基底100上，且在這些材料層上執行圖案化製程，以形成閘極結構200於基底100的汲極區100D之一部分上並可選地形成閘極結構200於基底100的源極區100S之一部分上。
第4A圖是沿第3圖的直線I-I’所繪示的剖面示意圖。如4A圖所示，在半導體鰭片120上執行多道佈植製程，以形成輕摻雜區120A於半導體鰭片120的下方部分及重摻雜區120B於半導體鰭片120的上方部分。由於輕摻雜區120A的電阻大於重摻雜區120B的電阻，潛洩電流可被局限在重摻雜區120B中，因此可阻礙電阻式隨機存取記憶體單元間的潛洩電流。
如前所提及，基底100可具有井區102。一些實施例中，藉由調整輕摻雜區120A之佈植製程參數，半導體鰭片120的底部可延伸至井區102中或與井區102隔開。舉例而言，當輕摻雜區120A之佈植製程能量夠大，使所形成的輕摻雜區120A延伸超過半導體鰭片120之底部，則井區102與半導體鰭片120之底部隔開，如第4A圖所示。反之則輕摻雜區120A無法到達半導體鰭片120之底部，且半導體鰭片120延伸至井區102中，如第4B圖所示。其他實施例中，在形成半導體鰭片120的期間，透過形成更深的溝槽，半導體鰭片120之底部可延伸至井區102中。
井區102的導電型態(conductivity type)和輕摻雜區120A及重摻雜區120B的導電型態相反。此實施例中，基底100的井區102是p型，且形成輕摻雜區120A及重摻雜區120B是透過佈植n型摻質，例如P或As，至基底100的汲極區100D中。其他實施例中，基底100的井區102是n型，且形成輕摻雜區120A及重摻雜區120B是透過在基底100中佈植p型摻質，例如B。
一些實施例中，輕摻雜區120A的厚度T1約150-250nm，例如約200nm，且其電阻大於100k歐姆。重摻雜區120B的厚度T2約50-150nm，例如約100nm，且其電阻小於1000歐姆。輕摻雜區120A與重摻雜區120B之深度比約1-3，例如約2。一些實施例中，在半導體鰭片120上執行第一佈植製程，以形成輕摻雜區120A於半導體鰭片120的下方部分。第一佈植製程之能量約50-300keV，例如150keV。第一佈植製程所使用的劑量約1x1015 cm‑2 -1x1017 cm‑2 ，例如約1x1016 cm‑2 。一些實施例中，在半導體鰭片120上執行第二佈植製程，以形成重摻雜區120B於半導體鰭片120的上方部分。第二佈植製程之能量約30-200keV，例如100keV。第二佈植製程所使用的劑量約1x1017 -1x1019 cm‑2 ，例如約1x1017 cm‑2 。如此處所述，輕摻雜區120A的形成是在重摻雜區120B的形成之前，但本發明實施例並不侷限於此。舉例而言，形成重摻雜區120B的佈植製程可在形成輕摻雜區120A之前執行，然後執行其他佈植製程以形成輕摻雜區120A。
雖然圖中未繪示，可在源極區100S上執行額外的佈植製程以摻雜半導體塊體130。源極區100S的導電型態和汲極區100D的導電型態相同。此實施例中，基底100的源極區100S是n型，且半導體塊體130之摻雜是透過佈植n型摻質，例如P或As。其他實施例中，基底100的源極區100S是p型，且半導體塊體130之摻雜是透過佈植p型摻質，例如B。額外的佈植製程之能量約30 -200keV，例如100keV。額外的佈植製程所使用的劑量約1x1015 -1x1018 cm‑2 ，例如約1x1016 cm‑2 。如此處所述，源極區100S之佈植是在汲極區100D之佈植後，但本發明實施例並不侷限於此。舉例而言，源極區100S之佈植可在汲極區100D之佈植前執行。
第5圖繪示出形成電阻式隨機存取記憶體裝置10的後續製程，此裝置是以第4A圖之結構延伸。應注意的是，也可使用第4B圖之結構形成電阻式隨機存取記憶體裝置10。接著參照第5圖，形成介電層150於隔離層140上，且介電層150覆蓋半導體鰭片120。如第6圖所示，形成接觸件開口160於介電層150中，其中接觸件開口160延伸至半導體鰭片120的重摻雜區120B中，但未延伸至輕摻雜區120A中。一些實施例中，接觸件開口160可具錐形的下方部分，也就是接觸件開口160在半導體鰭片120的重摻雜區120B中具有傾斜側壁，使形成於接觸件開口160中的接觸件180可與半導體鰭片120邊端接觸(edge-contacted) (未繪示於第6圖中，而在第7圖繪示及描述如下)，其有助於消除電流轉彎(current bending)，由此改善電阻式隨機存取記憶體裝置10之效能(以下將討論細節)。
一些實施例中，透過圖案化製程，可形成接觸件開口160於介電層150及半導體鰭片120的重摻雜區120B中。一些實施例中，藉由微影製程，可形成相應接觸件開口160的具開口之圖案化光阻層(未繪示)於介電層150上，然後可執行蝕刻製程，將圖案化光阻層(未繪示)之開口所露出的部分介電層150移除，以暴露半導體鰭片120之頂部表面。然後在半導體鰭片120之頂部表面執行濕蝕刻製程，例如晶向(crystallographic)蝕刻製程，以形成接觸件開口160。一些實施例中，濕蝕刻製程的蝕刻劑包括KOH。一些實施例中，如第6圖所示，於晶向蝕刻製程期間，在半導體鰭片120中可形成部分接觸件開口160，其具有不垂直於基底100之頂部表面的刻面(facet)，此頂部表面可相當於基底100之結晶面。舉例而言，接觸件開口160之較低側壁與接觸件開口160之底部表面之間的角度θ約120-150度，例如約135度。舉例而言，半導體鰭片120中的部分接觸件開口160之深度約30-80nm，例如約50nm。從俯視觀點，接觸件開口160可為任何形狀，例如圓形、矩形、或另一適合的形狀。
接著如第7圖所示，沉積導電材料於接觸件開口160中，以形成接觸件180，其中接觸件180的下方部分埋設於半導體鰭片120的重摻雜區120B中。每一個電阻式隨機存取記憶體單元(未繪示於第7圖中，而在第8圖繪示及描述如下)可由各自的接觸件180與相應的半導體鰭片120電性連接。由於在半導體鰭片120中可形成具小平面的部分接觸件開口160，埋設於半導體鰭片120中的接觸件180之下方部分可具有斜邊，使接觸件180得以收集所有電流而無電流轉彎，因此改善驅動電流(driving current)。
之後參照第8圖，為了使圖式清楚，其中未示出介電層150，電阻式隨機存取記憶體單元300對應地形成於接觸件180上。一些實施例中，電阻式隨機存取記憶體單元300可為電阻式隨機存取記憶體堆疊，其包含依序設置的底部電極層、電阻切換層(resistive switching layer)、阻障層、氧交換層、以及頂部電極層。一些實施例中，氧交換層可幫助電阻切換層形成細絲(filament)。具體地說，在施加電壓以形成細絲於電阻切換層中之後，離子化氧原子可儲存於氧交換層中。此外，阻障層可幫助局限氧原子於氧交換層中，且使更多穩定的細絲得以形成於記憶體單元中並使電阻式隨機存取記憶體單元300有更好的細絲再現性(reproducibility)。
參照第8圖，形成位元線400以電性連接相應的電阻式隨機存取記憶體單元300，且形成源極線500以電性連接半導體塊體130。一些實施例中，更包括垂直於閘極結構的複數個位元線。一些實施例中，更包括平行於閘極結構的源極線。本發明所屬技術領域中具有通常知識者皆了解形成位元線400及源極線500的方法，所以此處不重複細節。
如第8圖所示，電阻式隨機存取記憶體裝置10包括位於基底100上的閘極結構200，以及源極區100S和汲極區100D，其配置於此基底100上的此閘極結構200之兩側。此源極區100S包括半導體塊體130，且此汲極區100D包括鄰近此半導體塊體130的複數個半導體鰭片120，其中此些半導體鰭片120彼此被隔離層140分隔。電阻式隨機存取記憶體裝置10更包括複數個電阻式隨機存取記憶體單元300，其中每一個電阻式隨機存取記憶體單元300都與此些半導體鰭片120的其中之一電性連接。具有多鰭片汲極區(也就是半導體鰭片120)的電阻式隨機存取記憶體裝置10中，其電阻式隨機存取記憶體單元300間的導電路徑之電阻遠大於具有平面汲極區的電阻式隨機存取記憶體裝置，因此可減少潛洩電流。
一些實施例中，電阻式隨機存取記憶體裝置10更包括位於半導體鰭片120下方部分的輕摻雜區120A，以及位於半導體鰭片120上方部分的重摻雜區120B，其中輕摻雜區120A的電阻大於100k歐姆。由於輕摻雜區120A的電阻較大，潛洩電流可被局限在重摻雜區120B中，因此可阻礙電阻式隨機存取記憶體單元300間的潛洩電流。
一些實施例中，每一個電阻式隨機存取記憶體單元300都以接觸件180與半導體鰭片120的其中之一電性連接，其中接觸件180的下方部分埋設於半導體鰭片120的重摻雜區120B中。一些實施例中，接觸件180的下方部分具有斜邊，使接觸件180得以收集所有電流而無電流轉彎，因此改善驅動電流。
綜上所述，根據本發明實施例，電阻式隨機存取記憶體裝置包括隔離層，其位於電阻式隨機存取記憶體單元間的汲極區，以形成具多鰭片結構的汲極區，從而減少潛洩電流且改善裝置效能。此外，由於半導體鰭片的輕摻雜區具有大的電阻，潛洩電流可被局限在半導體鰭片的重摻雜區中，因此可阻礙電阻式隨機存取記憶體單元間的潛洩電流。再者，埋設於半導體鰭片中的接觸件180之下方部分具有斜邊，使接觸件180得以收集所有電流而無電流轉彎，因此改善驅動電流。
10:電阻式隨機存取記憶體裝置 100:基底 102:井區 100D:汲極區 100S:源極區 120:半導體鰭片 120A:輕摻雜區 120B:重摻雜區 130:半導體塊體 140:隔離層 150:介電層 160:接觸件開口 180:接觸件 200:閘極結構 200E:側邊 300:電阻式隨機存取記憶體單元 400、BL400:位元線 500、SL500:源極線 D1:鰭片間距 H1:高度 I-I’:直線 T1、T2:厚度 W1:寬度
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。 第1-3圖是根據本發明的一些實施例，繪示出形成電阻式隨機存取記憶體裝置的例示方法之中間階段的示意圖。 第4A和4B圖是根據本發明的不同實施例，沿第3圖的直線I-I’，繪示出形成電阻式隨機存取記憶體裝置的例示方法之中間階段的剖面示意圖。 第5-7圖是根據本發明的一些實施例，沿第3圖的直線I-I’，繪示出形成電阻式隨機存取記憶體裝置的例示方法之中間階段的剖面示意圖。 第8圖是根據本發明的一些實施例，繪示出電阻式隨機存取記憶體裝置的示意圖。
10:電阻式隨機存取記憶體裝置
100:基底
100S:源極區
100D:汲極區
120:半導體鰭片
130:半導體塊體
140:隔離層
180:接觸件
200:閘極結構
300:電阻式隨機存取記憶體單元
BL400:位元線
SL500:源極線

Claims (10)

  1. 一種電阻式隨機存取記憶體(RRAM)裝置，包括：一閘極結構，其位於一基底上；一源極區和一汲極區，其配置於該基底上的該閘極結構之兩側上，其中該源極區包括一半導體塊體，且該汲極區包括鄰近該半導體塊體的複數個半導體鰭片，及其中該些半導體鰭片彼此被一隔離層分隔，其中該些半導體鰭片的寬度為50nm-250nm；以及複數個電阻式隨機存取記憶體單元，其中每一個該些電阻式隨機存取記憶體單元都與該些半導體鰭片的其中之一電性連接。
  2. 如申請專利範圍第1項所述的電阻式隨機存取記憶體裝置，更包括：一輕摻雜區，位於該些半導體鰭片的下方部分；以及一重摻雜區，位於該些半導體鰭片的上方部分。
  3. 如申請專利範圍第2項所述的電阻式隨機存取記憶體裝置，其中該輕摻雜區的電阻大於100k歐姆。
  4. 如申請專利範圍第2項所述的電阻式隨機存取記憶體裝置，其中該輕摻雜區與該重摻雜區之深度比約1-3。
  5. 如申請專利範圍第1項所述的電阻式隨機存取記憶體裝置，其中每一個該些電阻式隨機存取記憶體單元都以一接觸件與 該些半導體鰭片的其中之一電性連接，其中該接觸件的一下方部分埋設於該些半導體鰭片的該重摻雜區中，且該接觸件的該下方部分有一斜邊。
  6. 如申請專利範圍第1項所述的電阻式隨機存取記憶體裝置，其中該基底包括一井區，且其中該些半導體鰭片延伸至該井區中。
  7. 如申請專利範圍第1項所述的電阻式隨機存取記憶體裝置，更包括：垂直於該閘極結構的複數個位元線，其中每一個該些位元線都與該些電阻式隨機存取記憶體裝置的其中之一電性連接；以及平行於該閘極結構的一源極線，其中該源極線與該半導體塊體電性連接。
  8. 一種電阻式隨機存取記憶體裝置之形成方法，包括：提供一基底，其具有一源極區和鄰近該源極區的一汲極區；凹蝕該基底，以形成一半導體塊體於該源極區中且形成複數個彼此平行的半導體鰭片於該汲極區中，其中該些半導體鰭片鄰近該半導體塊體，其中該些半導體鰭片的寬度為50nm-250nm；形成一閘極結構於該基底上，其中該源極區與該汲極區位於該閘極結構的兩側上；以及形成複數個電阻式隨機存取記憶體單元，其中每一個該些電阻式 隨機存取記憶體單元都與該些半導體鰭片的其中之一電性連接。
  9. 如申請專利範圍第8項所述的電阻式隨機存取記憶體裝置之形成方法，更包括：在該些半導體鰭片上執行一第一佈植製程，以形成一輕摻雜區於該些半導體鰭片的一下方部分；以及在該些半導體鰭片上執行一第二佈植製程，以形成一重摻雜區於該些半導體鰭片的一上方部分。
  10. 如申請專利範圍第9項所述的電阻式隨機存取記憶體裝置之形成方法，更包括：形成複數個接觸件於該些半導體鰭片上，其中每一個該些電阻式隨機存取記憶體單元都以該些接觸件與該些半導體鰭片的其中之一電性連接，其中該些接觸件的一下方部分埋設於該些半導體鰭片的該些重摻雜區中，其中形成該些接觸件包括：蝕刻該些半導體鰭片，以形成一接觸件開口於該些半導體鰭片的該重摻雜區中，其中該接觸件開口之一側壁與該接觸件開口之一底部表面之間的一角度為約135度；以及沉積一導電材料於該接觸件開口中，以形成該些接觸件。
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