WO2019005113A1

WO2019005113A1 - Resistive random-access memory including tunnel source access transistor

Info

Publication number: WO2019005113A1
Application number: PCT/US2017/040321
Authority: WO
Inventors: Daniel H. MORRIS; Uygar E. Avci; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on the bitcell transistor's source terminal using epitaxial growth. Accordingly, such RRAM bitcells are referred to herein as having a 1T(D)-1R configuration. As can be understood based on this disclosure, the tunnel diode's resistance is asymmetric with respect to RRAM write voltage. Thus, the tunnel diode optimizes array operations for the 1T(D)-1R bitcells described herein, enabling both control of current compliance in the SET direction and maximization of current in the RESET direction from the same RRAM bitcell. The 1T(D)-1R architecture is compatible with a multitude of RRAM device structures and transistor types, such as NMOS and PMOS configurations. Further, the tunnel diode can be integrated in a MOSFET access transistor without increasing cell layout area.

Description

RESISTIVE RANDOM-ACCESS MEMORY INCLUDING

TUNNEL SOURCE ACCESS TRANSISTOR

BACKGROUND

Resistive memory, such as resistive random-access memory (RRAM or ReRAM), generally includes a two-terminal device in which a comparatively insulating switching layer or medium is positioned between two conductive electrodes. RRAM devices typically consist of one transistor (IT) or one diode (ID) along with one resistor (1R), resulting in 1T-1R or 1D-1R configurations, where the transistor (IT) or diode (ID) is used as an access device for reading and/or writing operations, and the resistor (1R) stores the memory state. Accordingly, the resistor may be considered a memory resistor or a memristor. RRAM typically changes between two different states. Those states include a high-resistance state (HRS), which may be representative of an Off or '0' state, and a low-resistance state (LRS), which may be representative of an On' or T state. A RESET process is used to switch the RRAM device to the HRS using a RESET voltage and a SET process is used to switch the RRAM device to the LRS using a SET voltage. Filamentary RRAM requires an initial forming process whereby a high voltage stress (known as a forming voltage) is applied to the device. Interfacial RRAM does not require such an initial forming process.

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), to name a few. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow between the source and the drain. The source and drain regions of a FET device typically include doped semiconductor material. Generally, p-type doped semiconductor material has a larger hole concentration than electron concentration, where the 'p' refers to the positive charge of the hole, while n-type doped semiconductor material has a larger electron concentration than hole concentration, where the 'n' refers to the negative charge of the electron. Standard dopant used for group IV semiconductor materials, such as Si, Ge, and SiGe, includes boron (B) for p-type (acceptor) dopant and phosphorous (P) or arsenic (As) for n-type (donor) dopant. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate electrode and the channel region. A MOSFET device may also be known as a metal-insulator-semiconductor FET (MISFET) device or an insulated-gate FET (IGFET) device. In instances where the charge carriers of the MOSFET device are electrons, the device is referred to as an n-channel MOSFET ( MOS) device, and in instances where the charge carriers of the MOSFET device are holes, the device is referred to as a p-channel MOSFET (PMOS) device. Complementary MOS (CMOS) structures use a combination of PMOS and NMOS devices to implement digital logic and other integrated circuit functionality.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1A-D illustrate schematic diagrams of example resistive random-access memory (RRAM) bitcells that each include a tunnel source MOSFET and a memristor (memory resistor), in accordance with some embodiments of the present disclosure.

Figure 2 illustrates an example cross-sectional integrated circuit (IC) view of the example

RRAM bitcells of Figures 1A and IC, in accordance with some embodiments of the present disclosure. Figure 2' illustrates a blown-out portion of Figure 2, specifically illustrating a variation to the memristor stack that includes oxygen exchange layers (OELs) between the dielectric layer and each of the electrodes, in accordance with some embodiments. Figure 2" illustrates the blown-out portion of Figure 2', with only the first or bottom OEL between the dielectric layer and the first or bottom electrode, in accordance with some embodiments. Figure 2"' illustrates the blown-out portion of Figure 2', with only the second or top OEL between the dielectric layer and the second or top electrode, in accordance with some embodiments.

Figures 3A-B illustrate perspective views of an example IC including non-planar transistors configured in accordance with the tunnel source MOSFET device of Figure 2, in accordance with some embodiments of the present disclosure.

Figure 4 illustrates a method of forming an RRAM cell including a tunnel source MOSFET, in accordance with some embodiments of the present disclosure.

Figures 5A-H illustrate example schematic diagrams that illustrate SET and RESET operations for different RRAM cell configurations, in accordance with some embodiments of the present disclosure.

Figure 6 illustrates a computing system implemented with RRAM cells and/or IC structures formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is primarily provided to assist in visually differentiating the different features. In short, the figures are provided merely to show example structures. DETAILED DESCRIPTION

The SET operation of RRAM must have precisely controlled maximum current compliance, because excessive current can cause run-away conductive filament formation and break future low-VDD (positive supply voltage) switching of RRAM memory state. In addition, the ratio of current in the SET and RESET operations must be optimized to enable repeatable switching in the presence of high variation and low supply voltages. Current approaches all have limitations with respect to the SET and RESET operations for RRAM. For instance, one current approach utilizes write-driver circuits to control direct current (DC) compliance, such as using write driver in saturation mode or write driver with feedback control to limit write current. However, such write-driver control approaches include parasitic bit line (BL) capacitance that may cause transient current spikes, and such transient current spikes are impossible to control with a write-driver circuit. Further such write-driver control approaches have integrated circuit (IC) area penalties due to their relative increase in array area, which decreases memory density.

Another current approach utilizes word line (WL) control of current compliance, which includes voltage under-drive of WL to control current during the SET operation. However, such WL control approaches do not allow for comparable SET and RESET operations, thereby suffering from increased write latency. Further, such WL control approaches require generation of additional voltage levels, which cost area and power, thereby resulting in a significant performance penalty (e.g., a 2 times degradation in performance). Further still, such WL control approaches are only compatible with specific RRAM device structures and transistor types, such as oxygen exchange layer (OEL) top plus MOS or OEL bottom plus PMOS configurations. Another current approach utilizes a selector diode in place of the access transistor in a 1D-1R RRAM configuration (as opposed to a 1T-1R RRAM configuration). However, in such 1D-1R approaches, the selector diode has current -voltage (I-V) curve and fabrication requirements that are substantially different and more challenging than utilizing an access transistor. Further, such 1D-1R approaches do not work with bipolar RRAM, which is a desired type of RRAM for many applications. Further still, such 1D-1R approaches typically are limited to forming the selector diode in the back end portion of IC fabrication. The aforementioned issues and limitations are further exacerbated as IC elements are scaled down to include smaller and smaller critical dimensions, such as transistor devices including, for example, sub- 100 nanometer (nm) or sub-50 nm gate lengths (dimension between corresponding gate spacers).

Thus and in accordance with various embodiments of the present disclosure, techniques are provided for forming RRAM including a tunnel source access transistor. In some such embodiments, the use of a tunnel source access transistor includes integrating a tunnel diode (also referred to as an Esaki diode) on the bitcell transistor's source terminal using epitaxial growth. Accordingly, such RRAM bitcell s are referred to herein as having a 1T(D)-1R configuration, as the access portion of the bitcell includes a tunnel diode on the transistor's source terminal. As can be understood based on this disclosure, the tunnel diode's resistance is asymmetric with respect to RRAM write voltage. Therefore, the tunnel diode optimizes array operations for the 1T(D)-1R bitcells described herein, enabling both control of current compliance in the SET direction and maximization of current in the RESET direction from the same RRAM bitcell. Further, the tunnel source access transistor's asymmetry provides early current saturation in the conduction direction of the SET operation for robust current compliance during the SET operation. Further still, the 1T(D)-1R bitcells described herein provide high current drive (similar to low threshold voltage) in the RESET operation direction for minimized RESET voltage drop. Further yet, the 1T(D)-1R bitcells described herein provide increased symmetry of the SET and RESET currents, even in in the presence of conflicting requirements of NMOS or PMOS access transistors and/or the conflicting requirement of WL over-drive and under-drive. In other words, the 1T(D)-1R bitcells described herein are compatible with a multitude of RRAM device structures and transistor types, as will be apparent in light of this disclosure.

In some embodiments, the tunnel source access transistors may be tunnel source MOSFET devices. Generally, different transistor types employ different source/drain (S/D) doping schemes, as is known in the semiconductor technology field. For example, standard metal- oxide-semiconductor field-effect transistors (MOSFETs) typically employ source-channel-drain region doping schemes of p-n-p or p-i-p for p-channel MOSFET (PMOS) devices and n-p-n or n- i-n for n-channel MOSFET (NMOS) devices. In such schemes, 'p' represents p-type doping for a given semiconductor material, 'n' represents n-type doping for a given semiconductor material, and represents intrinsic/undoped or nominally undoped semiconductor material, where nominally undoped semiconductor material includes dopant concentrations of less than 1E15, 5E15, or 1E16 atoms per cubic centimeter (cm). Note that when semiconductor material is described as n-type doped, p-type doped, or intrinsic/nominally undoped herein, such description is relative to the net doping of the semiconductor material. For instance, a given semiconductor material (e.g., Si) may include n-type dopant (e.g., P or As for Si) in a concentration of 2E18 atoms per cubic centimeter (cm) and p-type dopant (e.g., B for Si) in a concentration of 1E18 atoms per cubic cm, such that the given semiconductor material is n-type doped as it has a net n- type doping concentration of 1E18 atoms per cubic cm.

As stated above, standard MOSFETs employ similar-type doping in both of the S/D regions of one such device. However, tunnel source MOSFETs, which may also be referred to as Fermi filter FETs (FFFETs), generally include a similar structure as MOSFETs, except that tunnel source MOSFETs include a source region having an additional layer on the typical source region that includes oppositely type doped semiconductor material compared to the remainder of that typical source region. Thus, tunnel source MOSFETs employ source-channel-drain doping schemes of np-n-p or np-i-p for p-channel tunnel source MOSFET devices (or tunnel source PMOS devices) and pn-p-n or pn-i-n for n-channel tunnel source MOSFET devices (or tunnel source NMOS devices). As can be understood based on this disclosure, the pn or np layers of the source region form the tunnel diode portion of the tunnel source MOSFET device, and also represent the 'D' portion of a 1T(D)-1R RRAM bitcell. Also, as can be understood based on this disclosure, the bottom layer of the tunnel source region (or the layer closest to and in physical contact with the channel region) is used as both the typical source region of the MOSFET device and as one of the terminals of the tunnel diode. In addition, the bi-layer source region can be formed using epitaxial growth of the oppositely type doped semiconductor material layers (n- type versus p-type), which allows for the integration of the tunnel diode to enable transistor asymmetry.

Numerous different source, channel, and drain region doping schemes will be apparent in light of this disclosure. Generally, the source, channel, and drain regions may include any suitable semiconductor material, such as group IV and/or group III-V semiconductor material. The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. In the case of group IV semiconductor materials, the group IV material may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic). In the case of group III-V semiconductor material, the group III-V material may be p-type doped using a suitable acceptor (e.g., beryllium, zinc) or n-type doped using a suitable donor (e.g., silicon).

In some embodiments, a given tunnel source MOSFET may include a PMOS doping scheme (e.g., p-n-p or p-i-p) with an additional n-type doped layer on the typical source region of the PMOS device, to form an np-n-p or np-i-p configuration, as previously described. For instance, in an example embodiment, following the electrical flow from source contact to drain contact, such a tunnel source PMOS device may include n-type doped indium arsenide (In As) for the top tunnel source layer, p-type doped Si for the bottom tunnel source layer, n-type doped or intrinsic Si for the channel region, and p-type doped Si for the drain region. Note that use of an InAs/Si diode (or other diodes with similar characteristics) may be desired in some embodiments due to the very high current density in both directions of the diode. Further, using the InAs doping level, a specific ratio of asymmetric resistance can be adjusted. In other embodiments, a given tunnel source MOSFET may include an NMOS doping scheme (e.g., n-p-n or n-i-n) with an additional p-type doped layer on the typical source region of the NMOS device, to form a pn- p-n or pn-i-n configuration, as was also previously described. For instance, in an example embodiment, following the electrical flow from source contact to drain contact, such a tunnel source NMOS device may include p-type doped gallium antimonide (GaSb) for the top tunnel source layer, n-type doped InAs or indium gallium arsenide (InGaAs) for the bottom tunnel source layer, p-type doped or GaAs or InGaAs for the channel region, and n-type doped InAs or InGaAs for the drain region.

In some embodiments, the amount of asymmetric resistance provided from the tunnel diode (which is also referred to herein as the tunnel source region of the tunnel source MOSFET device) can be adjusted based on the materials used and/or the doping concentrations used for the layers of that feature. For instance, in some embodiments, it may be desired to use the same semiconductor material for both layers of the tunnel diode in a homojunction bi-layer tunnel diode source stack, such as the semiconductor material of both layers being Si or the semiconductor material of both layers being GaAs. As can be understood, in such embodiments, one of the layers of the tunnel diode (or the bi-layer tunnel source region) would be p-type doped and the other would be n-type doped. However, in other embodiments, the semiconductor material included in the layers may be compositionally different, such as in the examples described in the preceding paragraph. By way of another example, the semiconductor material of the layers would be compositionally different if one layer included SiGe with 30% Ge concentration and the other layer included SiGe with 60% Ge concentration even though they both include SiGe as the semiconductor material, because the composition of that SiGe is different in each layer. Therefore, bandgap engineering may be utilized as desired by adjusting the semiconductor material of the layers of the tunnel diode, where such bandgap engineering may utilize a heterojunction bi-layer tunnel diode source stack that tries to increase the valence band edge (Ev) difference between the two layers and/or the conduction band edge (Ec) difference between the two layers, for example.

Further, regardless of whether the layers of the tunnel diode (or bi-layer tunnel source region) include the same semiconductor material or compositionally different semiconductor material, the doping concentrations of the two layers may be adjusted as desired to adjust the asymmetric resistance of the tunnel diode. For instance, in some embodiments, one of the layers (e.g., the top or bottom layer) may be doped with relatively lower dopant concentrations (e.g., in the range of 1E18-5E19 atoms per cubic cm), while the other oppositely-type doped layer (e.g., the other of the top or bottom layer) may be doped with relatively higher dopant concentrations (e.g., in the range of 5E19-1E21 atoms per cubic cm). However, in general, in some embodiments, the tunnel diode layers (or the layers of the tunnel source region) may include dopant in concentrations in the range of 1E18-1E21, or higher, depending on the particular configuration. Thus, the specific ratio of asymmetric resistance can be adjusted as desired using material and/or doping engineering, such that numerous material and doping scheme configurations will be apparent in light of this disclosure.

In some embodiments, the 1R component of the 1T(D)-1R RRAM cell configuration may be a memory resistor, which is referred to herein as a memristor. In some such embodiments, the memristor may have a multilayer structure or stack, such as a metal-insulator-metal (MIM) structure, which may also be thought of as a capacitor-dielectric-capacitor structure or electrode- dielectric-electrode structure. In general, the aforementioned insulator or dielectric layer in the memristor multilayer stack may be considered a switching layer that is configured to switch between a high resistance state (HRS) (e.g., a '0' or Off state) and a low resistance state (LRS) (e.g., a T or On' state). In some embodiments, the electrodes may include any suitable metal or metal alloy, such as copper, aluminum, tungsten, tantalum (e.g., tantalum or tantalum nitride), and/or titanium (e.g., titanium or titanium nitride), to provide a few examples. In some embodiments, the electrodes may include one or more noble metals, such as ruthenium, rhodium, palladium, silver, platinum, and/or gold.

In some embodiments, the switching layer or memory dielectric may include any suitable dielectric, such as oxygen and at least one of hafnium, tantalum, titanium, silicon, aluminum, nitrogen, tungsten, zirconium, and/or vanadium, to provide some examples. For instance, the switching layer or memory dielectric may include hafnium oxide, tantalum oxide, titanium oxide, silicon oxide, hafnium tantalum oxide, and/or hafnium aluminum oxide. In some embodiments, the switching layer or memory dielectric may include one or more phase change chalcogenides, such as germanium-antimony-tellurium (GST) and/or silver-indium-antimony- tellurium (AglnSbTe). Thus, in some embodiments, the switching layer or memory dielectric may include at least antimony and tellurium. In some embodiments, the switching layer or memory dielectric may include binary transition metal oxides, such as nickel oxide (NiO) and/or titanium dioxide (Ti0₂), for example. In some embodiments, the switching layer or memory dielectric may include perovskites, such as strontium titanate (SrTi0 ), strontium zirconium titanate (SrZrTi0 ), and/or PCMO (Pr_xCa_yMn0 ), for example.

In some embodiments, the memristor multilayer stack may include one or more oxygen exchange layers (OELs), such as between the bottom or first electrode and the dielectric layer and/or between the top or second electrode and the dielectric layer. Where present, the one or more OELs may be used to increase flexibility in incorporating the other materials in the memristor stack and/or to affect the switching mechanism of the memristor stack (e.g., to help provide a more stable switching mechanism or to provide a bipolar operation versus a unipolar operation). In some embodiments, an included OEL may include hafnium, titanium, tantalum, and/or oxygen, to provide some example materials. For instance, in some embodiments, a given OEL may be hafnium or hafnium oxide, tantalum or tantalum oxide, titanium or titanium oxide, and so forth. In some embodiments, the memristor multilayer stack may be formed at a back end or back-end-of-line (BEOL) IC location, such that it can even be formed above the access transistor (e.g., above the tunnel source access MOSFET device), in some instances. In other embodiments, the memristor multilayer stack may be formed at a front end of front -end-of-line (FEOL) IC location. In still other embodiments, a portion of the memristor multilayer stack may be formed at the front end of the IC and a portion may be formed at the back end of the IC. Numerous configurations and variations for the memristor component of the RRAM bitcell will be apparent in light of this disclosure.

Numerous benefits of using a tunnel source MOSFET as the access device in an RRAM bitcell will be apparent in light of this disclosure. For example, the RRAM cells described herein can enable 1T(D)-1R embedded non- volatile memory (eNVM) RRAM that operates at relatively lower VDD and with increased endurance as compared to standard RRAM cells (e.g., standard 1T-1R or 1D-1R cells). In other words, the tunneling diode of the bitcell is used to beneficially modify the I-V characteristics of a RRAM access transistor, as will be apparent in light of this disclosure. Another benefit of the 1T(D)-1R cells described herein is that they isolate the RRAM from BL capacitance, further reducing transient current spikes. In addition, the RRAM cells described herein enable bit-granular high speed SET/RESET operations. Further, degenerate tunnel diode lowers drain bias of the MOSFET during the RESET operation, resulting in no debiasing plus lower resistance. Further still, for the SET operation, the RRAM cell does not only have higher resistance, but also debiasing effect since it is at the source. Further yet, the RRAM cells are compatible with a multitude of different device structures and transistor types, such as with OEL top + NMOS access transistor or OEL bottom + PMOS transistor configurations, or with any other configuration as will be apparent in light of this disclosure.

In addition, integration of the extra tunnel source region layer into a MOSFET access transistor can be achieved without increasing the cell layout area, as the addition of the oppositely type doped layer can be formed on the typical MOSFET source region in the front end or FEOL IC location, thereby utilizing vertical integration without sacrificing any IC area. Accordingly, the tunnel diode does not require a low off-state current (Ioff) value to protect against sneak paths as the tunnel diode is integrated with the front-end access transistor in a tunnel source MOSFET configuration. Further, standard MOSFET fabrication processing can be utilized to form the RRAM bitcells described herein, as the tunnel source MOSFET devices can add the additional tunnel source layer using epitaxial growth on the typical source MOSFET region (e.g., after the drain region has been masked or via some other suitable technique). Thus, the 1T(D)-1R architecture described herein can be fully integrated in the MOSFET process for no additional area cost. In addition, the use of a tunnel source transistor or MOSFET device may be beneficial for other types of memory, as can be understood based on this disclosure.

Note that, as used herein, the expression "X includes at least one of A or B" refers to an X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A or B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression "X includes A and B" refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where "at least one of those items is included in X. For example, as used herein, the expression "X includes at least one of A, B, or C" refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, or C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression "X includes A, B, and C" refers to an X that expressly includes each of A, B, and C. Likewise, the expression "X included in at least one of A or B" refers to an X that may be included, for example, in just A only, in just B only, or in both A and B. The above discussion with respect to "X includes at least one of A or B" equally applies here, as will be appreciated.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an RRAM cell including a tunnel source transistor, such as a tunnel source MOSFET, as variously described herein. For instance, a cross-section analysis of a bitcell array could be performed to determine whether an asymmetric diode is integrated in the bitcell S/D, as can be understood based on this disclosure. In some embodiments, the techniques and structures described herein may be detected based on the benefits derived therefrom, such as being able to operate an RRAM cell at lower VDD and with increased endurance due to the use of the 1T(D)-1R architecture. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figures 1A-D illustrate schematic diagrams of example RRAM bitcells 100A-D that each include a tunnel source MOSFET and a memristor, in accordance with some embodiments of the present disclosure. As shown in Figures 1A-D, each bitcell or memory cell 100A-D includes a 1T(D)-1R architecture, where the 'D' portion or the tunnel diode portion of the cell is formed such that the access transistor is formed between the corresponding tunnel diode and memristor 170 (in the case of Figures 1 A and 1C) or the tunnel diode is formed between the corresponding access transistor and memristor 170 (in the case of Figures IB and ID). Thus, the bitcell architecture of Figures 1A and 1C may be considered to be 1(D)T-1R configurations, while the bitcell architecture of Figures IB and ID may be considered to be 1T(D)-1R. However, both architectures are referred to generally herein as having a 1T(D)-1R configuration, for ease of description. In any such case, the bitcell includes a tunnel source MOSFET device operatively coupled to a resistor used for memory purposes, which is referred to herein as a memristor. In addition, Figures 1 A and IB illustrate RRAM bitcells 100 A and 100B, respectively, that include MOS access transistors 111, while Figures 1C and ID illustrate RRAM bitcells lOOC and 100D, respectively, that include PMOS access transistors 112. As will be apparent in light of this disclosure, the RRAM cells including a tunnel source access transistor can be formed with a multitude of configurations, in accordance with various embodiments. In some embodiments, the structures and techniques described herein may be used to benefit IC devices/circuits of varying scales, such as those having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

Figure 2 illustrates an example cross-sectional IC view of the example RRAM bitcells of Figures 1 A and IC, in accordance with some embodiments of the present disclosure. As shown, the cross-sectional IC view in Figure 2 is an example implementation of the 1T(D)-1R architecture. In more detail, in the example embodiment of Figure 2, tunnel diode 120 is formed as tunnel source region 220, where the source region 220 has a bi-layer structure that includes a first layer 221 that is one of n-type and p-type doped and a second layer 222 that is the other of n-type and p-type doped, thereby forming the tunnel diode. The opposite type doped layers (where n-type is opposite of p-type) result in a broken band gap based on the p-n or n-p structure, as is known to those having ordinary skill in the art. Further, in the example embodiment of Figure 2, the access transistor (which may be an NMOS device 111 or a PMOS device 112) is formed at the front end or front-end-of-line (FEOL) location 291 of the IC structure and will be described in more detail herein. Further still, in the example embodiment of Figure 2, the memristor 170 is formed as memristor stack 270, which is a metal-insulator-metal (MIM) stack, which will be described in more detail herein. As shown in Figure 2, MIM stack 270 is formed at the back end or back-end-of-line (BEOL) location 292 of the IC structure, in this example embodiment. However, the present disclosure is not intended to be so limited, as the memristor stack 270 (or other structure used for memristor 170) may be formed in the IC FEOL 291, in accordance with some embodiments.

Note that the cross-sectional IC view of Figure 2 is along the channel of the transistor shown, such that the source region, channel region, drain region, and gate stack of the transistor device can all be shown. Also note that the tunnel source region first layer 221 is used as both the source region of the transistor 111 or 112 in the 1T(D)-1R RRAM bitcells of Figures 1A-D and one of the two layers of the tunnel diode 120, as will be apparent in light of this disclosure. The techniques for forming the IC structure of Figure 2 may include any suitable semiconductor device fabrication techniques, such as lithography, etching, deposition, epitaxial growth, hardmasking, cleaning, polishing, planarizing, ion implantation, annealing, and/or any other suitable processes as will be apparent in light of this disclosure.

Substrate 200, in some embodiments, may be: a bulk substrate including group IV semiconductor material (e.g., Si, Ge, SiGe), group III-V semiconductor material, and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material, such that the XOI structure includes the electrically insulating material layer between two semiconductor layers; or some other suitable multilayer structure where the top layer includes one of the aforementioned semiconductor materials (e.g., group IV and/or group III-V semiconductor material). The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. In some embodiments, substrate 200 may be a bulk Si wafer, for example.

In some embodiments, substrate 200 may be doped with any suitable n-type and/or p-type dopant. For instance, in the example case of Figure 2, substrate 200 may be doped with p-type dopant (at least near the top surface of the substrate) in instances where the access tunnel source transistor is an NMOS device 111, such that the channel region 210 of that device is formed using that p-type doped substrate material. As can be understood, the opposite may be true (e.g., substrate 200 may be n-type doped) in instances where the access tunnel source transistor is a PMOS device 112, such that the channel region 210 of that device is formed using that n-type doped substrate material. In the case of a Si substrate, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, substrate 200 may be undoped/intrinsic or nominally doped (such as including a dopant concentration of less than 1E15 atoms per cubic cm), for example. In any such instance, and as is shown in Figure 2, channel region 210 is native to substrate 200. However, in other embodiments, the transistor channel region need not be native to substrate 200, as will be described herein. In some embodiments, substrate 200 may include a surface crystalline orientation described by a Miller index of (100), (110), or (111), or its equivalents, as will be apparent in light of this disclosure.

Although substrate 200, in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers/features for ease of illustration, in some instances, substrate 200 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

The processing to form the example IC structure of Figure 2 may continue with forming a dummy gate stack, such as in embodiments employing a gate last fabrication process flow. However, in the example structure of Figure 2, the final gate stack (including gate dielectric 252 and gate electrode 254) is shown. Formation of a dummy gate stack may include depositing dummy gate dielectric material and dummy gate electrode material, patterning the dummy gate stack, depositing gate spacer material, and performing a spacer etch, in accordance with some embodiments. In some such embodiments, dummy gate dielectric (e.g., dummy oxide material) and dummy gate electrode (e.g., dummy poly-silicon material) may be used for a replacement gate process. Note that side-wall spacers 250 referred to generally as gate spacers (or simply, spacers), would be formed on either side of the dummy gate stack, and such spacers 250 can be used to help determine the channel length and/or to help with replacement gate processes, for example. As can be understood based on this disclosure, the dummy gate stack (and spacers 250) can help define the channel region and source/drain (S/D) regions of each transistor device, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of and adjacent to the channel region. Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, as previously described, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Also note that in some such embodiments, spacers 250 may be formed on both sides of the final gate stack (such as is shown in Figure 2) to help electrically isolate the gate stack and/or to help with subsequent processing.

The final gate stack in this example embodiment includes gate dielectric 252 and gate electrode 254 (between gate spacers 250). Such a final gate stack or structure can be formed regardless of whether a gate first fabrication process flow is employed (e.g., such that the final gate stack is formed prior to the S/D regions being formed) or a gate last fabrication process flow is employed (e.g., such that the final gate stack is formed after the S/D regions have been formed and utilizing a dummy gate stack, as previously described). The processing may include any suitable techniques. For instance, in a gate first flow, the final gate stack may be formed using the techniques described above to form the dummy gate stack. In a gate last flow, the final gate stack may be formed by depositing interlayer dielectric (ILD) material 280, planarizing and/or polishing (e.g., via chemical mechanical polishing/planarization) the structure to reveal the dummy gate stack, removing the dummy gate stack via etching, and replacing that dummy gate stack by depositing the final gate stack materials. In any such embodiments, ILD material 280 may include any desired electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that although ILD material 280 is illustrated as a single feature, it may be formed using multiple layers that may or may not be visually distinguishable (e.g., the same ILD material 280 may be used for each layer and the interfaces may not be readily identified in the end structure). Also note that although the gate dielectric 252 is only shown below gate electrode 254 in the example embodiment of Figure 2, in other embodiments, a given gate dielectric may also be present on one or both sides of its corresponding gate electrode, such that the gate dielectric may also be between the corresponding gate electrode and one or both of the gate spacers, for example.

In a given final gate stack, the gate dielectric 252 may include, for example, any suitable oxide (such as silicon dioxide), high-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when high-k dielectric material is used. The gate electrode 254 may include a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN), for example. Further, in some embodiments, the gate electrode may include gold (Au), copper (Cu), magnesium (Mg), aluminum (Al), and/or nickel (Ni). In some embodiments, the gate dielectric and/or gate electrode may include a multilayer structure of two or more material layers, for example. In some embodiments, the gate dielectric and/or gate electrode may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). In some embodiments, one or more additional layers may be present in the final gate stack. Numerous different gate stack configurations will be apparent in light of this disclosure.

Source and drain regions 220 and 230, respectively, which may be generally referred to herein as source/drain (S/D) regions, of the example IC structure of Figure 2 may be formed using any suitable techniques. For instance, in some embodiments, the S/D regions may be formed by driving dopant into the semiconductor material of the S/D regions, such as via ion implantation. In some embodiments, the material located at the S/D regions may be removed and replaced with the final S/D region material. In some embodiments, the S/D regions may be formed via cladding the S/D regions with the final S/D region material. Thus, the final S/D regions may be formed using various different processing techniques as can be understood based on this disclosure. As the S/D regions are asymmetric in the tunnel source MOSFET, and more specifically, the source region 220 is a tunnel source region that includes a bi-layer structure, where the two layers 221 and 222 of the bi-layer structure are oppositely type doped, the S/D processing includes techniques for forming such asymmetric S/D regions. For instance, in some embodiments, the source region 220 may be processed separately than the drain region 230, where one of the S/D regions is masked to allow processing of the other S/D region, followed by masking the other S/D region to allow processing of the originally masked S/D region. Such masking may be performed using any suitable hardmask material, such as a suitable dielectric material, for example. In some embodiments, at least a portion of the S/D regions may be processed together, such as simultaneously processing the tunnel source region first layer 221 with drain region 230, as they may include the same semiconductor material and dopant, for instance. Numerous different processing techniques for forming tunnel source region 220 and drain region 230 will be apparent in light of this disclosure. In some embodiments, the S/D regions 220 and 230 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as monocrystalline group IV semiconductor material and/or monocrystalline group III-V semiconductor material. For instance, a given S/D region may include at least one of silicon, germanium, gallium, arsenide, indium, and/or aluminum. In some embodiments, a given S/D region may include n- type and/or p-type dopant. Generally, in some embodiments, the dopant may be included in a concentration in the range of 1E17 to 5E22 atoms per cubic cm, for example, and in some embodiments, the dopant may be included in a concentration in the range of 1E18 to 1E21 atoms per cubic cm. Note that the doping concentration described herein is the net doping concentration with reference to a given semiconductor material feature, such as a channel region, source region (or one of the layers of the tunnel source region described herein), or drain region of a transistor. Thus, the doping concentration accounts for both p-type and n-type dopants present in that given semiconductor material feature. For example, if a semiconductor material feature transistor channel region includes 2E18 atoms per cubic cm of p-type dopant and 1E18 atoms per cubic cm of n-type dopant, then the net doping concentration would be p-type in the amount of 1E18 atoms per cubic cm, as there would be a larger hole concentration than electron concentration. To provide another example, if a transistor drain region includes 8E20 atoms per cubic cm of n-type dopant and 2E20 atoms per cubic cm of p-type dopant, then the net doping concentration would be n-type in the amount of 6E20 atoms per cubic cm, as there would be a larger electron concentration than hole concentration. Numerous different doping schemes of the S/D regions 220 and 230 will be described in more detail herein.

In some embodiments, a given S/D region may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the region, such as the grading of a semiconductor material component concentration and/or the grading of the dopant concentration within that region, for example. For instance, in some such embodiments, the dopant concentration included in a given S/D region may be graded such that it is lower near the corresponding channel region and higher near the corresponding S/D contact, which may be achieved using any suitable processing, such as tuning the amount of dopant in the reactant flow (e.g., during an in-situ doping scheme), to provide an example. In the case of the bi-layer source region 220 of the tunnel source MOSFET, such grading may occur in one or both of the layers of that region, such as in layer 221 and/or 222, for example. In some embodiments, a given S/D region may include a multilayer structure that includes at least two compositionally different material layers. In the case of the bi-layer source region 220 of the tunnel source MOSFET, layers 221 and/or 222 may include such a multilayer structure, for example. Note that, in some embodiments, layer 221 may be considered the entirety of the transistor source region, and layer 222 may be considered as simply a layer that is on the source region, such that layer 222 is not a part of the source region of the transistor device, for example.

In some embodiments, one or both of layers 221 and 222 may have a height or thickness (dimension in the Y-axis direction) in the range of 5-10, 5-25, 5-50, 5-100, 5-500, 10-25, 10-40, 10-50, 10-100, 10-500, 25-50, 25-100, 25-500, 50-100, 50-500, or 100-500 nm, or some other suitable range as will be apparent in light of this disclosure. In some embodiments, one or both of layers 221 and 222 may have a height or thickness of at least 5, 10, 15, 20, 25, 30, 40, or 50 nm, or some other suitable minimum threshold value as will be apparent in light of this disclosure. In some embodiments, one or both of layers 221 and 222 may have a height or thickness of at most 10, 15, 20, 25, 30, 40, 50, or 100 nm, or some other suitable maximum threshold value as will be apparent in light of this disclosure. As can be understood, drain region 230 may have the same height/thickness (dimension in the Y-axis direction) as tunnel source region 220 (which includes layers 221 and 222), a greater height/thickness than tunnel source region 220, or a lesser height/thickness than tunnel source region 220. In some embodiments, a given S/D region may be raised such that it extends higher than a corresponding channel region (e.g., in the vertical or Y-axis direction), which is the case for both of the S/D regions 220 and 230 as shown in Figure 2. However, in other embodiments, the top surface of a given S/D region may be level with or lower than the top surface of the corresponding channel region.

Channel region 210 of the example IC structure of Figure 2 may be formed using any suitable techniques. For instance, in some embodiments, the channel region 210 may be formed from the substrate material, and thus, the channel region would be native to the substrate material. This is the case for channel regions 210 in the example structure of Figure 2, as that channel region 210 is native to substrate 200. However, even when channel regions are native to the substrate, modifications may occur, such as doping the substrate material to a desired net doping concentration, for example. In other embodiments, a given channel region may be formed by depositing or growing material above the substrate, where such material may be formed on the substrate or formed in a feature (e.g., a trench, fin-shaped trench, well) after removing a portion of the substrate (e.g., via etch processing) to form that feature. Thus, numerous different channel region materials and configurations can be achieved.

In some embodiments, the channel region 210 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as monocrystalline group IV semiconductor material and/or monocrystalline group III-V semiconductor material. For instance, a given channel region may include at least one of silicon, germanium, gallium, arsenide, indium, and/or aluminum. In some embodiments, the channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) at a dopant concentration in the range of 1E16 to 1E22 atoms per cubic cm, for example, or the channel region may be intrinsic/undoped (or nominally undoped, with a dopant concentration less than 1E15 atoms per cubic cm), depending on the particular configuration. In some embodiments, the channel region 210 may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the feature, such as the grading of a semiconductor material component concentration and/or the grading of the dopant concentration, for example. In some embodiments, the channel region 210 may include a multilayer structure that includes at least two compositionally different material layers (such as is the case for beaded-fin transistor configurations).

As can be seen in Figure 2, channel region 210 is between S/D regions 220 and 230. In other words, the S/D regions 220 and 230 are adjacent to channel region 210. More specifically, the first layer 221 of tunnel source region 220 is directly adjacent to and in physical contact with channel region 210, and drain region 230 is also directly adjacent to and in physical contact with channel region 210, in this example embodiment. However, tunnel source region first layer 221 is between tunnel source region second layer 222 and channel region 210, as shown. As can be understood based on this disclosure, the channel region 210 is at least below the gate stack, in this example embodiment. In other words, the gate stack or structure (including gate dielectric 252 and gate electrode 254) is at least above the channel region 210. For instance, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the stack is formed on three sides as is known to those having ordinary skill in the art. However, if the transistor device were inverted and bonded to what will be the end substrate, then the channel region may be above the gate. Therefore, in general, the gate structure and channel region may include a proximate relationship, where the gate structure is near the channel region such that it can exert control over the channel region in an electrical manner, in accordance with some embodiments. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire/nanoribbon in the channel region (or at least substantially surround each nanowire, such as surrounding at least 70, 80, or 90% of each nanowire). Further still, in the case of a planar transistor configuration, the gate stack may only be above the channel region.

In some embodiments, the gate length, which may be measured as the length or width of the gate electrode 254 in the X-axis direction in Figure 2, may be any suitable length as will be apparent in light of this disclosure. For instance, in some embodiments, the gate length may be in the range of 3-100 nm (e.g., 3-10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20, 10- 30, 10-50, 10-100, 20-30, 20-50, 20-100, or 50-100 nm) or greater, for example. In some embodiments, the gate length may be less than a given threshold, such as less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold as will be apparent in light of this disclosure. In some embodiments, the techniques enable maintaining a desired device performance when scaling to such low thresholds, such as sub- 100, sub-50, sub- 40, sub-30, or sub-20 nm thresholds, as can be understood based on this disclosure. In some embodiments, the gate length may approximate the channel length. However, in other embodiments, the channel length may be less, such as in devices employing source/drain tips or extensions.

Numerous different source, channel, and drain region doping schemes will be apparent in light of this disclosure. In some embodiments, a given tunnel source MOSFET may include a PMOS doping scheme (e.g., p-n-p or p-i-p) with an additional n-type doped layer on the typical source region of the PMOS device, to form an np-n-p or np-i-p configuration, as previously described. For instance, in an example embodiment, a tunnel source PMOS device may include n-type doped indium arsenide (InAs) for tunnel source region second layer 222, p-type doped Si for the tunnel source region first layer 221 , n-type doped or intrinsic Si for the channel region 210, and p-type doped Si for the drain region 230. Note that use of an InAs/Si diode (or other diodes with similar characteristics) may be desired in some embodiments due to the very high current density in both directions of the diode. Further, using the InAs doping level, a specific ratio of asymmetric resistance can be adjusted. In other embodiments, a given tunnel source MOSFET may include an NMOS doping scheme (e.g., n-p-n or n-i-n) with an additional p-type doped layer on the typical source region of the NMOS device, to form a pn-p-n or pn-i-n configuration, as was also previously described. For instance, in an example embodiment, following the electrical flow from source contact to drain contact, such a tunnel source NMOS device may include p-type doped gallium antimonide (GaSb) for the top tunnel source layer, n- type doped InAs or indium gallium arsenide (InGaAs) for the bottom tunnel source layer, p-type doped or GaAs or InGaAs for the channel region, and n-type doped InAs or InGaAs for the drain region.

Note that the layers 221, 222 of the source region 220 and the drain region 230 are patterned to merely visually indicate the different types of doping in the different features. As can be understood based on the patterning, tunnel source region first layer 221 and drain region 230 include the same patterning to indicate that they both include the same type of doping, whether they are both n-type doped or both p-type doped. As can also be understood, tunnel source region second layer 222 includes different and opposite patterning to indicate that the feature 222 includes opposite type doping than the doping type of the aforementioned features

221 and 230. Thus, in some embodiments, if features 221 and 230 are n-type doped, then feature

222 would be p-type doped. Moreover, in such embodiments, channel region 210 may be doped with the same dopant type as feature 222 (which would be p-type doped, in such embodiments) or channel region 210 may be intrinsic/undoped. Such embodiments would be similar to RRAM bitcell 100A of Figure 1 A, for example, as they both include an MOS device in the bitcell. In other embodiments, if features 221 and 230 are p-type doped, then feature 222 would be n-type doped. Moreover, in such embodiments, channel region 210 may be doped with the same dopant type as feature 222 (which would be n-type doped, in such embodiments) or channel region 210 may be intrinsic/undoped. Such embodiments would be similar to RRAM bitcell lOOC of Figure 1C, for example, as they both include a PMOS device in the bitcell.

In some embodiments, the amount of asymmetric resistance provided from the tunnel diode portion of the RRAM bitcell (which includes tunnel source region 220) can be adjusted based on the materials used and/or the doping concentrations used for the layers of that feature. For instance, in some embodiments, it may be desired to use the same semiconductor material for both layers 221 and 222 in a homojunction bi-layer tunnel diode source stack. In some such embodiments, both layers 221 and 222 may be layers of Si or both layers 221 and 222 may be layers of GaAs, to provide a few examples. As can be understood, in such embodiments, one of the layers 221 or 222 would be p-type doped and the other would be n-type doped. However, in other embodiments, the semiconductor material included in the layers 221 and 222 may be compositionally different, such as in the examples described in the preceding paragraph. By way of another example, the semiconductor material of the layers 221 and 222 may be compositionally different by both being layers of SiGe, but where one layer 221 or 222 includes SiGe with 30% Ge concentration and the other layer includes SiGe with 60% Ge concentration. Even though both layers 221 and 222 include SiGe as the semiconductor material in such an example case, because the composition of that SiGe is different in each layer, they are compositionally different semiconductor materials. Therefore, bandgap engineering may be utilized as desired by adjusting the semiconductor material of the layers 221 and 222, where such bandgap engineering may utilize a heterojunction bi-layer tunnel diode source stack that tries to increase the valence band edge (Ev) difference between the two layers and/or the conduction band edge (Ec) difference between the two layers, for example. Note that regardless of whether the semiconductor material of layers 221 and 222 is the same or compositionally different, the semiconductor material of drain region 230 may be selected to be any suitable semiconductor material, which may be the same as one or both of layers 221 and 222 or it may be compositionally different from both layers 221 and 222.

Further, regardless of whether the layers 221 and 222 of the tunnel diode (or bi-layer tunnel source region 220) include the same semiconductor material or compositionally different semiconductor material, the doping levels of the two layers may be adjusted as desired to adjust the asymmetric resistance of the tunnel diode. For instance, in some embodiments, one of the layers 221 or 222 may be doped with relatively lower dopant concentrations (e.g., in the range of 1E18-5E19 atoms per cubic cm), while the other oppositely-type doped layer (e.g., the other of 221 or 222) may be doped with relatively higher dopant concentrations (e.g., in the range of 5E19-1E21 atoms per cubic cm). However, in general, in some embodiments, the tunnel source region layers 221 and 222 may include dopant in concentrations in the range of 1E18-1E21, or higher, depending on the particular configuration. Thus, the specific ratio of asymmetric resistance can be adjusted as desired using material and/or doping engineering, such that numerous material and doping scheme configurations will be apparent in light of this disclosure.

S/D contacts 240 of the example IC structure of Figure 2 may be formed using any suitable techniques. For example, the techniques may include forming one or more layers of interlayer dielectric (ILD) material 280, etching contact trenches above the S/D regions, and depositing the S/D contact material to form the resulting S/D contacts 240. In some embodiments, S/D contact formation may include silicidation, germanidation, III-V-idation, and/or annealing processes, where such processing may be performed, e.g., to form an intervening contact layer before forming the bulk contact metal structure. In the example structure of Figure 2, it can be understood that S/D contacts 240 are in physical contact with and electrically connected to S/D regions 220 and 230. More specifically with respect to S/D region 220, the corresponding S/D contact is in physical contact with layer 222, as shown. In some embodiments, S/D contacts 240 may include aluminum or tungsten, although any suitable conductive metal or metal alloy (or other suitable electrically conductive material) can be used, such as silver, nickel -platinum, or nickel-aluminum, for example. In some embodiments, one or more of the S/D contacts 240 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, S/D contacts 240 may employ low work-function metal material(s) and/or high work-function metal material(s), depending on the particular configuration. In some embodiments, one or more additional layers may be present in the S/D contact regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

The above description of the processing used to form the example IC structure of Figure 2 has been describing features formed in the front end or front-end-of-line (FEOL) of the IC (indicated as 291 in Figure 2). For instance, in this example embodiment, the MOS or PMOS access device and the tunnel diode (or together, the tunnel source MOSFET) is formed at the device level or front end of the IC as shown. The memristor stack 270 (which is representative of the memristor 170 in Figures 1A-D) is shown as being formed above the device level in the back end or back-end-of-line (BEOL) location of the IC (indicated as 292 in Figure 2), which begins when the first metallization layer including interconnects 260 and 261 is formed. Although memristor stack 270 is shown in the example embodiment of Figure 2 as being formed at a back end or BEOL location of the IC (e.g., above at least one interconnect line/level and vertically higher than the tunnel source MOSFET device), the present disclosure is not intended to be so limited. For instance, in some embodiments, the memristor stack 270 may be formed at a front end or FEOL location of the IC, at the same device level (in the Y-axis direction) that the tunnel source MOSFET is formed. In some such embodiments, at least a portion of the processing of memristor 270 may be performed simultaneously with the processing of the tunnel source MOSFET, or the processing may be performed separately. However, in embodiments where the memristor stack 270 is formed at a back end IC location, as is the case with the example structure of Figure 2, a smaller IC footprint may be achieved for the RRAM cell, based on the use of vertical co-integration of the components, particularly where the memristor stack 270 is formed above the tunnel source MOSFET device. Thus, memristor stack 270 may be formed using any suitable techniques, where such techniques are based, at least in part, on the particular memristor stack being employed.

In some embodiments, the memristor includes a multilayer structure or stack, such as a metal-insulator-metal (MIM) structure, which may also be thought of as a capacitor-dielectric- capacitor structure or electrode-dielectric-electrode structure. In general, the aforementioned insulator or dielectric layer in the memristor multilayer stack may be considered a switching layer that is configured to switch between a high resistance state (HRS) (e.g., a '0' or Off state) and a low resistance state (LRS) (e.g., a T or On' state). Further, in some cases, the switching layer or memory dielectric layer may be referred to herein as an intervening layer, as it is located between the first and second electrodes. For instance, in the example embodiment of Figure 2, dielectric layer 275 is an intervening layer between a first or bottom electrode 271 and a second or top electrode 272. Note that although the first electrode 271 and second electrode 272 are arranged as top and bottom electrodes in the example structure of Figure 2 and referred to as such herein, the present disclosure is not intended to be so limited, as the memristor stack 270 may be formed horizontally, such that the major axis of the stack is in the X-axis direction, for example, instead of the Y-axis direction (which is the case in Figure 2). The memristor stack 270 may be formed using any suitable techniques, such as depositing ILD material 280, etching trenches for the included layers, and depositing the materials of the included layers to form the resulting structure shown in Figure 2, for example.

In some embodiments, one or both of the first electrode 271 and second electrode 272 may include any suitable metal or metal alloy, such as copper, aluminum, tungsten, tantalum (e.g., tantalum or tantalum nitride), and/or titanium (e.g., titanium or titanium nitride), to provide a few examples. In some embodiments, the electrodes 271 and/or 272 may include one or more noble metals, such as ruthenium, rhodium, palladium, silver, platinum, and/or gold. Generally, the electrodes 271 and 272 may include any suitable electrically conductive material. In some embodiments, first electrode 271 and second electrode 272 may each have a thickness (the dimension in the Y-axis direction) in the range of 5-500 nm (e.g., in the subrange of 5-25, 5-50, 5-100, 10-50, 10-100, 10-200, 25-250, or 50-500 nm), or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, first electrode 271 and second electrode 272 (and the memristor stack 270, in general) may have a width (the dimension in the X-axis direction) in the range of 10-500 nm (e.g., in the subrange of 10-100, 10-200, 20-250, or 50-500 nm), or any other suitable width, as will be apparent in light of this disclosure. Note that in some embodiments, the layers in memristor stack 270 need not have the same or similar thicknesses and/or widths, despite them being illustrated that way in Figure 2. For instance, in some embodiments, it may be desired to have one of the electrodes be thicker and/or wider than the other to, for example, affect the electrical characteristics of the memristor stack 270.

In some embodiments, the switching layer or memory dielectric 275 (which may be referred to herein as an intervening layer, as it is located between the electrode layers 271 and 272) may include any suitable dielectric, such as oxygen and at least one of hafnium, tantalum, titanium, silicon, aluminum, nitrogen, tungsten, zirconium, and/or vanadium, to provide some examples. For instance, the switching layer or memory dielectric 275 may include hafnium oxide, tantalum oxide, titanium oxide, silicon oxide, hafnium tantalum oxide, and/or hafnium aluminum oxide. In some embodiments, the switching layer or memory dielectric 275 may include one or more phase change chalcogenides, such as germanium-antimony-tellurium (GST) and/or silver-indium-antimony-tellurium (AglnSbTe). Thus, in some embodiments, the switching layer or memory dielectric 275 may include at least antimony and tellurium. In some embodiments, the switching layer or memory dielectric 275 may include binary transition metal oxides, such as nickel oxide (NiO) and/or titanium dioxide (Ti0₂), for example. In some embodiments, the switching layer or memory dielectric 275 may include perovskites, such as strontium titanate (SrTi0 ), strontium zirconium titanate (SrZrTi0 ), and/or PCMO (Pr_xCa_yMn0 ), for example. In some embodiments, switching layer or memory dielectric 275 may have a thickness (dimension in the Y-axis direction) in the range of 0.5-200 nm (e.g., in the subrange of 0.5-5, 0.5-10, 0.5-50, 0.5-100, 1-10, 1-20, 1-50, 1-100, 2-10, 2-20, 2-50, 2-100, 2- 200, 5-25, 5-50, 5-100, 5-200, 10-50, 10-100, 10-200, 20-50, 20-100, 20-200, 50-100, 50-200, or 100-200 nm), or any other suitable thickness as will be apparent in light of this disclosure.

In some embodiments, the memristor stack 270 may include one or more oxygen exchange layers (OELs). Where present, the one or more OELs may be used to increase flexibility in incorporating the other materials in the memristor stack and/or to affect the switching mechanism of the memristor stack (e.g., to help provide a more stable switching mechanism or to provide a bipolar operation versus a unipolar operation). For example, Figure 2' illustrates a blown-out portion of Figure 2, specifically illustrating a variation to the memristor stack 270 that includes OELs 273 and 274 between the dielectric layer 275 and each of the electrodes 271 and 272, in accordance with some embodiments. Further, Figure 2" illustrates the blown-out portion of Figure 2', with only the first or bottom OEL 273 between the dielectric layer 275 and the first or bottom electrode 271, in accordance with some embodiments. Further still, Figure 2"' illustrates the blown-out portion of Figure 2', with only the second or top OEL 274 between the dielectric layer 275 and the second or top electrode 272, in accordance with some embodiments. In some embodiments, OELs 273 and/or 274, where present, may include hafnium, titanium, tantalum, and/or oxygen, to provide some example materials. For instance, in some embodiments, a given OEL may include hafnium or hafnium oxide, tantalum or tantalum oxide, titanium or titanium oxide, and so forth. In some embodiments, a given OEL, when present, may have a thickness (dimension in the Y-axis direction) in the range of 0.5-200 nm (e.g., in the subrange of 0.5-5, 0.5-10, 0.5-50, 0.5-100, 1-10, 1-20, 1-50, 1-100, 2-10, 2-20, 2-50, 2-100, 2- 200, 5-25, 5-50, 5-100, 5-200, 10-50, 10-100, 10-200, 20-50, 20-100, 20-200, 50-100, 50-200, or 100-200 nm), or any other suitable thickness as will be apparent in light of this disclosure.

Although electrode layers 271 and 272, dielectric layer 275, and OELs 273 and 274 are illustrated in Figures 2-2"' as being single layers, one or more of the included layers in the memristor stack 270 may include a multilayer structure that includes multiple material layers. In addition, in some embodiments, one or more of features 271-275 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). Again, the layers included in the multilayer memristor stack 270 may be formed using any suitable techniques, as will be apparent to those having ordinary skill in the art. Numerous configurations and variations for memristor stack 270 will be apparent in light of this disclosure.

In some embodiments, interconnects 260, 261, and 262, which includes vertical interconnect access (VIA) features 261 and 262 may include any suitable electrically conductive material, such as one or more metals and/or metal alloys. For instance, in some embodiments, interconnects 260, 261, and 262 may include copper and/or tungsten, to provide some examples. In some embodiments, the interconnects may be formed using any suitable processing, such as forming one or more layers of ILD material 280, removing portions of the ILD material 280 layer(s) via etch processing, and then depositing the interconnect material to form the resulting structures shown. In some such embodiments, the processing is performed in a layer-by-layer approach moving upward in the positive Y-axis direction. In the example IC structure of Figure 2, VIA 261 electrically connects the S/D contact 240 of the drain region 230 of the tunnel source MOSFET device to the first electrode 271 of the memristor stack 270, as shown. Recall from Figures 1A-D that in some embodiments, the memristor stack 270 may instead be electrically connected to the tunnel source region 220 of the tunnel source MOSFET device. In some embodiments, interconnect 260 and VIA 262 may be electrically connected to a source line and a bit line, respectively, as can be understood based on this disclosure. However, other suitable configurations will be apparent in light of this disclosure.

Figures 3A-B illustrate perspective views of an example IC including non-planar transistors configured in accordance with the tunnel source MOSFET device of Figure 2, in accordance with some embodiments of the present disclosure. Note that although the cross- sectional IC view of Figure 2 may be depicting the tunnel source MOSFET device as having a planar configuration, the view may also be a cross-sectional view along a fin (such as the fin including channel region 310 in Figures 3A-B), such that the IC structure of Figure 2 may be depicting a non-planar MOSFET device. Regardless, Figures 3A-B help illustrate how the tunnel source MOSFET devices described herein may be formed with non-planar configurations. For ease of description, the same last two digits are used to identify similar features between those of the tunnel source MOSFET device of Figure 2 and those of the tunnel source MOSFET devices of Figures 3A-B. However, the features in Figure 2 are listed in the 200s and the features in Figures 3A-B are listed in the 300s. Thus, the previous relevant description with respect to the features of Figure 2 is equally applicable to the similar features of Figures 3A-B. For example, the previous relevant description with respect to substrate 200 is equally applicable to substrate 300, the previous relevant description with respect to tunnel source layers 221 and 222 is equally applicable to tunnel source layers 321 and 322, the previous relevant description with respect to drain region 230 is equally applicable to drain regions 330, the previous relevant description with respect to gate dielectric 252 and gate electrode 254 is equally applicable to gate dielectric 352 and gate electrode 354, and so forth. Further note that the non-planar transistor configurations and the relevant description herein related thereto is equally applicable to tunnel source MOS devices as it is to tunnel source PMOS devices.

Note that as can be seen when comparing the IC structure of Figure 2 and the IC structures of Figures 3A-B, there are differences between the structures, such as the shape of spacers 250 compared to spacers 350, and so forth. Also note that generally, the patterning/shading of any of the features in the figures is not intended to limit the present disclosure in any manner, but merely to assist with visually distinguishing the different features. Further note that the four lines of transistors shown in Figures 3A-B are separated and electrically isolated by shallow trench isolation (STI) regions 305, where such STI material 305 may be formed using any suitable techniques, such as forming fins from the top of substrate 300 via shallow trench recess (STR) processing, depositing the STI material between the fins, and recessing the STI material, for example. In some embodiments, STI material 305 (which may be referred to as an STI layer or STI regions) may include any suitable electrically insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), and/or nitride (e.g., silicon nitride) materials. In some embodiments, the material of STI regions 305 may be selected based on the material of substrate 300. For instance, in the case of a Si substrate, the STI material 305 may be selected to be silicon dioxide or silicon nitride, to provide some examples. Note that ILD layer 380 is shown as transparent in the example structures of Figures 3A-B to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited. Further note that in some cases, ILD material 380 and STI material 305 may not include a distinct interface as shown in Figures 3A-B, particularly where, e.g., the ILD material 380 and STI material 305 are the same dielectric material (e.g., where both are silicon dioxide).

As previously described, Figures 3A-B are provided to illustrate example non-planar transistor configurations that one or more tunnel source MOSFETs of a given RRAM cell can benefit from, in accordance with some embodiments. For instance, a finned MOSFET (or FinFET) is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. Other non- planar transistor configurations will be apparent in light of this disclosure, and such non-planar configurations may be employed to increase gate control, increase drive current, increase S/D contact area (and thereby reduce S/D contact resistance), and/or provide other benefits based on the particular configuration.

Figure 3 A illustrates four different non-planar channel regions, which include native fin channel region 310, replacement material fin channel region 314, beaded-fin channel region 316, and nanowire channel region 318. Note that when a dummy gate is employed, the channel region of the transistor devices may be modified after the dummy gate has been removed via any desired processing. Such processing of a given channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region as desired, forming the channel region into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, forming the channel region into a beaded-fin configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, finned channel region 310 is native to substrate 300 and it may or may not have been processed in any suitable manner, such as being doped in a desired manner (e.g., with intentional dopant opposite of what is typical for the type of device it is). Further, finned channel region 314 includes replacement material that is not native to substrate 300, where such replacement material may have been blanket deposited and formed into the fin shown, formed in a fin-shaped trench, or formed using some other suitable processing as is known to those having ordinary skill in the art.

To provide yet another example, nanowire channel region 318 may have been formed after a dummy gate was removed and the channel regions were exposed, by converting an original finned structure at that location into the nanowires 318 shown using, for example, any suitable techniques. For instance, the original finned channel region may have included a multilayer structure, where one or more of the layers were sacrificial and selective etch processing was performed to remove those sacrificial layers and release the nanowires 318. As shown in Figure 3 A, nanowire channel region 318 includes 2 nanowires (or nanoribbons) in this example case. However, a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration. In some embodiments, a nanowire or nanoribbon may be considered fin-shaped where the gate stack wraps around each fin-shaped nanowire or nanoribbon in a GAA transistor configuration. To provide yet another example, beaded-fin channel region 316 is a hybrid between a finned channel region and a nanowire channel region, where the sacrificial material (shown with grey shading) that may have been completely removed to release nanowires was instead only partially removed to form the resulting beaded- fin structure 316 shown. Such a beaded-fin channel region structure may benefit from, for instance, increased gate control (e.g., compared to a finned channel region structure) while also having, for instance, relatively reduced parasitic capacitance (e.g., compared to a nanowire channel region structure). Therefore, numerous different channel region configurations can be employed in the hybrid circuits described herein.

Figure 4 illustrates a method 400 of forming an RRAM cell including a tunnel source MOSFET, in accordance with some embodiments of the present disclosure. Method 400, in this example embodiment includes providing 402 a substrate, such as substrate 200 or 300 as described herein. Method 400 continues with forming 404 a tunnel source MOSFET device above the substrate, where the tunnel source MOSFET is a hybrid of a MOSFET device and a tunnel diode, such that the device includes a bi-layer source region having a first semiconductor layer (e.g., layer 221) that is one of n-type and p-type doped and a second semiconductor layer (e.g., layer 222) that is the other of n-type and p-type doped. In some embodiments, the tunnel source MOSFET may be 405 an n-channel device (and thus a tunnel source NMOS device) or a p-channel device (and thus a tunnel source PMOS device). Method 400 continues with forming a multilayer memristor stack (e.g., memristor stack 270) above the substrate and including a first electrode (e.g., electrode 271), a second electrode (e.g., electrode 272), and a dielectric layer (e.g., dielectric 275) between the electrodes, where the first electrode is electrically connected to the tunnel source MOSFET (e.g., via its source region or drain region). Method 400 may optionally include forming 408 one or more oxygen exchange layers (OELs) (e.g., 273 and/or 274) when forming 406 the multilayer memristor stack.

In some embodiments, the multilayer memristor stack may be formed in the front end (or FEOL) of the IC structure or in the back end (or BEOL) of the IC structure. As can be understood based on this disclosure, the tunnel source MOSFET and memristor stack form an RRAM cell 409 having a 1T(D)-1R configuration and providing the multitude of benefits described herein. Method 400 may continue with completing 410 IC processing as desired, such as forming other IC devices, forming back end interconnect or metallization lines, and/or any other suitable processing as can be understood based on this disclosure. Note that although the processes of method 400 are shown in a particular order in Figure 4, the present disclosure is not intended to be so limited. For instance, in some embodiments, process 408 may not be performed, process 406 may be performed before or simultaneous with process 404 (e.g., where the memristor stack is formed in the IC front end), and so forth. Numerous variations and configurations will be apparent in light of the present disclosure.

RRAM Cell Operation

Figures 5A-H illustrate example schematic diagrams that illustrate SET and RESET operations for different RRAM cell configurations, in accordance with some embodiments of the present disclosure. In more detail, Figure 5 A illustrates an example SET operation 501 of RRAM bitcell 100 A from Figure 1A that includes an NMOS plus tunnel diode access configuration 503, which may also be considered a tunnel source NMOS access device (or the ' IT(D)' portion of a 1T(D)-1R RRAM architecture). Further, Figure 5B illustrates an example RESET operation 502 of the aforementioned RRAM bitcell 100 A from Figure 1 A. In addition, Figure 5C illustrates an example SET operation 501 of RRAM bitcell lOOC from Figure IC that includes a PMOS plus tunnel diode access configuration 504, which may also be considered a tunnel source PMOS access device (or the ' IT(D)' portion of a 1T(D)-1R RRAM architecture). Further, Figure 5D illustrates an example RESET operation 502 of the aforementioned RRAM bitcell lOOC from Figure IC. In the case of Figures 5E and 5G, example SET operations 501 are shown for the RRAM bitcells 100B and 100D, respectively, while example RESET operations 502 are shown in Figures 5F and 5H, respectively. Recall that bitcells 100B and 100D include the tunnel diode 120 between the NMOS/PMOS device 111/112 and the memristor 170, whereas bitcells 100A and lOOC include the NMOS/PMOS device 111/112 between the tunnel diode 120 and the memristor 170. The previous relevant description of Figures 1A-D, 2, 3A-B, and 4 are equally applicable to the schematic diagrams of Figures 5A-H, and such schematic diagrams are provided to illustrate SET and RESET operations, as well as the benefits of the 1T(D)-1R RRAM cells as variously described herein. As can be understood based on this disclosure, tunnel diode 120 includes asymmetry, such that there is low current in one direction (e.g., in the SET direction, from the small triangle to the big triangle) and high current in the other direction (e.g., in the RESET direction, from the big triangle to the small triangle). In the case of Figure 5 A and 5C, example SET operations 501 are shown for the RRAM bitcells 100 A and lOOC, respectively. As shown, for such SET operations 501, a positive voltage 570 is applied to the bit line (BL) of bitcell 100A, which is electrically connect to the memristor 170 (e.g., to second electrode 272 of memristor stack 270 through VIA 262), while a positive voltage 520 is applied to the source line (SL) of bitcell lOOC, which is electrically connected to the tunnel diode 120 (e.g., through interconnect 260). Wordline (WL) control signal 511/512 provides a control signal to the gate structures of the NMOS device 111/PMOS device 112, where the enabling voltage value for the WL control signal is VDD for the NMOS WL 511 and VSS for the PMOS WL. For bitcell 100A, the other side of the tunnel diode 120 that is the SL is electrically connected to ground 521, while for bitcell lOOC, the other side of the memristor 170 that is the BL is electrically connected to ground 571. Such a SET operation 501 results in the SET current 531 passing through the memristor 170 to switch the state of the memristor 170 (e.g., the state of dielectric layer 275) to a low resistance state (LRS) 541 (or to keep the memristor 170 in the LRS, if it was already set in such a manner). In such instances, the tunnel diode 120 limits the SET current 531, providing improved control over the SET operation 501 for both RRAM bitcell configurations 100 A and lOOC. By way of comparison, standard 1T-1R RRAM bitcells have poor SET current compliance control, particularly for 1T- 1R configurations including a PMOS access transistor. Thus, the 1T(D)-1R architecture described herein can be used to benefit the SET operation of a RRAM cell.

In the case of Figures 5B and 5D, example RESET operations 502 are shown for the

RRAM bitcells 100B and 100D, respectively. As shown, for such RESET operations 502, the BL of the memristor 170 of bitcell 100A is electrically connected to ground 571 (e.g., to second electrode 272 of memristor stack 270 through VIA 262), while the SL of the tunnel diode 120 is electrically connected to ground 521 (e.g., through interconnect 260). WL control signal 511/512 provides a control signal to the gate structures of the NMOS device 111/PMOS device 112. For bitcell 100 A, the other side of the tunnel diode 120 is electrically connected to a positive voltage 520 applied to the SL, while for bitcell lOOC, the other side of memristor 170 is electrically connected to a positive voltage 570 applied to the BL. Such a RESET operation 502 results in the RESET current 532 passing through the memristor 170 to switch the state of the memristor 170 (e.g., the state of dielectric layer 275) to a high resistance state (URS) 542 (or to keep the memristor 170 in the HRS, if it was already set in such a manner). In such instances, the tunnel diode 120 enables use of low transistor VT (threshold voltage) and VDD for increased RESET current and voltage. By way of comparison, standard 1T-1R RRAM bitcells include RESET current that is limited by the source degeneration, particularly for 1T-1R configurations including an NMOS access transistor. Thus, the 1T(D)-1R architecture described herein can be used to benefit the RESET operation of a RRAM cell.

Recall that bitcells 100B and 100D include the tunnel diode 120 between the NMOS/PMOS device 111/112 and the memristor 170, whereas bitcells 100A and lOOC include the NMOS/PMOS device 111/112 between the tunnel diode 120 and the memristor 170. The previous relevant descriptions with respect to Figures 5 A-D are equally applicable to Figures 5E- H. Also note that Figures 5A-H indicate suitable ends of the memristor 170 device for OEL, where present, to be included, in accordance with some embodiments. As shown for bitcell 100 A (Figures 5 A and 5B), it may be desirable to employ optional OEL 574 for the electrode farthest from the NMOS device 111, in accordance with some embodiments. Further, for bitcell lOOC (Figures 5C and 5D), in some embodiments, it may be desirable to employ optional OEL 573 for the electrode nearest to the PMOS device. Further yet, for bitcell 100B (Figures 5E and 5F), in some embodiments, it may be desirable to employ optional OEL 573 for the electrode nearest to the NMOS device 111. Further still, for bitcell 100D (Figures 5G and 5H), in some embodiments, it may be desirable to employ optional OEL 574 for the electrode farthest from the PMOS device 112. The previous relevant description with respect to OELs 273 and 274 is equally applicable to OELs 573 and 574. As can be understood based on this disclosure, employing one or more OELs may be desirable to achieve particular desired configurations, such as OEL top plus NMOS, OEL bottom plus NMOS, OEL top plus PMOS, or OEL bottom plus PMOS configurations, for example. Numerous other benefits of the 1T(D)-1R RRAM cells described herein will be apparent in light of the present disclosure.

Example System

Figure 6 illustrates a computing system 1000 implemented with RRAM cells and/or IC structures formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, RRAM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is a resistive random-access memory (RRAM) cell including a transistor and a multilayer stack. The transistor includes: a channel region; a gate structure at least above the channel region; a source region adjacent the channel region, the source region including a first layer that includes a first semiconductor material that is one of p-type doped and n-type doped, and a second layer on the first layer, the second layer including a second semiconductor material that is the other of p-type doped and n-type doped relative to the first layer; and a drain region adjacent the channel region. The multilayer stack includes: a first electrode electrically connected to one of the source and drain regions of the transistor; a second electrode; and an intervening layer between the first and second electrodes, the intervening layer including dielectric material.

Example 2 includes the subject matter of Example 1, wherein the first semiconductor material is p-type doped and includes silicon, and wherein the second semiconductor material is n-type doped and includes indium and arsenic. Example 3 includes the subject matter of Example 1, wherein the first semiconductor material is n-type doped and includes indium and arsenic, and wherein the second semiconductor material is p-type doped and includes gallium and antimony.

Example 4 includes the subject matter of Example 3, wherein the first semiconductor material further includes gallium.

Example 5 includes the subject matter of Example 1, wherein the first and second semiconductor materials are the same.

Example 6 includes the subject matter of any of Examples 1-4, wherein the first and second semiconductor materials are compositionally different.

Example 7 includes the subject matter of any of Examples 1-6, wherein the drain region includes the first semiconductor material that is the one of p-type doped and n-type doped.

Example 8 includes the subject matter of any of Examples 1-7, wherein the second layer of the source region includes a vertical thickness in the range of 5 to 50 nanometers.

Example 9 includes the subject matter of any of Examples 1-8, wherein the first electrode is electrically connected to the source region of the transistor.

Example 10 includes the subject matter of any of Examples 1-9, wherein the dielectric material includes oxygen and at least one of hafnium, tantalum, titanium, silicon, nickel, or aluminum.

Example 11 includes the subject matter of any of Examples 1-10, wherein the multilayer stack further includes an additional layer between the intervening layer and one of the first and second electrodes, the additional layer including at least one of hafnium, titanium, tantalum, or oxygen.

Example 12 includes the subject matter of any of Examples 1-9, wherein the dielectric material includes antimony and tellurium.

Example 13 includes the subject matter of any of Examples 1-12, wherein the first and second electrodes include at least one of copper, tungsten, tantalum, titanium, aluminum, or ruthenium.

Example 14 includes the subject matter of any of Examples 1-13, wherein the transistor has a non-planar configuration.

Example 15 includes the subject matter of any of Examples 1-14, wherein the multilayer stack is at a back-end-of-line integrated circuit location that is vertically higher than the transistor. Example 16 includes the subject matter of any of Examples 1-15, wherein the multilayer stack is above the one of the source and drain regions of the transistor that is electrically connected to the first electrode.

Example 17 is a computing system including the subject matter of any of Examples 1-16. Example 18 is a resistive random-access memory (RRAM) cell including a transistor, a layer on the source region of the transistor, and a multilayer stack. The transistor includes: a channel region; a gate electrode at least above the channel region; a gate dielectric between the gate electrode and the channel region; a source region adjacent the channel region, the source region including a first semiconductor material that is one of p-type doped and n-type doped; and a drain region adjacent the channel region. The layer on the source region includes a second semiconductor material that is the other of p-type doped and n-type doped relative to the source region. The multilayer stack is vertically higher than the transistor in at least one orientation of the RRAM cell and the multilayer stack includes: a first electrode electrically connected to one of the layer and the drain region; a second electrode; and an intervening layer between the first and second electrodes, the intervening layer including dielectric material.

Example 19 includes the subject matter of Example 18, wherein the first semiconductor material is p-type doped and includes silicon, and wherein the second semiconductor material is n-type doped and includes indium and arsenic.

Example 20 includes the subject matter of Example 18, wherein the first semiconductor material is n-type doped and includes indium and arsenic, and wherein the second semiconductor material is p-type doped and includes gallium and antimony.

Example 21 includes the subject matter of Example 20, wherein the first semiconductor material further includes gallium.

Example 22 includes the subject matter of Example 18, wherein the first and second semiconductor materials are the same.

Example 23 includes the subject matter of any of Examples 18-21, wherein the first and second semiconductor materials are compositionally different.

Example 24 includes the subject matter of any of Examples 18-23, wherein the drain region includes the first semiconductor material that is the one of p-type doped and n-type doped.

Example 25 includes the subject matter of any of Examples 18-24, wherein the layer includes a vertical thickness in the range of 10 to 40 nanometers. Example 26 includes the subject matter of any of Examples 18-25, wherein the first electrode is electrically connected to the layer.

Example 27 includes the subject matter of any of Examples 18-26, wherein the dielectric material includes oxygen and at least one of hafnium, tantalum, titanium, silicon, nickel, or aluminum.

Example 28 includes the subject matter of any of Examples 18-27, wherein the multilayer stack further includes an additional layer between the intervening layer and one of the first and second electrodes, the additional layer including at least one of hafnium, titanium, tantalum, or oxygen.

Example 29 includes the subject matter of any of Examples 18-26, wherein the dielectric material includes antimony and tellurium.

Example 30 includes the subject matter of any of Examples 18-29, wherein the first and second electrodes include at least one of copper, tungsten, tantalum, titanium, aluminum, or ruthenium.

Example 31 includes the subject matter of any of Examples 18-30, wherein the transistor has a non-planar configuration.

Example 32 includes the subject matter of any of Examples 18-31, wherein the intervening layer is configured to switch between one of two resistance states.

Example 33 includes the subject matter of any of Examples 18-32, wherein the multilayer stack is above the one of the source and drain regions of the transistor that is electrically connected to the first electrode.

Example 34 is a mobile computing system including the subject matter of any of Examples 18-33.

Example 35 is a method of forming a resistive random-access memory (RRAM) cell, the method including forming a transistor and a multilayer stack. The transistor includes: a channel region; a gate structure at least above the channel region; a source region adjacent the channel region, the source region including a first layer that includes a first semiconductor material that is one of p-type doped and n-type doped, and a second layer on the first layer, the second layer including a second semiconductor material that is the other of p-type doped and n-type doped relative to the first layer; and a drain region adjacent the channel region. The multilayer stack includes: a first electrode electrically connected to one of the source and drain regions of the transistor; a second electrode; and an intervening layer between the first and second electrodes, the intervening layer including dielectric material.

Example 36 includes the subject matter of Example 35, wherein the multilayer stack is formed at a back-end-of-line integrated circuit location.

Example 37 includes the subject matter of Example 35, wherein the multilayer stack is formed at a front-end-of-line integrated circuit location.

Example 38 includes the subject matter of any of Examples 35-37, wherein the first semiconductor material is p-type doped and includes silicon, and wherein the second semiconductor material is n-type doped and includes indium and arsenic.

Example 39 includes the subject matter of any of Examples 35-37, wherein the first semiconductor material is n-type doped and includes indium and arsenic, and wherein the second semiconductor material is p-type doped and includes gallium and antimony.

Example 40 includes the subject matter of Example 39, wherein the first semiconductor material further includes gallium.

Example 41 includes the subject matter of any of Examples 35-37, wherein the first and second semiconductor materials are the same.

Example 42 includes the subject matter of any of Examples 35-40, wherein the first and second semiconductor materials are compositionally different.

Example 43 includes the subject matter of any of Examples 35-42, wherein the drain region includes the first semiconductor material that is the one of p-type doped and n-type doped.

Example 44 includes the subject matter of any of Examples 35-43, wherein the second layer of the source region includes a vertical thickness in the range of 5 to 50 nanometers.

Example 45 includes the subject matter of any of Examples 35-44, wherein the first electrode is electrically connected to the source region of the transistor.

Example 46 includes the subject matter of any of Examples 35-45, wherein the dielectric material includes oxygen and at least one of hafnium, tantalum, titanium, silicon, nickel, or aluminum.

Example 47 includes the subject matter of any of Examples 35-46, wherein the multilayer stack further includes an additional layer between the intervening layer and one of the first and second electrodes, the additional layer including at least one of hafnium, titanium, tantalum, or oxygen. Example 48 includes the subject matter of any of Examples 35-45, wherein the dielectric material includes antimony and tellurium.

Example 49 includes the subject matter of any of Examples 35-48, wherein the first and second electrodes include at least one of copper, tungsten, tantalum, titanium, aluminum, or ruthenium.

Example 50 includes the subject matter of any of Examples 35-49, wherein the transistor has a non-planar configuration.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. A resistive random-access memory (RRAM) cell comprising:

a transistor including

a channel region,

a gate structure at least above the channel region,

a source region adjacent the channel region, the source region including

a first layer that includes a first semiconductor material that is one of p- type doped and n-type doped and

a second layer on the first layer, the second layer including a second semiconductor material that is the other of p-type doped and n-type doped relative to the first layer, and

a drain region adjacent the channel region; and

a multilayer stack including

a first electrode electrically connected to one of the source and drain regions of the transistor,

a second electrode, and

an intervening layer between the first and second electrodes, the intervening layer including dielectric material.

2. The RRAM cell of claim 1, wherein the first semiconductor material is p-type doped and includes silicon, and wherein the second semiconductor material is n-type doped and includes indium and arsenic.

3. The RRAM cell of claim 1, wherein the first semiconductor material is n-type doped and includes indium and arsenic, and wherein the second semiconductor material is p-type doped and includes gallium and antimony.

4. The RRAM cell of claim 3, wherein the first semiconductor material further includes gallium.

5. The RRAM cell of claim 1, wherein the first and second semiconductor materials are the same.

6. The RRAM cell of claim 1, wherein the first and second semiconductor materials are compositionally different.

7. The RRAM cell of claim 1, wherein the drain region includes the first semiconductor material that is the one of p-type doped and n-type doped.

8. The RRAM cell of claim 1, wherein the second layer of the source region includes a vertical thickness in the range of 5 to 50 nanometers.

9. The RRAM cell of claim 1, wherein the first electrode is electrically connected to the source region of the transistor.

10. The RRAM cell of claim 1, wherein the dielectric material includes oxygen and at least one of hafnium, tantalum, titanium, silicon, nickel, or aluminum.

11. The RRAM cell of claim 1, wherein the multilayer stack further includes an additional layer between the intervening layer and one of the first and second electrodes, the additional layer including at least one of hafnium, titanium, tantalum, or oxygen.

12. The RRAM cell of claim 1, wherein the dielectric material includes antimony and tellurium.

13. The RRAM cell of any of claims 1-12, wherein the first and second electrodes include at least one of copper, tungsten, tantalum, titanium, aluminum, or ruthenium.

14. The RRAM cell of any of claims 1-12, wherein the transistor has a non-planar configuration.

15. The RRAM cell of any of claims 1 -12, wherein the multilayer stack is at a back- end-of-line integrated circuit location that is vertically higher than the transistor.

16. The RRAM cell of any of claims 1-12, wherein the multilayer stack is above the one of the source and drain regions of the transistor that is electrically connected to the first electrode.

17. A computing system comprising the RRAM cell of any of claims 1-12.

18. A resistive random-access memory (RRAM) cell comprising:

a transistor including a channel region,

a gate electrode at least above the channel region,

a gate dielectric between the gate electrode and the channel region, a source region adjacent the channel region, the source region including a first semiconductor material that is one of p-type doped and n-type doped and a drain region adjacent the channel region;

a layer on the source region, the layer including a second semiconductor material that is the other of p-type doped and n-type doped relative to the source region; and a multilayer stack that is vertically higher than the transistor in at least one orientation of the RRAM cell, the multilayer stack including

a first electrode electrically connected to one of the layer and the drain region, a second electrode, and

19. The RRAM cell of claim 18, wherein the first semiconductor material is p-type doped and includes silicon, and wherein the second semiconductor material is n-type doped and includes indium and arsenic.

20. The RRAM cell of claim 18, wherein the first semiconductor material is n-type doped and includes indium and arsenic, and wherein the second semiconductor material is p-type doped and includes gallium and antimony.

21. The RRAM cell of claim 18, wherein the first and second semiconductor materials are the same.

22. The RRAM cell of any of claims 18-20, wherein the first and second semiconductor materials are compositionally different.

23. A method of forming a resistive random-access memory (RRAM) cell, the method comprising:

forming a transistor, the transistor including

a channel region,

a gate structure at least above the channel region, a source region adjacent the channel region, the source region including

a drain region adjacent the channel region; and

forming a multilayer stack, the multilayer stack including

a second electrode, and

24. The method of claim 23, wherein the multilayer stack is formed at a back-end-of- line integrated circuit location.

25. The method of claim 23, wherein the multilayer stack is formed at a front-end-of- line integrated circuit location.