TWI734576B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI734576B TWI734576B TW109126489A TW109126489A TWI734576B TW I734576 B TWI734576 B TW I734576B TW 109126489 A TW109126489 A TW 109126489A TW 109126489 A TW109126489 A TW 109126489A TW I734576 B TWI734576 B TW I734576B
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- Prior art keywords
- semiconductor layer
- layer
- semiconductor
- conductive layer
- conductive
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 318
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 239000012535 impurity Substances 0.000 claims description 64
- 239000003990 capacitor Substances 0.000 description 90
- 230000005540 biological transmission Effects 0.000 description 21
- 230000000052 comparative effect Effects 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000000470 constituent Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
實施形態之半導體裝置具備:半導體基板;第1半導體層,其於與半導體基板之表面交叉之第1方向上與半導體基板之表面對向;第2半導體層,其相較第1半導體層距半導體基板較遠,於第1方向上與第1半導體層對向;第1導電層,其相較第2半導體層距半導體基板較遠,連接於第2半導體層;第3半導體層,其於與第1方向交叉之第2方向上與第2半導體層並排,連接於第1半導體層;及第2導電層,其於第2方向上與第1導電層並排,連接於第3半導體層。第1半導體層、第2半導體層及第3半導體層係將與第1方向及第2方向交叉之第3方向作為長度方向。
Description
本實施形態係關於一種半導體裝置。
已知一種半導體裝置,其具備半導體基板、設置於半導體基板上方之第1半導體層、及設置於第1半導體層上方之第2半導體層,且將該等構成用作電容器。
一實施形態提供一種高速動作之半導體裝置。
一實施形態之半導體裝置具備:半導體基板;第1半導體層,其於與半導體基板之表面交叉之第1方向上與半導體基板之表面對向;第2半導體層,其相較第1半導體層距半導體基板較遠,於第1方向上與第1半導體層對向;第1導電層,其相較第2半導體層距半導體基板較遠,連接於第2半導體層;第3半導體層,其於與第1方向交叉之第2方向上與第2半導體層並排,連接於第1半導體層;及第2導電層,其於第2方向上與第1導電層並排,連接於第3半導體層。第1半導體層、第2半導體層及第3半導體層係將與第1方向及第2方向交叉之第3方向作為長度方向。
根據上述構成,可提供一種高速動作之半導體裝置。
接下來,參照圖式對實施形態之半導體裝置詳細地進行說明。再者,以下實施形態僅為一例,並不意圖限定本發明。
又,於本說明書中,將與半導體基板之表面平行之特定方向稱為X方向,將與半導體基板之表面平行且與X方向垂直之方向稱為Y方向,將與半導體基板之表面垂直之方向稱為Z方向。
又,於本說明書中,有時將沿特定平面之方向稱為第1方向,將沿該特定平面與第1方向交叉之方向稱為第2方向,將與該特定平面交叉之方向稱為第3方向。該等第1方向、第2方向及第3方向可與X方向、Y方向及Z方向中任一方向對應,亦可不對應。
又,於本說明書中,「上」或「下」等表述係以半導體基板為基準。例如,將沿Z方向遠離半導體基板之方向稱為上,將沿Z方向靠近半導體基板之方向稱為下。又,於針對某一構成記述為下表面或下端部之情形時,係指該構成之半導體基板側之面或端部,於記述為上表面或上端部之情形時,係指該構成之與半導體基板相反側之面或端部。又,將與X方向或Y方向交叉之面稱為側面等。
又,於本說明書中,於記述為第1構成「電性連接」於第2構成之情形時,可為第1構成直接連接於第2構成,亦可為第1構成經由配線、半導體構件或電晶體等連接於第2構成。例如於將3個電晶體串聯連接之情形時,即便第2個電晶體為斷開(OFF)狀態,第1個電晶體亦「電性連接」於第3個電晶體。
又,於本說明書中,於記述為第1構成「連接於」第2構成與第3構成「之間」之情形時,有時係指第1構成、第2構成及第3構成串聯連接,且第1構成設置於第2構成及第3構成之電流路徑中。
又,於本說明書中,於記述為電路等使2條配線等「導通」之情形時,例如,有時係指該電路等包含電晶體等,該電晶體等設置於2條配線之間之電流路徑中,該電晶體等成為接通(ON)狀態。
[第1實施形態] 圖1係表示本實施形態之第1構成之記憶系統100之構成例之模式性側視圖。圖2係表示記憶系統100之構成例之模式性俯視圖。為了便於說明,於圖1及圖2中省略了一部分構成。
如圖1所示,第1構成之記憶系統100具備安裝基板MSB、於安裝基板MSB上積層之複數個記憶體晶粒MD、及於記憶體晶粒MD上積層之控制晶粒CD。於安裝基板MSB上表面中之Y方向之端部區域設置有焊墊電極P,其他一部分區域經由接著劑等連接於記憶體晶粒MD之下表面。於記憶體晶粒MD上表面中之Y方向之端部區域設置有焊墊電極P,其他區域經由接著劑等連接於另一記憶體晶粒MD或控制晶粒CD之下表面。於控制晶粒CD上表面中之Y方向之端部區域設置有焊墊電極P。
如圖2所示,安裝基板MSB、複數個記憶體晶粒MD及控制晶粒CD分別具備複數個焊墊電極P。設置於安裝基板MSB、複數個記憶體晶粒MD及控制晶粒CD上之複數個焊墊電極P分別經由接合線B相互連接。
圖3係表示記憶體晶粒MD之構成之模式性俯視圖。於圖3之例中,記憶體晶粒MD具備半導體基板S、設置於半導體基板S上表面之記憶胞陣列MCA、及設置於記憶胞陣列MCA周邊之周邊電路PC。於圖3之例中,於半導體基板S上表面設置有沿X方向排列之2個記憶胞陣列MCA。各記憶胞陣列MCA具備沿Y方向排列之複數個記憶塊MB。又,於周邊電路PC之一部分設置有焊墊電極P。
圖4係表示記憶體晶粒MD之一部分構成之模式性電路圖。如圖4所示,記憶體晶粒MD具備複數個焊墊電極P、連接於該等複數個焊墊電極P之複數個去耦電容器C
D、及連接於該等複數個焊墊電極P之內部電路IC。
複數個焊墊電極P中之一部分連接於傳輸輸入信號及輸出信號之輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…。該等複數個輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…連接於內部電路IC中所包含之未圖示之比較器等。
又,複數個焊墊電極P中之一部分連接於向記憶體晶粒MD中之各構成供給接地電壓VSS之電壓傳輸線W
VSS。電壓傳輸線W
VSS連接於內部電路IC。又,於電壓傳輸線W
VSS與輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之間分別連接有下拉電路PD。下拉電路PD包含並聯連接於電壓傳輸線W
VSS與輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之間之複數個NMOS(N-channel metal oxide semiconductor,N通道金氧半導體)電晶體。
又,複數個焊墊電極P中之一部分連接於向記憶體晶粒MD中之各構成供給驅動電壓VCCQ之電壓傳輸線W
VCCQ。電壓傳輸線W
VCCQ連接於內部電路IC。又,於電壓傳輸線W
VCCQ與輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之間分別連接有提昇電路PU。提昇電路PU包含並聯連接於電壓傳輸線W
VCCQ與輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之間之複數個PMOS(P-channel metal oxide semiconductor,P通道金氧半導體)電晶體。
複數個去耦電容器C
D並聯連接於電壓傳輸線W
VSS與電壓傳輸線W
VCCQ之間。
內部電路IC包含參照圖3所說明之記憶胞陣列MCA及周邊電路PC。周邊電路PC於輸出數據時,驅動與輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…對應之下拉電路PD或提昇電路PU。藉此,輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…與電壓傳輸線W
VSS或電壓傳輸線W
VCCQ導通。
接下來,參照圖5~圖14對記憶體晶粒MD之構成例進行說明。
圖5係將圖3所示之構造沿V-V線切斷並沿箭頭方向觀察時之模式性剖視圖。圖6係將圖3所示之構造沿VI-VI線切斷並沿箭頭方向觀察時之模式性剖視圖。
如圖5及圖6所示,記憶體晶粒MD具備設置於上表面之鈍化層PL、設置於鈍化層PL下方之配線層M2、設置於配線層M2下方之配線層M1、設置於配線層M1下方之配線層M0、設置於配線層M0下方之配線層MX、設置於配線層MX下方之元件層DL、及設置於元件層DL下方之半導體基板S。
圖7係用以對配線層M2之構成進行說明之模式性俯視圖。配線層M2例如具備包含氮化鈦(TiN)及鋁(Al)等之複數條配線m2。配線m2中之一部分作為焊墊電極P發揮功能。焊墊電極P形成為大致矩形。如圖5及圖6所示,焊墊電極P上表面之一部分由聚醯亞胺等鈍化層PL覆蓋。又,如圖5及圖6所示,焊墊電極P上表面之一部分經由設置於鈍化層PL之開口OP
PL向外部露出。又,如圖7所示,於焊墊電極P之上表面設置有與接合線B(圖1、圖2)接觸之大致圓形之接合區域BB。
圖8係用以對配線層MX之構成進行說明之模式性俯視圖。配線層MX例如具備包含氮化鈦(TiN)及鎢(W)等之複數條配線mX。
於配線層MX中之自Z方向觀察時與焊墊電極P重疊之區域設置有大致圓形之絕緣區域RI、及包圍該大致圓形之絕緣區域RI之大致矩形之導電區域RC。絕緣區域RI例如係由氧化矽(SiO
2)等絕緣層51嵌埋之區域,係不包含導電構件等之區域。於絕緣區域RI之內側設置有與焊墊電極P和接合線B之接觸面對應之接合區域BB。導電區域RC例如具備沿X方向延伸且沿Y方向排列之複數個導電構件52、及沿Y方向延伸且沿X方向排列之複數個導電構件53。導電構件52、53為上述複數條配線mX中之一部分。又,於導電構件52、53之間設置有氧化矽(SiO
2)等絕緣層54。
於配線層MX中之自Z方向觀察時不與焊墊電極P重疊之區域設置有沿X方向及Y方向排列之6組配線群WG。此6組配線群WG分別具備沿X方向延伸且沿Y方向排列之複數條配線mX。該等複數條配線mX分別作為上述電壓傳輸線W
VSS或電壓傳輸線W
VCCQ之一部分發揮功能。又,於此6組配線群之周圍設置有以包圍此6組配線群WG及上述導電構件52、53之方式配置之配線mX。該配線mX作為上述電壓傳輸線W
VSS之一部分發揮功能。
再者,對詳細構成進行了省略,但配線層M0(圖5、圖6)例如具備包含氮化鈦(TiN)及鎢(W)等之複數條配線m0。又,配線層M1(圖5、圖6)例如具備包含氮化鈦(TiN)及銅(Cu)等之複數條配線m1。又,於配線層M0及配線層M1中之自Z方向觀察時與焊墊電極P重疊之區域設置有如參照圖8所說明之大致圓形之絕緣區域、及包圍該大致圓形之絕緣區域之大致矩形之導電區域。
圖9係用以對元件層DL之構成進行說明之模式性俯視圖。將圖9所示之構造沿V-V線切斷並沿箭頭方向觀察時之截面模式性地相當於圖5之元件層DL。將圖9所示之構造沿VI-VI線切斷並沿箭頭方向觀察時之截面模式性地相當於圖6之元件層DL。於元件層DL上設置有複數個去耦電容器C
D之一部分構成。於圖9之例中,與一個焊墊電極P對應而設置有沿X方向及Y方向排列之6個去耦電容器C
D。此6個去耦電容器C
D自與焊墊電極P重疊之區域沿Y方向延伸至不與焊墊電極P重疊之區域。又,於與上述配線群WG(圖8)對應之區域設置有將上述配線群WG中之配線mX與去耦電容器C
D連接之複數個接觸電極CS
VSS、CS
VCCQ。又,於此6個去耦電容器C
D之周圍設置有以包圍此6個去耦電容器C
D之方式配置之複數個接觸電極CS
VSS。
圖10係用以對半導體基板S之構成進行說明之模式性俯視圖。半導體基板S例如為包含硼(B)等P型雜質之單晶矽等之半導體基板。於半導體基板S上設置有半導體基板區域S
S、及以包圍該半導體基板區域S
S之方式設置之P井區域S
PW。
於半導體基板區域S
S中之與去耦電容器C
D對應之區域分別設置有雜質區域S
N。雜質區域S
N例如包含磷(P)或砷(As)等N型雜質。又,於雜質區域S
N之Y方向一端設置有雜質區域S
N+。雜質區域S
N+例如包含磷(P)或砷(As)等N型雜質。雜質區域S
N+中之雜質濃度大於雜質區域S
N中之雜質濃度。
P井區域S
PW例如包含硼(B)等P型雜質。P井區域S
PW中之雜質濃度大於半導體基板區域S
S中之雜質濃度。於P井區域S
PW中之與上述複數個接觸電極CS
VSS對應之區域設置有雜質區域S
P+。雜質區域S
P+例如包含硼(B)等P型雜質。雜質區域S
P+中之雜質濃度大於P井區域S
PW中之雜質濃度。
圖11係表示圖9中之一個去耦電容器C
D之構成之模式性立體圖。圖12~圖14係自圖11中將一部分構成省略後之模式性立體圖。
如圖11所示,本實施形態之去耦電容器C
D具備設置於半導體基板S之雜質區域S
N、設置於半導體基板S上表面之絕緣層101、設置於絕緣層101上表面之半導體層102、設置於半導體層102上表面之絕緣層103、設置於絕緣層103上表面之半導體層104、及設置於半導體層104上表面之導電層105。如圖9及圖10所示,該等構成係將Y方向作為長度方向,從自Z方向觀察時與焊墊電極P重疊之區域延伸至自Z方向觀察時不與焊墊電極P重疊之區域。
絕緣層101例如包含氧化矽(SiO
2)等。
半導體層102包含含有磷(P)或砷(As)等N型雜質、或硼(B)等P型雜質之多晶矽等。如圖5及圖6所示,半導體層102之下表面介隔絕緣層101與雜質區域S
N之上表面對向。
再者,如圖5所示,於X方向上相鄰之2個去耦電容器C
D中所包含之雜質區域S
N、絕緣層101及半導體層102介隔絕緣層STI相互隔開。又,如圖6所示,於Y方向上相鄰之2個去耦電容器C
D中所包含之雜質區域S
N、絕緣層101及半導體層102介隔絕緣層STI相互隔開。絕緣層STI例如包含氧化矽(SiO
2)等。
絕緣層103例如包含氧化矽(SiO
2)等。如圖14所示,於絕緣層103上設置有沿Y方向延伸之開口OP
103。於圖示之例中,絕緣層103經由開口OP
103被截成沿X方向排列之2個部分即絕緣層103a、絕緣層103b。絕緣層103a、絕緣層103b之下表面設置於半導體層102及絕緣層STI之上表面。
半導體層104(圖11)包含含有磷(P)或砷(As)等N型雜質、或硼(B)等P型雜質之多晶矽等。如圖11所示,半導體層104包含沿X方向排列之2個部分即半導體層104a、半導體層104b、設置於其等之間之半導體層104c、及連接於半導體層104c之Y方向一端部之半導體層104d。
如圖11所示,半導體層104a係將Y方向作為長度方向。該半導體層104a之下表面介隔絕緣層103a(圖14)與半導體層102之一部分區域102a(圖13)對向。
如圖11所示,半導體層104b係將Y方向作為長度方向。半導體層104b之下表面介隔絕緣層103b(圖14)與半導體層102之一部分區域102b(圖13)對向。
如圖11所示,半導體層104c係將Y方向作為長度方向。半導體層104c之下表面經由絕緣層103之上述開口OP
103(圖14)連接於半導體層102之一部分區域102c(圖13)。
如圖11所示,半導體層104d係將X方向作為長度方向。半導體層104d之下表面連接於半導體層102之一部分區域102d(圖13)。自Z方向觀察時,半導體層104d與絕緣層103a重疊一部分(圖6)。
導電層105(圖11)包含鎢矽化物(WSi)等。如圖11所示,導電層105包含沿X方向排列之2個導電層105a、導電層105b、設置於其等之間之導電層105c、及連接於導電層105c之Y方向一端部之導電層105d。
導電層105a係將Y方向作為長度方向。導電層105a之下表面連接於半導體層104a之上表面。再者,如圖10所示,導電層105a沿著雜質區域S
N之X方向端部於Y方向上延伸。但是,導電層105a不到達雜質區域S
N之Y方向端部。因此,雜質區域S
N之角部S
NE不由導電層105a覆蓋。半導體層104a亦同樣如此。
導電層105b係將Y方向作為長度方向。導電層105b之下表面連接於半導體層104b之上表面。再者,如圖10所示,導電層105b沿著雜質區域S
N之X方向端部於Y方向上延伸。但是,導電層105b不到達雜質區域S
N之Y方向端部。因此,雜質區域S
N之角部S
NE不由導電層105b覆蓋。半導體層104b亦同樣如此。
導電層105c係將Y方向作為長度方向。導電層105c之下表面連接於半導體層104c之上表面。再者,如圖10所示,導電層105c沿Y方向延伸,到達雜質區域S
N之Y方向端部。半導體層104c亦同樣如此。
導電層105d係將X方向作為長度方向。導電層105d之下表面連接於半導體層104d之上表面。
接觸電極CS
VSS與被供給接地電壓VSS之焊墊電極P導通。接觸電極CS
VSS係沿Z方向延伸之通孔接觸電極,例如包含氮化鈦(TiN)及鎢(W)等。圖11所例示之接觸電極CS
VSS沿X方向設置複數個,且分別連接於導電層105d之上表面。又,該等接觸電極CS
VSS之上端連接於參照圖8所說明之配線群WG中之作為電壓傳輸線W
VSS發揮功能的配線mX。導電層105d及導電層105c之下表面與半導體層104d及半導體層104c之上表面連接。半導體層104d及半導體層104c之下表面與半導體層102d及半導體層102c之上表面連接。藉此,亦向上述半導體層102a、102b供給接地電壓VSS。
接觸電極CS
VCCQ與被供給驅動電壓VCCQ之焊墊電極P導通。接觸電極CS
VCCQ係沿Z方向延伸之通孔接觸電極,例如包含氮化鈦(TiN)及鎢(W)等。
圖11所例示之接觸電極CS
VCCQ中之一部分沿Y方向設置複數個,且分別連接於導電層105a之上表面。又,圖11所例示之接觸電極CS
VCCQ中之一部分沿Y方向設置複數個,且分別連接於導電層105b之上表面。又,該等接觸電極CS
VCCQ之上端連接於參照圖8所說明之配線群WG中之作為電壓傳輸線W
VCCQ發揮功能的配線mX。導電層105a及導電層105b之下表面與半導體層104a及半導體層104b之上表面連接。藉此,向上述半導體層104a、104b供給驅動電壓VCCQ。
圖11所例示之接觸電極CS
VCCQ中之一部分如圖12所示,沿X方向設置複數個,且分別連接於半導體基板S。再者,如圖6所示,於半導體基板S之與接觸電極CS
VCCQ之連接部分設置有雜質區域S
N+。又,該等接觸電極CS
VCCQ之上端連接於參照圖8所說明之配線群WG中之作為電壓傳輸線W
VCCQ發揮功能的配線mX。藉此,向半導體基板S之雜質區域S
N供給驅動電壓VCCQ。
[比較例] 接下來,參照圖15~圖17對比較例之記憶體晶粒進行說明。圖15係表示比較例之記憶體晶粒之一部分構成之模式性俯視圖。圖16係表示圖15所示之構成之一部分之模式性立體圖。圖17係自圖16所示之構成中將一部分構成省略後之模式性立體圖。
比較例之記憶體晶粒與第1實施形態之記憶體晶粒不同,不具備去耦電容器C
D。作為代替,比較例之記憶體晶粒具備去耦電容器C
D'。
如圖16所示,比較例之去耦電容器C
D'具備雜質區域S
N、設置於半導體基板S上表面之絕緣層101、設置於絕緣層101上表面之半導體層102、設置於半導體層102上表面之絕緣層103'、設置於絕緣層103'上表面之半導體層104'、及設置於半導體層104'上表面之導電層105'。如圖15所示,該等構成係將Y方向作為長度方向,從自Z方向觀察時與焊墊電極P重疊之區域延伸至自Z方向觀察時不與焊墊電極P重疊之區域。
絕緣層103'(圖16)基本上與絕緣層103(圖12)同樣地構成。但是,如圖17所示,絕緣層103'不具有開口OP
103(圖14),不被截成2個部分。
半導體層104'(圖16)包含含有磷(P)或砷(As)等N型雜質、或硼(B)等P型雜質之多晶矽等。如圖16所示,半導體層104'包含沿Y方向排列之2個部分即半導體層104a'、半導體層104d'。半導體層104a'之下表面介隔絕緣層103'與半導體層102之上表面之一部分區域對向。半導體層104d'之下表面連接於半導體層102之一部分區域之上表面。
導電層105'包含鎢矽化物(WSi)等。導電層105'包含沿Y方向排列之2個部分即導電層105a'、導電層105d'。導電層105a'之下表面連接於半導體層104a'之上表面。導電層105d'之下表面連接於半導體層104a'之上表面。
圖17所例示之接觸電極CS
VSS沿X方向設置複數個,且分別連接於導電層105d'之上表面。藉此,向上述半導體層102供給接地電壓VSS。再者,如圖15所示,接觸電極CS
VSS設置於自Z方向觀察時不與焊墊電極P重疊之位置。
[效果] 將接合線B(圖1、圖2)安裝於焊墊電極P時,利用毛細管向下按壓焊墊電極P。此時,經由焊墊電極P亦對配線mX、m0、m1施加應力。此處,若於產生此種應力之區域設置上述配線mX、m0、m1,則有可能應力會集中到該等配線mX、m0、m1附近之絕緣層,導致於該絕緣層上產生龜裂。若毛細管於此種狀態下向上方移動,則包含焊墊電極P之一部分構造可能與接合線B一同自半導體基板S上被揭下。為了抑制此種現象,於比較例中,例如與參照圖8所說明之第1實施形態同樣地,不於與焊墊電極P和接合線B之接觸面對應之接合區域BB設置配線mX、m0、m1。
此處,連接於去耦電容器C
D'之複數個接觸電極CS
VSS、CS
VCCQ在上端連接於參照圖8所說明之配線群WG中之配線mX。因此,在將該等配線群WG設置於不與焊墊電極P重疊之區域之情形時,接觸電極CS
VSS、CS
VCCQ亦設置於不與焊墊電極P重疊之區域。因此,於比較例之去耦電容器C
D'中,將作為電容器之電極發揮功能之雜質區域S
N、半導體層102及半導體層104'於不與焊墊電極P重疊之區域中,與接觸電極CS
VSS、CS
VCCQ連接。
此處,半導體層102之電阻率大於導電層105'(圖16)之電阻率。因此,存在以下情況:若參照圖4所說明之輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之信號頻率變大,則半導體層102中之設置於距導電層105d'相對較遠之區域之部分難以作為電容器發揮功能。於此種情形時,存在輸入輸出信號線W
IO0、W
IO1、W
IO2、W
IO3…之電壓變得不穩定之情況。
此處,如參照圖14所說明,於第1實施形態之去耦電容器C
D中,於絕緣層103上設置有沿Y方向延伸之開口OP
103。又,如參照圖11所說明,半導體層104c經由該開口OP
103連接於半導體層102之上表面。又,導電層105c連接於半導體層104c之上表面。
根據此種構成,能夠使半導體層102整體經由導電層105c靠近導電層105d。藉此,不於如參照圖7所說明之接合區域BB配置接觸電極CS
VSS等,便能使半導體層102之充放電高速化。因此,能夠一面抑制如上所述之焊墊電極P之剝離,一面抑制伴隨信號頻率之高速化所造成之電容值之衰減。
圖18係表示去耦電容器C
D、C
D'之信號頻率與電容值之關係之曲線圖。再者,圖18所示之特性之中,去耦電容器C
D之相關特性表示與半導體層102上表面和半導體層104下表面之間的電容值相關之模擬結果。又,圖18所示之特性之中,去耦電容器C
D'之相關特性表示與半導體層102'上表面和半導體層104'下表面之間的電容值相關之模擬結果。
於信號頻率相對較小之情形時,去耦電容器C
D'之電容值大於去耦電容器C
D之電容值。認為其理由在於:於去耦電容器C
D中,不以半導體層104介隔絕緣層103與半導體層102c(圖13)對向之方式配置,故而不蓄積電荷。
於信號頻率相對較大之情形時,去耦電容器C
D之電容值大於去耦電容器C
D'之電容值。認為其理由在於:於去耦電容器C
D'中,半導體層102之一部分區域距導電層105d'較遠,此種部分中之充放電速度較小。又,認為其理由在於:於去耦電容器C
D中,半導體層102整體設置於導電層105d附近,於半導體層102之區域102a、102b中,高速地進行充放電。
[第2實施形態] 接下來,參照圖19~圖21對第2實施形態之記憶體晶粒進行說明。圖19及圖20係用以對本實施形態之記憶體晶粒之構成進行說明之模式性俯視圖。圖21係用以對本實施形態之記憶體晶粒之構成進行說明之模式性立體圖。再者,於以下說明中,對與第1實施形態相同之構成要素標註相同符號,並省略說明。
本實施形態之記憶體晶粒基本上與第1實施形態之記憶體晶粒MD同樣地構成。但是,本實施形態之記憶體晶粒不具備去耦電容器C
D,作為代替,具備去耦電容器C
D2。本實施形態之去耦電容器C
D2基本上與第1實施形態之去耦電容器C
D同樣地構成。但是,本實施形態之去耦電容器C
D2不具備絕緣層103、半導體層104及導電層105,作為代替,具備絕緣層203、半導體層204及導電層205。
絕緣層203基本上與絕緣層103同樣地構成。但是,絕緣層203不具有上述開口OP
103(圖14),不被截成2個部分。又,絕緣層203不覆蓋半導體層102之X方向之一側端部。
半導體層204基本上與半導體層104同樣地構成。但是,半導體層204僅具備與半導體層104a對應之半導體層204a、與半導體層104c對應之半導體層204c、及與半導體層104d對應之半導體層204d,不具備與半導體層104b對應之半導體層204b。半導體層204c連接於半導體層102之不由絕緣層203覆蓋之部分之上表面。
導電層205基本上與導電層105同樣地構成。但是,導電層205僅具備與導電層105a對應之導電層205a、與導電層105c對應之導電層205c、及與導電層105d對應之導電層205d,不具備與導電層105b對應之導電層205b。
再者,如圖20所示,於本實施形態中,導電層205c覆蓋雜質區域S
N之X方向一端部及Y方向一端部。藉此,於本實施形態中,雜質區域S
N之角部S
NE由導電層205c覆蓋。
[第3實施形態] 接下來,參照圖22及圖23對第3實施形態之記憶體晶粒進行說明。圖22係用以對本實施形態之記憶體晶粒之構成進行說明之模式性俯視圖。用以對本實施形態之記憶體晶粒之構成進行說明之模式性立體圖與圖21相同。圖23係用以對本實施形態之比較例之記憶體晶粒之構成進行說明之模式性俯視圖。再者,於以下說明中,對與第2實施形態相同之構成要素標註相同符號,並省略說明。
本實施形態之記憶體晶粒基本上與第2實施形態之記憶體晶粒同樣地構成。然而,本實施形態之記憶體晶粒不具備去耦電容器C
D2,作為代替,具備去耦電容器C
D3。本實施形態之去耦電容器C
D3基本上與第2實施形態之去耦電容器C
D2同樣地構成。但是,本實施形態之去耦電容器C
D3不具備半導體層204及導電層205,作為代替,具備未圖示之半導體層及導電層305。
未圖示之半導體層基本上與半導體層204同樣地構成。即,該半導體層具備與半導體層204a對應之半導體層、與半導體層204c對應之半導體層、及與半導體層204d對應之半導體層。但是,與該半導體層204d對應之部分不覆蓋雜質區域S
N之Y方向之一側端部。因此,於本實施形態中,雜質區域S
N之角部S
NE(圖22)不由半導體層304覆蓋。
導電層305基本上與導電層205同樣地構成。即,導電層305具備與導電層205a對應之導電層305a、與導電層205c對應之導電層305c、及與導電層205d對應之導電層305d。但是,本實施形態之導電層305c不覆蓋雜質區域S
N之Y方向一端部。因此,於本實施形態中,例如如圖22所示,雜質區域S
N之角部S
NE不由導電層305覆蓋。
此處,於雜質區域S
N之角部S
NE,存在發生電場集中之情況。於此種情形時,若雜質區域S
N之角部S
NE由導電層等覆蓋,則存在該角部附近容易發生絕緣破壞等,導致去耦電容器之壽命變短之情況。因此,於第1實施形態中,使得半導體層104及導電層105不與雜質區域S
N之角部S
NE重疊。同樣地,於第3實施形態中,使得未圖示之半導體層及導電層305不與此種雜質區域S
N之角部S
NE重疊。根據此種構成,與第2實施形態相比較,能夠提供長壽命之記憶體晶粒。
於第3實施形態之比較例之構成中,如圖23所示,未圖示之半導體層及導電層305不覆蓋雜質區域S
N之X方向之一側端部。此處,由於半導體層102係將Y方向作為長度方向,故而於未圖示之半導體層及導電層305以避開X方向之一側端部(長邊)之方式配置之構成中,存在去耦電容器C
D3'之電容值相對於去耦電容器C
D3之電容值相對較小之情況。又,如第3實施形態,由於未圖示之半導體層及導電層305c之Y方向長度(圖22)小於第2實施形態中之半導體層204c及導電層205c之Y方向長度(圖20),故而存在電容值相對較小之情況。對此,於第1實施形態中,將連接於半導體層102之半導體層104c配置於半導體層104a、半導體層104b之間。根據此種構成,能夠抑制X方向上之電容值減少及Y方向上之電容值減少,因此,能夠實現長壽命且大電容之去耦電容器C
D。
[第4實施形態] 接下來,參照圖24對第4實施形態之記憶體晶粒進行說明。圖24係用以對本實施形態之記憶體晶粒之構成進行說明之模式性俯視圖。再者,於以下說明中,對與第1實施形態相同之構成要素標註相同符號,並省略說明。
本實施形態之記憶體晶粒基本上與第1實施形態之記憶體晶粒同樣地構成。然而,本實施形態之記憶體晶粒不具備去耦電容器C
D,作為代替,具備去耦電容器C
D4。本實施形態之去耦電容器C
D4基本上與第1實施形態之去耦電容器C
D同樣地構成。然而,本實施形態之去耦電容器C
D4不具備半導體層104及導電層105,作為代替,具備導電層405及未圖示之半導體層。
導電層405基本上與導電層105同樣地構成。即,導電層405具備與導電層105a對應之導電層405a、與導電層105b對應之導電層405b、與上述導電層105c對應之導電層405c、及與導電層105d對應之導電層405d。但是,本實施形態之導電層405d不沿X方向延伸。
設置於絕緣層103與導電層405之間之半導體層基本上與半導體層104同樣地構成。但是,該半導體層之平面形狀與導電層405同樣地形成。
[第5實施形態] 接下來,參照圖25~圖28對第5實施形態之記憶體晶粒進行說明。圖25係用以對本實施形態之記憶體晶粒之構成進行說明之模式性俯視圖。圖26及圖27係用以對本實施形態之記憶體晶粒之構成進行說明之模式性剖視圖。再者,於以下說明中,對與第1實施形態相同之構成要素標註相同符號,並省略說明。
本實施形態之記憶體晶粒基本上與第1實施形態之記憶體晶粒同樣地構成。然而,本實施形態之記憶體晶粒不具備半導體基板S,作為代替,具備半導體基板S
5。本實施形態之半導體基板S
5基本上與第1實施形態之半導體基板S同樣地構成。然而,如參照圖10所說明,於第1實施形態之半導體基板S上設置有半導體基板區域S
S、及以包圍該半導體基板區域S
S之方式設置之P井區域S
PW,於該半導體基板區域S
S設置有6個去耦電容器C
D。另一方面,如圖25所示,於本實施形態之半導體基板S
5上設置有N井區域S
NW、及以包圍該N井區域S
NW之方式設置之P井區域S
PW,於該N井區域S
NW設置有6個去耦電容器C
D5。N井區域S
NW例如包含磷(P)或砷(As)等N型雜質。又,於該N井區域S
NW設置有沿Y方向延伸之雜質區域S
N+。於該雜質區域設置有沿Y方向排列之複數個接觸電極CS
VCCQ。
本實施形態之去耦電容器C
D5基本上與第1實施形態之去耦電容器C
D同樣地構成。然而,如圖26及圖27所示,6個去耦電容器C
D5中所包含之6個雜質區域S
N經由N井區域S
NW導通。
圖28係表示去耦電容器C
D5、C
D'之信號頻率與電容值之關係之曲線圖。再者,圖28所示之特性之中,去耦電容器C
D5之相關特性表示與半導體基板S
5之上表面和半導體層102之下表面之間的電容值相關之模擬結果。又,圖28所示之特性之中,去耦電容器C
D'之相關特性表示與半導體基板S之上表面和半導體層102之下表面之間的電容值相關之模擬結果。
於信號頻率相對較小之情形時,去耦電容器C
D5、C
D'之電容值成為相同程度。另一方面,於信號頻率相對較大之情形時,去耦電容器C
D5之電容值大於去耦電容器C
D'之電容值。其原因在於:藉由N井區域S
NW降低了半導體基板S
5上表面之電阻率。
如上所述,根據本實施形態之此種構成,藉由N井區域S
NW降低了半導體基板S
5上表面之電阻率,能夠更好地抑制伴隨信號頻率之高速化所造成之電容值之衰減。
又,根據本實施形態之此種構成,藉由半導體基板S
5之N井區域S
NW與設置於該N井區域S
NW下方之半導體基板區域S
S之間之耗盡層而產生寄生電容。因此,能夠利用該寄生電容來增大去耦電容器C
D5之電容值。
[第6實施形態] 接下來,參照圖29~圖31對第6實施形態之記憶體晶粒進行說明。圖29係用以對本實施形態之記憶體晶粒之構成進行說明之模式性俯視圖。圖30及圖31係用以對本實施形態之記憶體晶粒之構成進行說明之模式性剖視圖。再者,於以下說明中,對與第5實施形態相同之構成要素標註相同符號,並省略說明。
本實施形態之記憶體晶粒基本上與第5實施形態之記憶體晶粒同樣地構成。然而,本實施形態之記憶體晶粒不具備半導體基板S
5及去耦電容器C
D5,作為代替,具備半導體基板S
6及去耦電容器C
D6。
本實施形態之去耦電容器C
D6基本上與第5實施形態之去耦電容器C
D5同樣地構成。然而,本實施形態之去耦電容器C
D6具備使半導體基板S
6之上表面露出之複數個貫通孔OP
CD。即,去耦電容器C
D6例如如圖30及圖31所示,具備絕緣層601來代替絕緣層101。具備半導體層602來代替半導體層102。半導體層602具有區域602a、區域602b、區域602c、區域602d來代替半導體層102所具有之區域102a、區域102b、區域102c、區域102d。具備半導體層604來代替半導體層104。具備半導體層604a、半導體層604b、半導體層604c、半導體層604d來代替半導體層104a、半導體層104b、半導體層104c、半導體層104d。具備導電層605來代替導電層105。具備導電層605a、導電層605b、導電層605c、導電層605d來代替導電層105a、導電層105b、導電層105c、導電層105d。於絕緣層601、半導體層602之區域602c、半導體層604c、及導電層605c上設置有沿Y方向排列之複數個貫通孔。
本實施形態之半導體基板S
6基本上與第5實施形態之半導體基板S
5同樣地構成。然而,例如如圖30及圖31所示,於本實施形態之半導體基板S
6中,於與上述貫通孔OP
CD對應之區域設置有雜質區域S
N+。又,於該雜質區域S
N+分別設置有接觸電極CS
VCCQ。接觸電極CS
VCCQ經由配線層MX之配線mx而與電壓傳輸線W
VCCQ連接。藉此,於更多之位置對N井區域S
NW施加電壓VCCQ,因此,N井區域S
NW之薄層電阻有效地減少。因此,能夠抑制高頻區域之有效電容下降。再者,該等接觸電極CS
VCCQ之至少一部分設置於自Z方向觀察時與焊墊電極P重疊之位置。
[其他] 雖對本發明之若干實施形態進行了說明,但該等實施形態係作為例而提出,並不意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施,且能夠於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍中所記載之發明及其同等之範圍內。
相關申請案之引用
本申請案係基於2020年03月24日提出申請之在先日本專利申請案第2020-053410號之優先權而主張優先權利益,藉由引用將其全部內容併入本文中。
51:絕緣層
52:導電構件
53:導電構件
54:絕緣層
100:記憶系統
101:絕緣層
102:半導體層
102a:半導體層102之一部分區域
102b:半導體層102之一部分區域
102c:半導體層102之一部分區域
102d:半導體層102之一部分區域
103:絕緣層
103':絕緣層
103a:絕緣層
103b:絕緣層
104:半導體層
104':半導體層
104a:半導體層
104a':半導體層
104b:半導體層
104c:半導體層
104d:半導體層
104d':半導體層
105:導電層
105':導電層
105a:導電層
105a':導電層
105b:導電層
105c:導電層
105d:導電層
105d':導電層
203:絕緣層
204:半導體層
204a:半導體層
204c:半導體層
204d:半導體層
205:導電層
205a:導電層
205c:導電層
205d:導電層
305a:導電層
305c:導電層
305d:導電層
405a:導電層
405b:導電層
405c:導電層
405d:導電層
601:絕緣層
602:半導體層
602a:區域
602b:區域
602c:區域
602d:區域
604:半導體層
604a:半導體層
604b:半導體層
604c:半導體層
604d:半導體層
605:導電層
605a:導電層
605b:導電層
605c:導電層
605d:導電層
B:接合線
BB:接合區域
C
D:去耦電容器
C
D':去耦電容器
C
D2:去耦電容器
C
D3:去耦電容器
C
D3':去耦電容器
C
D4:去耦電容器
C
D5:去耦電容器
C
D6:去耦電容器
CS
VCCQ:接觸電極
CS
VSS:接觸電極
DL:元件層
DL':元件層
DL
2:元件層
DL
4:元件層
DL
5:元件層
DL
6:元件層
IC:內部電路
M0:配線層
m0:配線
M1:配線層
m1:配線
M2:配線層
m2:配線
MB:記憶塊
MCA:記憶胞陣列
MD:記憶體晶粒
MSB:安裝基板
MX:配線層
mX:配線
OP
CD:貫通孔
OP
PL:開口
P:焊墊電極
PC:周邊電路
PD:下拉電路
PL:鈍化層
PU:提昇電路
RC:導電區域
RI:絕緣區域
S:半導體基板
S
5:半導體基板
S
6:半導體基板
S
N:雜質區域
S
N+:雜質區域
S
NE:角部
S
NW:N井區域
S
P+:雜質區域
S
PW:P井區域
S
S:半導體基板區域
STI:絕緣層
W
IO0, W
IO1, W
IO2, W
IO3:輸入輸出信號線
W
VCCQ:電壓傳輸線
W
VSS:電壓傳輸線
WG:配線群
圖1係表示第1實施形態之第1構成之記憶系統100之構成例之模式性側視圖。
圖2係表示該記憶系統100之構成例之模式性俯視圖。
圖3係表示記憶體晶粒MD之構成之模式性俯視圖。
圖4係表示記憶體晶粒MD之構成之模式性電路圖。
圖5係將圖3所示之構造沿V-V線切斷並沿箭頭方向觀察時之模式性剖視圖。
圖6係將圖3所示之構造沿VI-VI線切斷並沿箭頭方向觀察時之模式性剖視圖。
圖7係表示配線層M2之構成之模式性俯視圖。
圖8係表示配線層MX之構成之模式性俯視圖。
圖9係表示元件層DL之構成之模式性俯視圖。
圖10係表示半導體基板S之構成之模式性俯視圖。
圖11係表示去耦電容器C
D之構成之模式性立體圖。
圖12係表示去耦電容器C
D之一部分構成之模式性立體圖。
圖13係表示去耦電容器C
D之一部分構成之模式性立體圖。
圖14係表示去耦電容器C
D之一部分構成之模式性立體圖。
圖15係表示比較例之元件層DL'之構成之模式性俯視圖。
圖16係表示比較例之去耦電容器C
D'之構成之模式性立體圖。
圖17係表示去耦電容器C
D'之一部分構成之模式性立體圖。
圖18係用以對去耦電容器C
D、C
D'之頻率特性進行說明而示出之曲線圖。
圖19係表示第2實施形態之元件層DL
2之構成之模式性俯視圖。
圖20係表示第2實施形態之半導體基板S之構成之模式性俯視圖。
圖21係表示第2實施形態之去耦電容器C
D2之構成之模式性立體圖。
圖22係表示第3實施形態之去耦電容器C
D3之構成之模式性俯視圖。
圖23係表示第3實施形態之半導體基板S之構成之模式性俯視圖。
圖24係表示第4實施形態之元件層DL
4之構成之模式性俯視圖。
圖25係表示第5實施形態之元件層DL
5之構成之模式性俯視圖。
圖26係將圖25所示之構造沿XXVI-XXVI線切斷並沿箭頭方向觀察時之模式性剖視圖。
圖27係將圖25所示之構造沿XXVII-XXVII線切斷並沿箭頭方向觀察時之模式性剖視圖。
圖28係用以對去耦電容器C
D5、C
D'之頻率特性進行說明而示出之曲線圖。
圖29係表示第6實施形態之元件層DL
6之構成之模式性俯視圖。
圖30係將圖29所示之構造沿XXX-XXX線切斷並沿箭頭方向觀察時之模式性剖視圖。
圖31係將圖29所示之構造沿XXXI-XXXI線切斷並沿箭頭方向觀察時之模式性剖視圖。
101:絕緣層
102:半導體層
103:絕緣層
104:半導體層
104a:半導體層
104b:半導體層
104c:半導體層
104d:半導體層
105:導電層
105a:導電層
105b:導電層
105c:導電層
105d:導電層
CD:去耦電容器
CSVCCQ:接觸電極
CSVSS:接觸電極
S:半導體基板
SN:雜質區域
STI:絕緣層
Claims (7)
- 一種半導體裝置,其具備: 半導體基板; 第1半導體層,其於與上述半導體基板之表面交叉之第1方向上與上述半導體基板之表面對向; 第2半導體層,其相較上述第1半導體層距上述半導體基板較遠,於上述第1方向上與上述第1半導體層對向; 第1導電層,其相較上述第2半導體層距上述半導體基板較遠,連接於上述第2半導體層; 第3半導體層,其於與上述第1方向交叉之第2方向上與上述第2半導體層並排,連接於上述第1半導體層;及 第2導電層,其於上述第2方向上與上述第1導電層並排,連接於上述第3半導體層;且 上述第1半導體層、上述第2半導體層及上述第3半導體層係將與上述第1方向及上述第2方向交叉之第3方向作為長度方向。
- 如請求項1之半導體裝置,其具備: 第4半導體層,其於上述第2方向上與上述第3半導體層並排,相較上述第3半導體層距上述第2半導體層較遠,於上述第1方向上與上述第1半導體層對向;及 第3導電層,其於上述第2方向上與上述第2導電層並排,相較上述第2導電層距上述第1導電層較遠,連接於上述第4半導體層;且 上述第4半導體層係將上述第3方向作為長度方向。
- 如請求項1之半導體裝置,其具備: 第5半導體層,其連接於上述第3半導體層在上述第3方向上之端部,將上述第2方向作為長度方向;及 第4導電層,其連接於上述第2導電層在上述第3方向上之端部,將上述第2方向作為長度方向。
- 如請求項1之半導體裝置,其 具備連接有接合線之焊墊電極,且 上述第1半導體層、上述第2半導體層及上述第3半導體層分別具備設置於自上述第1方向觀察時與上述焊墊電極重疊之位置之部分、及設置於自上述第1方向觀察時不與上述焊墊電極重疊之位置之部分。
- 如請求項4之半導體裝置,其 具備連接於上述第1導電層及上述第2導電層之複數個第1接觸電極,且 上述複數個第1接觸電極設置於自上述第1方向觀察時不與上述焊墊電極重疊之位置。
- 如請求項1至5中任一項之半導體裝置,其中 上述半導體基板之與上述第1半導體層對向之區域設置有包含N型雜質之N井。
- 如請求項6之半導體裝置,其 具備連接有接合線之焊墊電極,且 具備連接於上述N井之第2接觸電極, 上述第2接觸電極設置於自上述第1方向觀察時與上述焊墊電極重疊之位置。
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