TWI729544B - 連接結構及其形成方法 - Google Patents

連接結構及其形成方法 Download PDF

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TWI729544B
TWI729544B TW108138801A TW108138801A TWI729544B TW I729544 B TWI729544 B TW I729544B TW 108138801 A TW108138801 A TW 108138801A TW 108138801 A TW108138801 A TW 108138801A TW I729544 B TWI729544 B TW I729544B
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pad
bump
epoxy
semiconductor structure
carrier board
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TW108138801A
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TW202038342A (zh
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吳佳芸
邱玉玲
劉慈祥
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立積電子股份有限公司
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Abstract

一種用於形成連接結構的方法。首先，提供一半導體結構，所述半導體結構在其底面上分別具有一第一接墊和一凸塊。接著提供一載板，在其上表面具有一第二接墊。所述第二接墊對應於所述凸塊。一環氧結構部設置在所述載板的所述第二接墊上。所述環氧結構部的直徑小於或等於所述凸塊的直徑。在設置所述環氧結構部之後，將所述凸塊經由所述環氧結構部附接到所述第二接墊。

Description

連接結構及其形成方法
本公開大致上涉及半導體技術領域。更具體地，本公開涉及半導體結構與載板之間的連接結構及其形成方法。
如本領域中已知的，諸如表面聲波(Surface Acoustic Wave,SAW)元件等半導體結構在商業應用中經常用作射頻(RF)和中頻(IF)濾波器，以提供頻率選擇性和其他電子功能。此外，在組裝過程中，通常使用焊料將半導體結構的凸塊附接到載板上的接墊。然而，在焊料回焊過程中發生的助焊劑飛濺經常導致半導體結構的底面的污染問題。
因此，在該技術領域中仍需要提供一種用於在半導體結構與載板之間形成連接結構的改進方法，該方法能夠解決上述現有技術中的問題和缺點。
本公開的目的是提供一種用於形成連接結構的改進方法，其可以避免上述現有技術的缺點。
本發明一方面提供了一種用於形成連接結構的方法。首先，提供一半導體結構，所述半導體結構在其底面上分別具有一第一接墊和一凸塊。接著 提供一載板，在其上表面具有一第二接墊。所述第二接墊對應於所述凸塊。一環氧結構部設置在所述載板的所述第二接墊上。所述環氧結構部的直徑小於或等於所述凸塊的直徑。在設置所述環氧結構部之後，將所述凸塊經由所述環氧結構部附接到所述第二接墊。
本發明另一方面提供了一種連接結構。所述連接結構包括一半導體結構，所述半導體結構在其底面上分別具有一第一接墊和一凸塊；一載板，在其上表面上具有第二接墊；以及一環氧結構部，連接於所述凸塊和所述第二接墊之間。所述第二接墊對應於所述凸塊。根據本發明一實施例，所述環氧結構部的直徑小於所述凸塊的直徑。
1:連接結構
10:半導體結構
10b:底面
20:載板
20a:上表面
30:乾膜
40:間隙
50:空腔
101:電路元件
102:第一接墊
104:凸塊
202:第二接墊
204:環氧結構部
500:方法
501、502、503、504、505、506:步驟
d1、d2、d3:直徑
h:高度
第1圖至第3圖為根據本發明一實施例所繪示的形成連接結構的方法示意性截面圖。
第4圖為根據本發明一實施例所繪示的連接結構的放大截面圖。
第5圖為根據本發明一實施例所繪示的用於形成連接結構的方法流程圖。
以下，將參考附圖詳細描述示例性實施例，以使本領域的普通技術人員容易地實現示例性實施例。本發明構思可以以各種形式體現，而不限於在此闡述的示例性實施例。為了清楚起見，省略了對公知部分的描述，並且相似的附圖標記始終指代相似的元件。
因此，以下詳細描述不應被理解為限制性的，並且本發明的範圍僅由所附權利要求以及這些權利要求所賦予的均等物的全部範圍來限定。
請注意，說明書中對“一實施例”、“一個實施例”、“示例性實施例”、“一些實施例”等的引用指示所描述的實施例可以包括特定的特徵、結構或特性，但是，每個實施例可能不一定包括特定的特徵、結構或特性。而且，這樣的用語不一定指相同的實施例。
此外，當結合一實施例描述特定的特徵、結構或特性時，無論是否明確描述，與其他實施例結合地影響這種特徵、結構或特性都將在相關領域的技術人員的知識範圍內。
下文中所用的用語“晶圓”和“基板”包括具有曝露表面的任何結構，例如，材料層沉積在該曝露表面上以形成電路結構，該電路結構包括但不限於互連金屬線或重分佈層(RDL)。用語“基板”應理解為包括晶圓，但不限於此。用語“基板”還用於指處理期間的半導體結構，並且可以包括已經製造在其上的其他層。
本公開涉及一種連接結構及其形成方法。在半導體結構的組裝過程中，通過在載板的接墊上施加導電環氧結構部，可以避免半導體結構的底面的污染問題。
第1圖至第3圖為根據本發明一實施例所繪示的形成連接結構的方法示意性截面圖。如第1圖所示，首先提供一半導體結構10。根據本發明實施例，半導體結構10可以包括一晶圓或一SAW晶片。例如，半導體結構10是一SAW晶片，且在半導體結構10的底面10b上分別具有第一接墊102和凸塊104。根據一實施例，例如，凸塊104是金凸塊，但不限於此。凸塊104具有直徑d1。至少一電路元件101，例如叉指式轉換器(interdigital transducer,IDT)，可以被設置在半導體結構10的底面10b上。
儘管未在圖中示出，但是已知IDT可以是製作在合適的壓電基板上的串接的薄金屬條或“指狀件”。一組指狀件連接到輸入/輸出端子，而另一組指 狀件連接到第二端子。在單端IDT中，前述第二端子接地。但是，對於差分輸入信號，第二端子是脈衝輸入/輸出端子。
仍參照第1圖，接著提供一載板20。載板20可以包括在載板20的上表面20a的第二接墊202。根據一實施例，第二接墊202對應於凸塊104。組裝時，凸塊104與第二接墊202對準。在一實施例中，載板20可以包括高溫共燒陶瓷(HTCC)基板、低溫共燒陶瓷(LTCC)基板、矽基板或印刷電路板(PCB)。根據一實施例，可以在上表面20a上設置防焊遮罩以保護上表面20a上的銅走線不被氧化。根據一實施例，第二接墊202可以是包括金、銅、鋁、鈦、氮化鈦、銀或其任何組合的金屬接墊。
根據一實施例，將環氧結構部204設置在載板20的第二接墊202上。根據一實施例，可以通過鋼板印刷或本領域中已知的任何合適的方法將環氧結構部204設置在第二接墊202上。
根據一實施例，環氧結構部204的直徑d2小於或等於凸塊104的直徑d1。根據一實施例，環氧結構部204是導電的。例如，環氧結構部204包括銀和環氧樹脂，但不限於此。
如第2圖所示，在設置環氧結構部204之後，使半導體結構10朝向載板20移動並靠近載板20的上表面20a，直到凸塊104與環氧結構部204直接接觸，如此使得凸塊104經由環氧結構部204附接到第二接墊202上。在將凸塊104附接到第二接墊202之後，接著進行一固化處理，通過加熱來固化環氧結構部204。例如，環氧結構部204可以在以下條件下固化：在烤箱中於60分鐘內升溫至150℃，並於150℃固化60分鐘。
根據一實施例，在將凸塊104附接到第二接墊202之前，環氧結構部204在室溫下可具有小於12000cps的黏度。根據一實施例，在將凸塊104附著到第二接墊202之前，環氧結構部204在室溫下可具有大於8000cps的黏度。優選地， 在將凸塊104附著到第二接墊202之前，選擇黏度為小於12000cps(例如，在25℃時)的環氧結構部204，因此在組裝過程中可以減少不良的附著。此外，當通過加熱環氧結構部204進行固化處理時，由於選擇的黏度範圍，環氧結構部204幾乎不變形，因此，環氧結構部204幾乎不會接觸到半導體結構10的底面10b，故能降低半導體結構表面污染的風險。
根據一實施例，環氧結構部204可以具有小於5×10-5ohm-cm的電阻率，以提供更好的電導率並降低對半導體結構10的性能的影響。根據一實施例，在將凸塊104附接到第二接墊202之前，環氧結構部204可以具有範圍在0.03mm至0.07mm之間的厚度。根據一實施例，在將凸塊104附接到第二接墊202上之後，環氧結構部204的直徑d3小於或等於凸塊104的直徑d1。
根據一實施例，在將凸塊104附接到第二接墊202之後，半導體結構10的底面10b與載板20的上表面20a之間的高度h大於10μm。通過提供這種構造，可以降低對半導體結構的性能的影響。根據一實施例，凸塊104不與第二接墊202物理接觸。
如第3圖所示，接著將乾膜30層壓到半導體結構10和載板20的上表面20a上。根據一實施例，乾膜30可以包括環氧樹脂膜。根據一實施例，乾膜30可以延伸到半導體結構10的底面10b和載板20的上表面20a之間的間隙40中。半導體結構10的電路元件101位於空腔50內，密封在乾膜30、半導體結構10的底面10b和載板20的上表面20a之間。
使用本公開優點說明如下。首先，施加環氧結構部204，可以省略傳統的焊料回焊製程，因此降低了污染半導體結構10的底面10b的風險。其次，通過控制環氧結構部204的直徑和厚度，可以減小環氧結構部204和凸塊104的側邊緣之間的接觸面積，這可以降低環氧結構部204通過凸塊104的側邊緣接觸半導體結構10的底面10b的風險。通過選擇具有合適黏度的環氧結構部204，在組裝過程 中可以減少不良的附著且能夠降低半導體結構10表面污染的風險。通過選擇具有合適電阻率的環氧結構部204，可以降低對半導體結構10性能的影響。此外，因為可以保持半導體結構10的底面10b與載板20的上表面20a之間的適當高度h，亦可降低對半導體結構10性能的影響。因此，本發明所提供的方法可以顯著提高將SAW晶片組裝到載板上的可靠性。
第4圖為根據本發明一實施例所繪示的連接結構的放大截面圖，其中相同的附圖標記表示相同的元件、區域或層。如第4圖所示，連接結構1包括半導體結構10，在半導體結構10的底面10b上分別具有第一接墊102和凸塊104。提供一載板20，在載板20的上表面20a上具有第二接墊202。第二接墊202對應於凸塊104。連接結構1還包括連接在凸塊104和第二接墊202之間的環氧結構部204。在將凸塊104附接到第二接墊202之後，環氧結構部204的直徑d3小於或等於凸塊104的直徑d1。
根據一實施例，半導體結構10可以包括晶圓或SAW晶片。根據一實施例，載板20可以包括HTCC基板、LTCC基板，矽基板或PCB。根據一實施例，凸塊是金凸塊。根據一實施例，第二接墊202是金屬墊，包括金、銅、鋁、鈦、氮化鈦、銀或其任何組合。
根據一實施例，環氧結構部是導電的。根據一實施例，環氧結構部204可以包括銀和環氧樹脂。根據一實施例，環氧結構部204可以具有小於5×10-5ohm-cm的電阻率。根據一實施例，半導體結構10的底面10b與載板20的上表面20a之間的高度h大於10μm。
根據一實施例，連接結構1可以進一步包括層壓在半導體結構10和載板20的上表面20a上的乾膜30。根據一實施例，乾膜30可以包括環氧樹脂膜。半導體結構10的電路元件101位於空腔50內，空腔50被密封在乾膜30、半導體結構10的底面10b和載板20的上表面20a之間。
請參考第5圖，並簡要地參考第1圖至第3圖。第5圖為根據本發明一實施例所繪示的用於形成連接結構的方法500流程圖。如第4圖和第5圖所示，在步驟501中，提供半導體結構10。半導體結構10包括在半導體結構10的底面10b上的第一接墊102和凸塊104。在步驟502中，提供在其上表面20a上具有第二接墊202的載板20。第二接墊202對應於凸塊104。根據一實施例，第二接墊202與凸塊104對準。在步驟503中，將環氧結構部204設置在載板20的第二接墊202上。環氧結構部204的直徑d2小於或等於凸塊104的直徑d1。在步驟504中，在設置環氧結構部204之後，凸塊104通過環氧結構部204附接到第二接墊202。在步驟505中，在將凸塊104附接到第二接墊202之後，通過加熱來固化環氧結構部204。在步驟506中，將乾膜30層壓到半導體結構10和載板20的上表面20a上。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10:半導體結構
10b:底面
20:載板
20a:上表面
30:乾膜
40:間隙
50:空腔
101:電路元件
102:第一接墊
104:凸塊
202:第二接墊
204:環氧結構部
d1、d3:直徑

Claims (17)

  1. 一種形成連接結構的方法，包含：提供一半導體結構，其具有一第一接墊和一凸塊，分別位於所述半導體結構的一底面上；提供一載板，在其上表面具有一第二接墊，其中所述第二接墊對應於所述凸塊；於所述載板的所述第二接墊上設置一環氧結構部，其中所述環氧結構部的一直徑小於或等於所述凸塊的一直徑；於設置所述環氧結構部後，經由所述環氧結構部將所述凸塊附接至所述第二接墊；以及將所述凸塊附接至所述第二接墊後，以加熱方式固化所述環氧結構部，其中所述環氧結構部在以下條件下固化：將溫度於60分鐘內升至150℃，並在150℃下固化60分鐘。
  2. 如請求項1所述的方法，其中所述環氧結構部是導電的。
  3. 如請求項2所述的方法，其中所述環氧結構部包含銀和環氧樹脂。
  4. 如請求項1所述的方法，其中將所述凸塊附接至所述第二接墊前，所述環氧結構部在室溫下的黏度小於12000cps。
  5. 如請求項1所述的方法，其中將所述凸塊附接至所述第二接墊前，所述環氧結構部在室溫下的黏度大於8000cps。
  6. 如請求項1所述的方法，其中所述環氧結構部的電阻率小於5x10-5ohm-cm。
  7. 如請求項1所述的方法，其中將所述凸塊附接至所述第二接墊後，所述環氧結構部的直徑小於所述凸塊的直徑。
  8. 如請求項1所述的方法，其中將所述凸塊附接至所述第二接墊前，所述環氧結構部的厚度介於0.03mm至0.07mm之間。
  9. 如請求項1所述的方法，其中將所述凸塊附接至所述第二接墊後，所述半導體結構的所述底面與所述載板的所述上表面之間的高度大於10μm。
  10. 如請求項1所述的方法，其中所述環氧結構部係通過鋼板印刷設置在所述第二接墊上。
  11. 如請求項1所述的方法，其中所述半導體結構包含一晶圓或一表面聲波晶片。
  12. 如請求項1所述的方法，其中所述凸塊係為金凸塊。
  13. 如請求項1所述的方法，其中所述第二接墊是金屬墊，包括金、銅、鋁、鈦、氮化鈦、銀或其任意組合。
  14. 如請求項1所述的方法，其中所述載板包含高溫共燒陶瓷基板、低溫 共燒陶瓷基板、矽基板或印刷電路板。
  15. 如請求項1所述的方法，其中另包含：將一乾膜層壓到所述半導體結構和所述載板的所述上表面上。
  16. 如請求項15所述的方法，其中所述乾膜為一環氧樹脂膜。
  17. 如請求項15所述的方法，其中所述乾膜延伸到所述半導體結構的所述底面和所述載板的所述上表面之間的一間隙中。
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KR20210092122A (ko) * 2020-01-14 2021-07-23 파워테크 테크놀로지 인코포레이티드 후면 증착형 차폐층을 갖는 배치-타입 반도체 패키징 구조물 및 그 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
US20050104210A1 (en) * 1996-05-21 2005-05-19 Farnworth Warren M. Use of palladium in IC manufacturing with conductive polymer bump
US20070013067A1 (en) * 1999-01-29 2007-01-18 Kazuto Nishida Electronic component mounting method and apparatus

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
JPH09260431A (ja) * 1996-03-22 1997-10-03 Nec Corp フリップチップ実装の接続構造
US6981317B1 (en) * 1996-12-27 2006-01-03 Matsushita Electric Industrial Co., Ltd. Method and device for mounting electronic component on circuit board
US6064120A (en) * 1997-08-21 2000-05-16 Micron Technology, Inc. Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes
JP3625646B2 (ja) * 1998-03-23 2005-03-02 東レエンジニアリング株式会社 フリップチップ実装方法
US6189208B1 (en) * 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6821888B2 (en) * 2000-07-07 2004-11-23 Chartered Semiconductor Manufacturing Ltd. Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding
US20030047339A1 (en) * 2001-09-12 2003-03-13 Lutz Michael A. Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same
JP2003100803A (ja) * 2001-09-27 2003-04-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
US7154206B2 (en) * 2002-07-31 2006-12-26 Kyocera Corporation Surface acoustic wave device and method for manufacturing same
AU2002343595A1 (en) * 2002-08-02 2004-02-23 Bae Systems Information And Electronic Systems Integration Inc. High-density interconnection of temperature sensitive electronic devices
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US8900931B2 (en) * 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package
US8004076B2 (en) * 2008-09-30 2011-08-23 Intel Corporation Microelectronic package with carbon nanotubes interconnect and method of making same
US20130234344A1 (en) * 2012-03-06 2013-09-12 Triquint Semiconductor, Inc. Flip-chip packaging techniques and configurations
JP6438790B2 (ja) * 2015-02-06 2018-12-19 デクセリアルズ株式会社 半導体装置の製造方法、及びアンダーフィルフィルム
KR102600926B1 (ko) * 2016-08-24 2023-11-14 삼성디스플레이 주식회사 반도체 칩, 표시패널 및 전자장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
US20050104210A1 (en) * 1996-05-21 2005-05-19 Farnworth Warren M. Use of palladium in IC manufacturing with conductive polymer bump
US20070013067A1 (en) * 1999-01-29 2007-01-18 Kazuto Nishida Electronic component mounting method and apparatus

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