CN111106087B - 连接结构及其形成方法 - Google Patents

连接结构及其形成方法 Download PDF

Info

Publication number
CN111106087B
CN111106087B CN201911029904.6A CN201911029904A CN111106087B CN 111106087 B CN111106087 B CN 111106087B CN 201911029904 A CN201911029904 A CN 201911029904A CN 111106087 B CN111106087 B CN 111106087B
Authority
CN
China
Prior art keywords
epoxy
pad
bump
carrier
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911029904.6A
Other languages
English (en)
Other versions
CN111106087A (zh
Inventor
吴佳芸
邱玉玲
刘慈祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Richwave Technology Corp
Original Assignee
Richwave Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Richwave Technology Corp filed Critical Richwave Technology Corp
Publication of CN111106087A publication Critical patent/CN111106087A/zh
Application granted granted Critical
Publication of CN111106087B publication Critical patent/CN111106087B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/058—Holders; Supports for surface acoustic wave devices
    • H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1085—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

一种用于形成连接结构的方法。首先，提供一半导体结构，所述半导体结构在其底面上分别具有一第一接垫和一凸块。接着提供一载板，在其上表面具有一第二接垫。所述第二接垫对应于所述凸块。一环氧结构部设置在所述载板的所述第二接垫上。所述环氧结构部的直径小于或等于所述凸块的直径。在设置所述环氧结构部之后，将所述凸块经由所述环氧结构部附接到所述第二接垫。

Description

连接结构及其形成方法
技术领域
本发明涉及半导体技术领域。更具体地，本发明涉及半导体结构(semiconductorstructure)与载板(carrier)之间的连接结构及其形成方法。
背景技术
如本领域中已知的，诸如声表面波(Surface Acoustic Wave,SAW)组件等半导体结构在商业应用中经常用作射频(Radio Frequency,RF)和中频(IntermediateFrequency,IF)滤波器，以提供频率选择性和其他电子功能。此外，在组装过程(assemblyprocess)中，通常使用焊料(solder)将半导体结构的凸块(bump)附接(attach)到载板上的接垫(pad)。然而，在焊料回焊过程(solder reflow process)中发生的助焊剂飞溅(fluxsplashing)经常导致半导体结构的底面的污染问题。
因此，在该技术领域中仍需要提供一种用于在半导体结构与载板之间形成连接结构的改进方法，该方法能够解决上述现有技术中的问题和缺点。
发明内容
本发明的目的是提供一种用于形成连接结构的改进方法，其可以避免上述现有技术的缺点。
本发明一方面提供了一种用于形成连接结构的方法。首先，提供一半导体结构，所述半导体结构在其底面上分别具有一第一接垫和一凸块。接着提供一载板，在其上表面具有一第二接垫。所述第二接垫对应于所述凸块。一环氧结构部设置在所述载板的所述第二接垫上。所述环氧结构部的直径小于或等于所述凸块的直径。在设置所述环氧结构部之后，将所述凸块经由所述环氧结构部附接到所述第二接垫。
本发明另一方面提供了一种连接结构。所述连接结构包括一半导体结构，所述半导体结构在其底面上分别具有一第一接垫和一凸块；一载板，在其上表面上具有一第二接垫；以及一环氧结构部，连接于所述凸块和所述第二接垫之间。所述第二接垫对应于所述凸块。根据本发明一实施例，所述环氧结构部的直径小于所述凸块的直径。
附图说明
图1至图3为根据本发明一实施例所绘示的形成连接结构的方法示意性截面图。
图4为根据本发明一实施例所绘示的连接结构的放大截面图。
图5为根据本发明一实施例所绘示的用于形成连接结构的方法流程图。
【符号说明】
1 连接结构
10 半导体结构
10b 底面
20 载板
20a 上表面
30 干膜
40 间隙
50 空腔
101 电路组件
102 第一接垫
104 凸块
202 第二接垫
204 环氧结构部
500 方法
501、502、503、504、505、506 步骤
d1、d2、d3 直径
h 高度
具体实施方式
以下，将参考附图详细描述示例性实施例，以使本领域的普通技术人员容易地实现示例性实施例。本发明构思可以以各种形式体现，而不限于在此阐述的示例性实施例。为了清楚起见，省略了对公知部分的描述，并且相似的附图标记始终指代相似的组件。
因此，以下详细描述不应被理解为限制性的，并且本发明的范围仅由所附权利要求以及这些权利要求所赋予的等同物的全部范围来限定。
请注意，说明书中对“一实施例”、“一个实施例”、“示例性实施例”、“一些实施例”等的引用指示所描述的实施例可以包括特定的特征、结构或特性，但是，每个实施例可能不一定包括特定的特征、结构或特性。而且，这样的用语不一定指相同的实施例。
此外，当结合一实施例描述特定的特征、结构或特性时，无论是否明确描述，与其他实施例结合地影响这种特征、结构或特性都将在相关领域的技术人员的知识范围内。
下文中所用的用语“晶圆(wafer)”和“基板(substrate)”包括具有曝露表面的任何结构，例如，材料层(material layer)沉积(deposit)在该曝露表面上以形成电路结构，该电路结构包括但不限于互连金属线或再分布层(redistribution layer,RDL)。用语“基板”应理解为包括晶圆，但不限于此。用语“基板”还用于指处理期间的半导体结构，并且可以包括已经制造在其上的其他层。
本发明涉及一种连接结构及其形成方法。在半导体结构的组装过程中，通过在载板的接垫上施加导电环氧结构部(epoxy portion)，可以避免半导体结构的底面的污染问题。
图1至图3为根据本发明一实施例所绘示的形成连接结构的方法示意性截面图(cross-sectional view)。如图1所示，首先提供一半导体结构10。根据本发明实施例，半导体结构10可以包括一晶圆或一SAW芯片(chip)。例如，半导体结构10是一SAW芯片，且在半导体结构10的底面10b上分别具有第一接垫102和凸块104。根据一实施例，例如，凸块104是金凸块，但不限于此。凸块104具有直径d1。至少一电路组件101，例如叉指换能器(interdigital transducer,IDT)，可以被设置在半导体结构10的底面10b上。
尽管未在图中示出，但是已知IDT可以是制作在合适的压电基板(piezoelectricsubstrate)上的串接的薄金属条或“指状件(fingers)”。一组指状件连接到输入/输出端子，而另一组指状件连接到第二端子。在单端IDT中，前述第二端子接地。但是，对于差分(differential)输入信号，第二端子是脉冲(pulse)输入/输出端子。
仍参照图1，接着提供一载板20。载板20可以包括在载板20的上表面20a的第二接垫202。根据一实施例，第二接垫202对应于凸块104。组装时，凸块104与第二接垫202对准。在一实施例中，载板20可以包括高温共烧结陶瓷(high-temperature co-fired ceramic,HTCC)基板、低温共烧结陶瓷(low-temperature co-fired ceramic,LTCC)基板、硅(silicon)基板或印刷电路板(printed circuit board,PCB)。根据一实施例，可以在上表面20a上设置防焊屏蔽(solder mask)以保护上表面20a上的铜走线(copper trace)不被氧化。根据一实施例，第二接垫202可以是包括金、铜、铝、钛、氮化钛(titanium nitride)、银或其任何组合的金属接垫。
根据一实施例，将环氧结构部204设置在载板20的第二接垫202上。根据一实施例，可以通过钢板印刷(stencil printing)或本领域中已知的任何合适的方法将环氧结构部204设置在第二接垫202上。
根据一实施例，环氧结构部204的直径d2小于或等于凸块104的直径d1。根据一实施例，环氧结构部204是导电的。例如，环氧结构部204包括银和环氧树脂(epoxy resin)，但不限于此。
如图2所示，在设置环氧结构部204之后，使半导体结构10朝向载板20移动并靠近载板20的上表面20a，直到凸块104与环氧结构部204直接接触，如此使得凸块104经由环氧结构部204附接到第二接垫202上。在将凸块104附接到第二接垫202之后，接着进行一固化(curing)处理，通过加热来固化环氧结构部204。例如，环氧结构部204可以在以下条件下固化：在烤箱(oven)中于60分钟内升温至150℃，并于150℃固化60分钟。
根据一实施例，在将凸块104附接到第二接垫202之前，环氧结构部204在室温下可具有小于12000cps的黏度(viscosity)。根据一实施例，在将凸块104附着到第二接垫202之前，环氧结构部204在室温下可具有大于8000cps的黏度。优选地，在将凸块104附着到第二接垫202之前，选择黏度为小于12000cps(例如，在25℃时)的环氧结构部204，因此在组装过程中可以减少不良的附着(undesirable adhesion)。此外，当通过加热环氧结构部204进行固化处理时，由于选择的黏度范围，环氧结构部204几乎不变形，因此，环氧结构部204几乎不会接触到半导体结构10的底面10b，故能降低半导体结构表面污染的风险。
根据一实施例，环氧结构部204可以具有小于5×10-5Ω·cm的电阻率(resistivity)，以提供更好的电导率并降低对半导体结构10性能的影响。根据一实施例，在将凸块104附接到第二接垫202之前，环氧结构部204可以具有范围在0.03mm至0.07mm之间的厚度。根据一实施例，在将凸块104附接到第二接垫202上之后，环氧结构部204的直径d3小于或等于凸块104的直径d1。
根据一实施例，在将凸块104附接到第二接垫202之后，半导体结构10的底面10b与载板20的上表面20a之间的高度h大于10μm。通过提供这种构造，可以降低对半导体结构的性能的影响。根据一实施例，凸块104不与第二接垫202物理接触(physical contact)。
如图3所示，接着将干膜(dry film)30层压(laminated)到半导体结构10和载板20的上表面20a上。根据一实施例，干膜30可以包括环氧树脂膜(epoxy resin film)。根据一实施例，干膜30可以延伸到半导体结构10的底面10b和载板20的上表面20a之间的间隙(gap)40中。半导体结构10的电路组件101位于空腔(cavity)50内，密封(sealed)在干膜30、半导体结构10的底面10b和载板20的上表面20a之间。
使用本发明优点说明如下。首先，施加环氧结构部204，可以省略传统的焊料回焊过程，因此降低了污染半导体结构10的底面10b的风险。其次，通过控制环氧结构部204的直径和厚度，可以减小环氧结构部204和凸块104的侧边缘之间的接触面积，这可以降低环氧结构部204通过凸块104的侧边缘接触半导体结构10的底面10b的风险。通过选择具有合适黏度的环氧结构部204，在组装过程中可以减少不良的附着且能够降低半导体结构10表面污染的风险。通过选择具有合适电阻率的环氧结构部204，可以降低对半导体结构10性能的影响。此外，因为可以保持半导体结构10的底面10b与载板20的上表面20a之间的适当高度h，亦可降低对半导体结构10性能的影响。因此，本发明所提供的方法可以显著提高将SAW芯片组装到载板上的可靠性。
图4为根据本发明一实施例所绘示的连接结构的放大截面图，其中相同的附图标记表示相同的组件、区域或层。如图4所示，连接结构1包括半导体结构10，在半导体结构10的底面10b上分别具有第一接垫102和凸块104。提供一载板20，在载板20的上表面20a上具有第二接垫202。第二接垫202对应于凸块104。连接结构1还包括连接在凸块104和第二接垫202之间的环氧结构部204。在将凸块104附接到第二接垫202之后，环氧结构部204的直径d3小于或等于凸块104的直径d1。
根据一实施例，半导体结构10可以包括晶圆或SAW芯片。根据一实施例，载板20可以包括HTCC基板、LTCC基板，硅基板或PCB。根据一实施例，凸块是金凸块。根据一实施例，第二接垫202是金属垫，包括金、铜、铝、钛、氮化钛、银或其任何组合。
根据一实施例，环氧结构部204是导电的。根据一实施例，环氧结构部204可以包括银和环氧树脂。根据一实施例，环氧结构部204可以具有小于5×10-5Ω·cm的电阻率。根据一实施例，半导体结构10的底面10b与载板20的上表面20a之间的高度h大于10μm。
根据一实施例，连接结构1可以进一步包括层压在半导体结构10和载板20的上表面20a上的干膜30。根据一实施例，干膜30可以包括环氧树脂膜。半导体结构10的电路组件101位于空腔50内，空腔50被密封在干膜30、半导体结构10的底面10b和载板20的上表面20a之间。
请参考图5，并简要地参考图1至图3。图5为根据本发明一实施例所绘示的用于形成连接结构的方法500流程图。如图4和图5所示，在步骤501中，提供半导体结构10。半导体结构10包括在半导体结构10的底面10b上的第一接垫102和凸块104。在步骤502中，提供在其上表面20a上具有第二接垫202的载板20。第二接垫202对应于凸块104。根据一实施例，第二接垫202与凸块104对准。在步骤503中，将环氧结构部204设置在载板20的第二接垫202上。环氧结构部204的直径d2小于或等于凸块104的直径d1。在步骤504中，在设置环氧结构部204之后，凸块104通过环氧结构部204附接到第二接垫202。在步骤505中，在将凸块104附接到第二接垫202之后，通过加热来固化环氧结构部204。在步骤506中，将干膜30层压到半导体结构10和载板20的上表面20a上。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的等同变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种形成连接结构的方法，其特征在于，包含：
提供一半导体结构，其具有一第一接垫和一凸块，分别位于所述半导体结构的一底面上；
提供一载板，在其上表面具有一第二接垫，其中所述第二接垫对应于所述凸块；
于所述载板的所述第二接垫上设置一环氧结构部，其中所述环氧结构部的一直径小于或等于所述凸块的一直径；以及
于设置所述环氧结构部后，经由所述环氧结构部将所述凸块附接至所述第二接垫；其中，
另包含：将所述凸块附接至所述第二接垫后，以加热方式固化所述环氧结构部；
所述环氧结构部在以下条件下固化：将温度于60分钟内升至150℃，并在150℃下固化60分钟。
2.如权利要求1所述的方法，其特征在于，其中所述环氧结构部是导电的。
3.如权利要求2所述的方法，其特征在于，其中所述环氧结构部包含银和环氧树脂。
4.如权利要求1所述的方法，其特征在于，其中将所述凸块附接至所述第二接垫前，所述环氧结构部在室温下的黏度小于12000cps。
5.如权利要求1所述的方法，其特征在于，其中将所述凸块附接至所述第二接垫前，所述环氧结构部在室温下的黏度大于8000cps。
6.如权利要求1所述的方法，其特征在于，其中所述环氧结构部的电阻率小于5x10-5Ω·cm。
7.如权利要求1所述的方法，其特征在于，其中将所述凸块附接至所述第二接垫后，所述环氧结构部的直径小于所述凸块的直径。
8.如权利要求1所述的方法，其特征在于，其中将所述凸块附接至所述第二接垫前，所述环氧结构部的厚度介于0.03mm至0.07mm之间。
9.如权利要求1所述的方法，其特征在于，其中将所述凸块附接至所述第二接垫后，所述半导体结构的所述底面与所述载板的所述上表面之间的高度大于10μm。
10.如权利要求1所述的方法，其特征在于，其中所述环氧结构部是通过钢板印刷设置在所述第二接垫上。
11.如权利要求1所述的方法，其特征在于，其中所述半导体结构包含一晶圆或一声表面波芯片。
12.如权利要求1所述的方法，其特征在于，其中所述凸块为金凸块。
13.如权利要求1所述的方法，其特征在于，其中所述第二接垫是金属垫，包括金、铜、铝、钛、氮化钛、银或其任意组合。
14.如权利要求1所述的方法，其特征在于，其中所述载板包含高温共烧结陶瓷基板、低温共烧结陶瓷基板、硅基板或印刷电路板。
15.如权利要求1所述的方法，其特征在于，其中另包含：
将一干膜层压到所述半导体结构和所述载板的所述上表面上。
16.如权利要求15所述的方法，其特征在于，其中所述干膜为一环氧树脂膜。
17.如权利要求15所述的方法，其特征在于，其中所述干膜延伸到所述半导体结构的所述底面和所述载板的所述上表面之间的一间隙中。
CN201911029904.6A 2018-10-28 2019-10-25 连接结构及其形成方法 Active CN111106087B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201862751690P 2018-10-28 2018-10-28
US62/751,690 2018-10-28
US62/751690 2018-10-28
US16/658185 2019-10-21
US16/658,185 US10923365B2 (en) 2018-10-28 2019-10-21 Connection structure and method for forming the same
US16/658,185 2019-10-21

Publications (2)

Publication Number Publication Date
CN111106087A CN111106087A (zh) 2020-05-05
CN111106087B true CN111106087B (zh) 2022-03-18

Family

ID=70327389

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911029904.6A Active CN111106087B (zh) 2018-10-28 2019-10-25 连接结构及其形成方法

Country Status (3)

Country Link
US (1) US10923365B2 (zh)
CN (1) CN111106087B (zh)
TW (1) TWI729544B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210092122A (ko) * 2020-01-14 2021-07-23 파워테크 테크놀로지 인코포레이티드 후면 증착형 차폐층을 갖는 배치-타입 반도체 패키징 구조물 및 그 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
JPH09260431A (ja) * 1996-03-22 1997-10-03 Nec Corp フリップチップ実装の接続構造
CN107785347A (zh) * 2016-08-24 2018-03-09 三星显示有限公司 半导体芯片和电子装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
US6558979B2 (en) * 1996-05-21 2003-05-06 Micron Technology, Inc. Use of palladium in IC manufacturing with conductive polymer bump
EP0954208A4 (en) * 1996-12-27 2002-09-11 Matsushita Electric Ind Co Ltd METHOD AND DEVICE FOR FIXING AN ELECTRONIC COMPONENT ON A CIRCUIT BOARD
US6064120A (en) * 1997-08-21 2000-05-16 Micron Technology, Inc. Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes
JP3625646B2 (ja) * 1998-03-23 2005-03-02 東レエンジニアリング株式会社 フリップチップ実装方法
US6189208B1 (en) * 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6926796B1 (en) * 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6821888B2 (en) * 2000-07-07 2004-11-23 Chartered Semiconductor Manufacturing Ltd. Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding
US20030047339A1 (en) * 2001-09-12 2003-03-13 Lutz Michael A. Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same
JP2003100803A (ja) * 2001-09-27 2003-04-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
US7154206B2 (en) * 2002-07-31 2006-12-26 Kyocera Corporation Surface acoustic wave device and method for manufacturing same
JP2005535122A (ja) * 2002-08-02 2005-11-17 ビーエイイー・システムズ・インフォメーション・アンド・エレクトロニック・システムズ・インテグレイション・インコーポレーテッド 感温電気デバイスの高密度相互接続
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US8900931B2 (en) * 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package
US8004076B2 (en) * 2008-09-30 2011-08-23 Intel Corporation Microelectronic package with carbon nanotubes interconnect and method of making same
US20130234344A1 (en) * 2012-03-06 2013-09-12 Triquint Semiconductor, Inc. Flip-chip packaging techniques and configurations
JP6438790B2 (ja) * 2015-02-06 2018-12-19 デクセリアルズ株式会社 半導体装置の製造方法、及びアンダーフィルフィルム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001542A (en) * 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
JPH09260431A (ja) * 1996-03-22 1997-10-03 Nec Corp フリップチップ実装の接続構造
CN107785347A (zh) * 2016-08-24 2018-03-09 三星显示有限公司 半导体芯片和电子装置

Also Published As

Publication number Publication date
US10923365B2 (en) 2021-02-16
US20200135497A1 (en) 2020-04-30
CN111106087A (zh) 2020-05-05
TWI729544B (zh) 2021-06-01
TW202038342A (zh) 2020-10-16

Similar Documents

Publication Publication Date Title
US6710682B2 (en) Surface acoustic wave device, method for producing the same, and circuit module using the same
JP3503133B2 (ja) 電子デバイス集合体と電子デバイスの接続方法
JP2002261582A (ja) 弾性表面波デバイスおよびその製造方法ならびにそれを用いた回路モジュール
JP4636882B2 (ja) 気密に密封された素子、及びこれを製造するための方法
JP3772702B2 (ja) 弾性表面波装置の製造方法
JP4135565B2 (ja) 電子回路装置およびその製造方法
JP4689704B2 (ja) 圧電部品及びその製造方法
JP2012182604A (ja) 弾性波フィルタ部品
JP2010050539A (ja) 圧電部品及びその製造方法
JPH1155066A (ja) 表面弾性波装置およびその製造方法
JP2002100877A (ja) セラミック多層基板の表面電極構造及び表面電極の製造方法
JP2001189337A (ja) 電極バンプおよびそれを用いた半導体素子並びに半導体装置
JP2008135971A (ja) 弾性波デバイス
CN111106087B (zh) 连接结构及其形成方法
US9941461B2 (en) Electronic component element and composite module including the same
JPH06204291A (ja) 半導体装置
JP2007158989A (ja) 電子部品
JP2007189501A (ja) 電子部品
JP2005110017A (ja) 高周波フィルタモジュール及びその製造方法
JPH01192125A (ja) 半導体装置の実装構造
JP2004129193A (ja) 弾性表面波装置
JP2002261203A (ja) バンプ付電子部品の実装構造
JPS6290938A (ja) 半導体装置
JPH10340933A (ja) 半導体装置の製造方法
JP2002076828A (ja) 弾性表面波素子

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant