CN107785347A - 半导体芯片和电子装置 - Google Patents
半导体芯片和电子装置 Download PDFInfo
- Publication number
- CN107785347A CN107785347A CN201710733545.7A CN201710733545A CN107785347A CN 107785347 A CN107785347 A CN 107785347A CN 201710733545 A CN201710733545 A CN 201710733545A CN 107785347 A CN107785347 A CN 107785347A
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- Prior art keywords
- semiconductor chip
- conductive
- polymeric layer
- cored
- metal
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Classifications
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- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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Abstract
提供了一种半导体芯片和电子装置。该半导体芯片包括:基底;一个或更多个导电焊盘,设置在基底上;一个或更多个凸起,电连接到一个或更多个导电焊盘,其中,一个或更多个凸起包括:金属芯;聚合物层,设置在金属芯的表面的上方;导电涂层,设置在聚合物层的表面的上方并且电连接到一个或更多个导电焊盘。
Description
本申请要求于2016年8月24日提交的第10-2016-0107764号韩国专利申请的优先权和权益,出于所有目的,通过引用将上述申请包含于此,如同在这里充分阐述一样。
技术领域
发明总体上涉及具有连接端子的半导体芯片、显示面板和电子装置,更具体地,涉及在其中复合金属-聚合物结构可被用作连接端子以提供高度可靠的连接结构和/或稳定连接的半导体芯片、显示面板和电子装置。
背景技术
近来,按照对电子装置的高性能和集成的需求,半导体芯片中提供的连接端子的数量迅速增加。因此,半导体芯片的每个连接端子的尺寸和在连接端子之间的节距迅速减小。例如,在安装在显示面板中的驱动器集成电路(IC)的情况下,通常需要将连接端子之间的节距设计为诸如10μm至15μm或更小的精细的水平。
当使用诸如各向异性导电膜(ACF)的粘合剂在诸如显示面板的电子装置中安装需要精细节距的半导体芯片时,短路缺陷或开路故障的可能性增加。例如,在半导体芯片中设置的某些相邻连接端子的侧表面中密集布置的ACF内部包括的导电粒子可能导致相邻连接端子之间的短路缺陷,或者,如果将ACF的导电颗粒不适当地设置在与具有微小尺寸的连接端子中的至少一些对应的位置处,那么所述导电颗粒会导致开路故障。
在该背景技术部分公开的上述信息仅用于促进对发明构思的背景的理解,因此,它可包含不形成对本领域普通技术人员来讲在该国已经知晓的现有技术的信息。
发明内容
根据发明原理构造的半导体芯片、显示面板和电子装置通过提供使电子组件(诸如半导体芯片、显示面板或电子装置)之间的连接稳定的高度可靠的连接结构来克服上述缺陷或缺点中的一个或更多个。
另外的方面将在随后的详细描述中进行阐述,并且部分地,通过公开将是明显的,或者可通过发明构思的实践而被获知。
根据发明的一个方面,半导体芯片包括基底、设置在基底上的一个或更多个导电焊盘以及电连接到一个或更多个导电焊盘上的一个或更多个凸起。一个或更多个凸起包括:金属芯;聚合物层,设置在金属芯的表面的上方;导电涂层,设置在聚合物层的表面的上方并且电连接到一个或更多个导电焊盘。
聚合物层可以具有1μm至7μm的厚度。
聚合物层可以直接邻近于金属芯的表面并且可以覆盖金属芯的表面。
导电涂层可以直接邻近于聚合物层的表面并且可以覆盖聚合物层的表面。
金属芯可以包括凸表面,聚合物层可以覆盖金属芯的凸表面。
聚合物层可以包括凸表面,导电涂层可以覆盖聚合物层的凸表面。
导电涂层可以包括一个或更多个金属层。
半导体芯片还可以包括:绝缘层,设置在一个或更多个导电焊盘上方,并且暴露一个或更多个导电焊盘中的至少一个区域。
一个或更多个凸起可以接触至少一个暴露区域。
一个或更多个凸起可以设置在一个或更多个导电焊盘上,并且可以具有从由圆顶形状或半球形状组成的组中选择的凸形状,凸形状在远离基底的方向上延伸。
根据发明的另一方面,显示面板包括:基底;多个连接焊盘,设置在基底的第一区域中;多个突出焊盘,分别连接到多个连接焊盘。多个突出焊盘中的至少一些包括金属芯、覆盖金属芯的表面的聚合物层以及覆盖聚合物层的表面的导电涂层。
金属芯中的至少一些可以具有远离基底延伸的凸表面,并且可以设置在多个连接焊盘中的一个连接焊盘的一个表面上,其中,聚合物层可以覆盖至少一些金属芯的凸表面。
聚合物层可以包括凸表面,导电涂层可以覆盖聚合物层的凸表面。
聚合物层可以具有1μm至7μm的厚度。
根据发明的另一方面,电子装置包括:基底,包括多个连接焊盘;半导体芯片,安装在基底上,并且具有多个导电焊盘,多个导电焊盘分别面对多个连接焊盘;多个凸起结构,设置在多个连接焊盘与多个导电焊盘之间,多个凸起结构将多个连接焊盘分别电连接到多个导电焊盘。多个凸起结构中的至少一些包括金属芯、覆盖金属芯的表面的聚合物层以及覆盖聚合物层的表面的导电涂层。
聚合物层可以具有1μm至7μm的厚度。
金属芯可以包括凸表面,聚合物层可以覆盖金属芯的凸表面。
聚合物层可以包括凸表面,导电涂层可以覆盖聚合物层的凸表面。
电子装置还可以包括设置在所述基底与所述半导体芯片之间的非导电粘合层。
电子装置还可以包括包含基底的显示面板。
前面的总体描述和下面的详细描述是示例性的和解释性的,并意图提供对要求保护的主题的进一步解释。
附图说明
附图示出了发明构思的示例性实施例,并与描述一起用于解释发明构思的原理,其中,包括附图以提供发明构思的进一步理解,并且附图被包括在本说明书中并构成本说明书的一部分。
图1是根据发明的原理构造的半导体芯片的实施例的透视图。
图2是根据发明的原理构造的半导体芯片的示出多个连接端子的一个表面的平面图。
图3是根据发明的原理构造的半导体芯片的单个连接端子的平面图。
图4A是根据示例性实施例沿图3的剖面线I-I'截取的图3的连接端子的剖视图。
图4B是根据示例性实施例沿图3的剖面线II-II'截取的图3的连接端子的剖视图。
图5A是根据另一示例性实施例沿图3的剖面线I-I'截取的图3的连接端子的剖视图。
图5B是根据另一示例性实施例沿图3的剖面线II-II'截取的图3的连接端子的剖视图。
图6是根据发明的原理构造的电子装置的透视图。
图7是沿图6的剖面线III-III'截取的图6的电子装置的剖视图。
图8是根据发明的原理构造的显示面板的透视图。
图9是沿图8的剖面线IV-IV'截取的图8的显示面板的剖视图。
图10是根据发明的原理构造的电子装置的剖视图。
具体实施方式
在下面的描述中,为了解释的目的,阐述了许多具体细节,以提供对各种示例性实施例的彻底理解。然而,显而易见的是,各种示例性实施例可以在没有这些具体细节或者在一个或更多个等同布置的情况下实施。在其它情况下,公知的结构和装置以框图的形式示出以避免使各种示例性实施例不必要地模糊。
在附图中,为了清晰和描述的目的,可夸大层、膜、面板、区域等的尺寸和相对尺寸。另外,相同的附图标记表示相同的元件。
当元件或层被称作“在”另一元件或层“上”、“连接到”或“结合到”另一元件或层时,该元件或层可直接在其它元件或层上、直接连接到或结合到其它元件或层,或者可以存在中间元件或中间层。然而,当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”或“直接结合到”另一元件或层时,不存在中间元件或中间层。为了本公开的目的,“X、Y和Z中的至少一个(种/者)”以及“从由X、Y和Z组成的组中选择的至少一个(种/者)”可被解释为仅X、仅Y、仅Z,或者X、Y和Z中的两个(种/者)或更多个(种/者)的任意组合,诸如以XYZ、XYY、YZ和ZZ为例。同样的标号始终表示同样的元件。如这里所用的,术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
虽然在这里可使用术语第一、第二等来描述各种元件、组件、区域、层和/或部分,但是这些元件、组件、区域、层和/或部分不应该受这些术语限制。这些术语用来将一个元件、组件、区域、层或部分与另一个元件、组件、区域、层和/或部分区分开。因此,在不脱离本公开的教导的情况下,下面讨论的第一元件、组件、区域、层和/或部分可被称为第二元件、组件、区域、层和/或部分。
为了描述的目的,在这里可使用诸如“在……之下”、“在……下方”、“下面”、“在……之上”、“上面”等的空间相对术语,并由此来描述如图中所示的一个元件或特征与另一元件或特征的关系。除了附图中绘出的方位之外,空间相对术语还意图包括在使用、运行和/或制造中的设备的不同方位。例如,如果附图中的设备被翻转,则被描述为“在”其它元件或特征“下方”或“之下”的元件将随后被定位为在所述其它元件或特征“之上”。因此,示例性术语“在……下方”可包含上方和下方这两种方位。此外,设备可被另外定位(例如,旋转90度或者在其它方位),这样,相应地解释这里使用的空间相对描述符。
这里使用的术语是出于描述具体实施例的目的,并非意图限制。如这里所使用的,除非上下文另外清楚地指出,否则单数形式的“一个(种/者)”和“该/所述”也意图包括复数形式。此外,当术语“包含”、“包括”和/或它们的变型在本说明书中使用时,说明存在所述特征、整体、步骤、操作、元件、组件和/或它们的组,但不排除存在或附加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
这里参照作为理想化示例性实施例和/或中间结构的示意图的剖视图来描述各种示例性实施例。如此,将预计由例如制造技术和/或公差导致的示出的形状的变化。因此,这里公开的示例性实施例不应被解释为局限于具体示出的区域的形状,而是将包括因例如制造导致的形状的偏差。例如,示出为矩形的注入区域将通常在其边缘处具有圆形的或弯曲的特征和/或注入浓度的梯度,而不是从注入区域到非注入区域的二元变化。同样,通过注入形成的掩埋区会导致在掩埋区和发生注入的表面之间的区域的某些注入。因此,附图中所示的区域本质上是示意性的,它们的形状不意图示出装置的区域的实际形状,并且不意图是限制性的。
除非另有定义,否则这里使用的所有术语(包括技术术语和科学术语)具有与本公开作为其一部分的领域的普通技术人员所通常理解的意思相同的意思。除非这里明确地如此定义,否则术语(诸如在通用字典中定义的术语)应该被解释为具有与在相关领域的上下文中它们的意思一致的意思,并且将不以理想化或者过于形式化的含义来解释它们。
图1是根据发明的原理构造的半导体芯片的实施例的透视图。图2是根据发明的原理构造的半导体芯片的示出多个连接端子的一个表面的平面图。例如,图2示出半导体芯片的一个表面,在其上设置有一个或更多个连接端子。
参照图1和图2,根据示例性实施例的半导体芯片100包括基底110、设置在基底110的至少一个表面上的一个或更多个连接端子120。半导体芯片100可以包括以预定的节距布置在同一表面(例如,下表面)上的多个连接端子120。
基底110可以是硅晶片。然而,基底110不限于此,可以改变基底110的材料和/或形状。各种电路装置(未示出)可以形成或设置在基底110上。用于将电路装置电连接到电子装置(例如,显示面板)的连接端子120可以形成或设置在基底110的至少一个表面上。
连接端子120中的每个可以包括导电焊盘和电连接到导电焊盘的凸起。连接端子120可以包括用于发送半导体芯片100的输入/输出信号的输入/输出端子。例如,半导体芯片100可以包括布置在至少一行中的多个输入端子120a和多个输出端子120b。可以布置输入端子120a同时与输出端子120b分隔开预定的距离或更大的距离。
为便于描述,图2示出了连接端子120在水平方向和竖直方向上规则地布置在半导体芯片100的一个表面上,但是发明构思不限于此。即,可以对连接端子120的尺寸、数量、节距和/或排列结构作出各种改变。
图3是根据发明的原理构造的半导体芯片的单个连接端子的平面图。图4A是沿图3的剖面线I-I'截取的图3的连接端子的剖视图,图4B是根据示例性实施例沿图3的剖面线II-II'截取的图3的连接端子的剖视图。为便于描述,图3、图4A和图4B仅示出了连接端子的一个实施例,但图1和图2中示出的连接端子中的至少一些可以具有彼此相似或基本相同的结构。另外,图3示出了构成连接端子的导电焊盘和凸起两者具有四边形形状,但是发明构思不限于此。即,可以对导电焊盘和/或凸起的形状作出各种改变。此外,在图3中,为了清楚地示出构成连接端子的对应元件之间的位置关系还示出了绝缘层,绝缘层的边界用虚线示出。
参照图3、图4A和图4B,每个连接端子120包括设置在基底110上的导电焊盘121和电连接到导电焊盘121的凸起122。导电焊盘121可以与基底110一起形成半导体芯片100的主体部。例如,导电焊盘121可以与电路层(未示出)一起形成在基底110的至少一个表面上,以与电路层一起形成半导体芯片100的主体部。
凸起122可以通过导电焊盘121的未被绝缘层130覆盖的一个区域电连接到导电焊盘121。导电焊盘121和凸起122可以彼此叠置。例如,凸起122可以设置在导电焊盘121的一个表面(例如,上表面)上以与导电焊盘121叠置。设置有导电焊盘121的区域的面积可以比设置有凸起122的区域的面积大,但发明构思不限于此。导电焊盘121可以被凸起122和/或绝缘层130覆盖,因此,可以不暴露于外部。
一层或更多层缓冲层112可以设置在基底110与导电焊盘121之间。缓冲层112可以包括一层或更多层的氧化层或氮化层,但发明构思不限于此。例如,缓冲层112可以由氧化硅(SiO2)层形成。
导电焊盘121可以包括一层或更多层导电层,例如,一层或更多层金属层。例如,导电焊盘121可被实现为由包括钛(Ti)或金(Au)的金属层形成的单层或者包括由彼此不同的金属形成的第一金属层和第二金属层的多层。然而,导电焊盘121的材料不限于前述材料,且可被改变。例如,导电焊盘121可以包括金属、它们的合金、导电聚合物、导电金属氧化物中的至少一种。可以形成导电焊盘121的金属可以包括:铜(Cu)、银(Ag)、金(Au)、铂(Pt)、钯(Pd)、镍(Ni)、锡(Sn)、铝(Al)、钴(Co)、铑(Rh)、铱(Ir)、铁(Fe)、钌(Ru)、锇(Os)、锰(Mn)、钼(Mo)、钨(W)、铌(Nb)、钽(Ta)、钛(Ti)、铋(Bi)、锑(Sb)和/或铅(Pb)。可以形成导电焊盘121的导电聚合物可以包括:聚噻吩化合物、聚吡咯化合物、聚苯胺化合物、聚乙炔化合物和聚苯醚化合物和/或它们的混合物。例如,在具体实施例中,可以使用聚噻吩化合物中的PEDOT/PSS化合物以形成导电焊盘121。可以形成导电焊盘121的导电金属氧化物可以包括:氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锑锌(AZO)、氧化铟锡锌(ITZO)、氧化锌(ZnO)和/或氧化锡(SnO2)。此外,除了前述导电材料之外,只要材料能够提供导电性,材料即可用作形成导电焊盘121的材料。此外,导电焊盘121的结构没有具体的限制,可以以单层或多层进行各种实施。
导电焊盘121的尺寸和/或相邻导电焊盘121(包括在相邻连接端子120中的导电焊盘)之间的节距没有具体的限制。根据示例性实施例的凸起122的结构可以稳定在连接端子120与用于具有微小尺寸和/或精细节距的连接端子120的电子装置的连接焊盘之间的连接。例如,导电焊盘121可以具有10μm至15μm的微小尺寸和/或精细节距。
绝缘层130可以设置在导电焊盘121的至少一个区域的上表面上。绝缘层130可以包括暴露导电焊盘121的至少一个区域(例如,接合区域或接触区域)的开口。例如,可以将绝缘层130图案化以仅覆盖导电焊盘121的边界区域且暴露导电焊盘121的中心部分。绝缘层130可以设置成覆盖导电焊盘121的上表面的边界且沿着基底110和导电焊盘121的表面的轮廓。绝缘层130可以设置为保护半导体芯片100的钝化层。
绝缘层130可以包括一层或更多层氧化物层或氮化物层,但不限于此。例如,绝缘层130可以由氮化硅SiNx层形成。
凸起122可以布置为与导电焊盘121的暴露区域(即,接合区域或接触区域)上的导电焊盘121相接触。例如,凸起122可以在导电焊盘121上,以与导电焊盘121直接接触。然而,发明构思不限于此。即,可以对导电焊盘121与对应于导电焊盘121的凸起122之间的位置关系和连接结构作出各种改变。
凸起122可以布置在导电焊盘121上,且具有在与基底110相对的方向(例如,图4A和图4B中的向上方向)上突出的圆顶或半球的形状。当凸起122以圆顶或半球形状突出时,粘合力由于形成凸起122的聚合物层122b的弹性而增加,从而提供可靠的连接结构。然而,发明构思不限于此,凸起122的形状也可以改变为包括诸如圆柱或多边棱柱的形状的各种形状。
凸起122可以包括金属芯122a、覆盖金属芯122a的表面的聚合物层122b以及与导电焊盘121电连接并覆盖聚合物层122b的表面的导电涂层122c。例如,在凸起122中,金属芯122a和聚合物层122b可以形成具有异质多层结构的芯结构。即,根据示例性实施例的凸起122可以被实现为金属芯聚合物凸起。
金属芯122a、聚合物层122b和导电涂层122c可以被布置为彼此重叠,其中设置有金属芯122a、聚合物层122b和导电涂层122c的面积可以依次增加。例如,聚合物层122b可被设置为覆盖金属芯122a的突出表面且具有比金属芯122a的面积大的面积,导电涂层122c可被设置为覆盖聚合物层122b的突出表面且具有比聚合物层122b的面积大的面积。例如,聚合物层122b可以形成为完全地覆盖金属芯122a的整个暴露表面,导电涂层122c可以形成为完全地覆盖聚合物层122b的整个暴露表面。当聚合物层122b完全地覆盖金属芯122a的表面时,凸起122可以通常具有均匀的弹性。此外,当导电涂层122c完全地覆盖聚合物层122b的表面时,可以稳定地确保凸起122的导电性。
导电涂层122c可以与导电焊盘121接触且覆盖导电焊盘121的上表面中的暴露区域(例如,在由图3和图4B中的绝缘层130的内边缘线限定的开口区域中未被聚合物层122b覆盖的区域),所述暴露区域未被金属芯122a、聚合物层122b和绝缘层130覆盖,从而导电涂层122c可以电连接到导电焊盘121。然而,发明构思不限于此,可以改变导电焊盘121和凸起122之间的连接结构。
金属芯122a可以具有5μm至6μm的厚度(或高度)H1。例如,金属芯122a可以形成为具有基于导电焊盘121的一个表面(接触金属芯122a的一个表面)的5μm至6μm的厚度H1。然而,金属芯122a的厚度H1不限于此,金属芯122a的厚度H1和形成面积可以根据导电焊盘121和/或凸起122的尺寸和/或节距而改变。此外,金属芯122a的厚度H1可以根据凸起122所需的弹性程度而改变。例如,金属芯122a的厚度H1可被设定为与聚合物层122b的厚度H2对应,所述厚度H2根据凸起122所需的弹性范围和凸起122的整体厚度(H1+H2+H3)来设定。即,金属芯122a的厚度H1可以综合考虑以下情况来确定:聚合物层122b的设定的厚度H2以及考虑导电焊盘121和/或凸起122的节距等而设定的整体厚度(H1+H2+H3)。
金属芯122a可由一层或更多层的导电层形成,所述导电层由金(Au)、锡(Sn)、镍(Ni)、钛(Ti)及它们的合金中的至少一种形成。然而,发明构思不限于此,可以改变形成金属芯122a的导电材料。例如,金属芯122a可以包括从由铜(Cu)、银(Ag)、金(Au)、铂(Pt)、钯(Pd)、镍(Ni)、锡(Sn)、铝(Al)、钴(Co)、铑(Rh)、铱(Ir)、铁(Fe)、钌(Ru)、锇(Os)、锰(Mn)、钼(Mo)、钨(W)、铌(Nb)、钽(Ta)、钛(Ti)、铋(Bi)、锑(Sb)和铅(Pb)组成的组中选择的至少一种材料或包含所述材料的合金。
聚合物层122b可以形成为覆盖金属芯122a的表面且具有比金属芯122a的面积更大的面积。例如,聚合物层122b可以涂覆在金属芯122a的表面上,以完全地覆盖包括金属芯122a的上表面和侧表面的表面。
当假设考虑到间距条件等将凸起122的整个厚度(H1+H2+H3)设定为8μm至15μm时,聚合物层122b可以薄地涂覆在金属芯122a的表面上以具有1μm至3μm的厚度(或高度)H2。然而,聚合物层122b的厚度H2不限于此,聚合物层122b的厚度H2可以根据凸起122所需的弹性范围和/或聚合物层122b的材料而变化。
当聚合物层122b的厚度H2过小,例如,为1μm或更小时,可能难以获得具有根据环境变化或从外部施加的冲击提供稳定的连接结构所需的程度的弹性。此外,当聚合物层122b的厚度H2过大,例如,为7μm或更大时,通过电子装置的连接焊盘在压缩工艺期间施加的负载(例如,10MPa或更大的负载)会引起裂纹或撕裂。即,根据示例性实施例,聚合物层122b的厚度H2可以设定在1μm至7μm的范围内,以在提供预定范围的弹性的同时防止裂纹或撕裂。
根据示例性实施例,以包括金属芯122a和聚合物层122b的至少两层的结构形成凸起122的芯结构。因此,凸起122可以形成为将聚合物层122b的弹性限定成确保弹性足够柔顺地对环境变化或外部压力作出反应且稳定连接结构的范围,并且可以在压缩工艺期间防止裂纹或撕裂。例如,可以形成与期望的尺寸和/或节距的连接端子120对应的凸起122,并且其中连接结构稳定在防止聚合物层122b的裂纹或撕裂的范围内的柔顺凸起(compliantbump)122可以通过调节金属芯122a和聚合物层122b的厚度(或高度)H1和H2、尺寸和/或材料来形成。
聚合物层122b可以由具有弹性的聚合物形成,聚合物层122b的材料没有具体的限制。聚合物层122b可以由导电聚合物形成,所述导电聚合物能够提供在半导体芯片100的导电焊盘121与连接到半导体芯片100的电子装置之间传输各种信号和/或电力所需的导电性。例如,聚合物层122b可以由环氧树脂的聚合物材料形成。此外,聚合物层122b可以由单层或多层形成,但聚合物层122b的结构没有具体的限制。
聚合物层122b可以与金属芯122a一起形成凸起122的芯结构,并且芯结构的厚度(或高度)(H1+H2)可以为6μm至9μm。然而,发明构思不限于此,芯结构的厚度(H1+H2)可以设定为其中芯结构可以稳定地与连接到半导体芯片100的电子装置的连接焊盘连接并且可以提供柔顺特性的范围。此外,芯结构的厚度(H1+H2)可以根据连接端子120的尺寸和/或相邻的连接端子120之间的节距作出各种改变。
导电涂层122c可以形成为具有比聚合物层122b的面积更大的面积,并且可以完全覆盖聚合物层122b的表面。例如,导电涂层122c可以与导电焊盘121接触并覆盖导电焊盘121的上表面中的未被金属芯122a、聚合物层122b和绝缘层130覆盖的暴露区域,与聚合物层122b一起电连接到导电焊盘121。例如,导电涂层122c可以在围绕绝缘层130的内边界并且邻近于绝缘层130的内边界的区域中与导电焊盘121相接触。然而,发明构思不限于此,可以改变导电焊盘121和导电涂层122c之间的连接结构。
导电涂层122c可以具有2μm至6μm的厚度(或高度)H3,但不限于此。例如,导电涂层122c的厚度H3可以确定在对应于连接端子120的尺寸和/或相邻连接端子120之间的节距来设定的凸起122的厚度(H1+H2+H3)的范围内,并通过由导电涂层122c稳定地覆盖非导电聚合物层122b的表面来确保凸起122所需的导电性。例如,当连接端子120的尺寸和/或相邻的连接端子120之间的节距为精细的,如10μm至15μm时,凸起122的整体厚度(H1+H2+H3)可以设定为8μm至15μm。然而,凸起122的厚度(H1+H2+H3)不限于此,可以根据半导体芯片100的设计条件而改变。
导电涂层122c可以由涂覆在聚合物层122b的表面上的一个或多个导电层形成。例如,导电涂层122c可以由一层或更多层金属层形成,所述一层或更多层金属层包括从由铜(Cu)、银(Ag)、金(Au)、铂(Pt)、钯(Pd)、镍(Ni)、锡(Sn)、铝(Al)、钴(Co)、铑(Rh)、铱(Ir)、铁(Fe)、钌(Ru)、锇(Os)、锰(Mn)、钼(Mo)、钨(W)、铌(Nb)、钽(Ta)、钛(Ti)、铋(Bi)、锑(Sb)和铅(Pb)组成的组中选择的至少一种材料或包含所述材料的合金,但不限于此。此外,除了前述导电材料之外,只要材料能够提供导电性,该材料可以用作形成导电涂层122c的材料。导电涂层122c由导电材料形成,所述导电材料能够提供向连接到半导体芯片100的电子装置的连接焊盘传输各种信号和/或电力所需的导电性。
根据示例性实施例,包括凸起122的半导体芯片100设置有金属芯聚合物结构。可以提供具有高度可靠的连接结构的半导体芯片100和包括半导体芯片100的电子装置(例如,显示装置)。
更具体地,根据示例性实施例,通过聚合物层122b的柔顺特性,可以提供能够比例如固体金属凸起更柔顺地对各种环境变化和外部压力作出反应的半导体芯片100。因此,可以获得半导体芯片100与连接到半导体芯片100的电子装置之间的稳定的连接结构。
此外,根据示例性实施例,金属芯122a可以设置在聚合物层122b的内部,从而与芯仅由聚合物层形成的结构相比,可以获得简易连接所需的凸起122的厚度(H1+H2+H3)且可以容易地限制弹性的范围。即,聚合物层122b的厚度H2可以比仅由聚合物层122b形成的单个芯结构的厚度小。例如,聚合物层122b的厚度H2可以减小到7μm或更小,从而即使在压缩工艺(接合工艺)期间对凸起122施加预定的负载范围,也可以防止聚合物层122b的裂纹或撕裂。因此,可以降低在压缩工艺期间发生的缺陷,并且可以促进和优化批量生产。
此外,根据示例性实施例,由于涂覆有导电涂层122c而具有导电性的聚合物凸起122可以固定到半导体芯片100。例如,根据示例性实施例,可以在半导体芯片100的一个表面(例如,导电焊盘121的一个表面)上形成多个导电聚合物凸起122。因此,当将半导体芯片100安装在电子装置中时,不需要使用具有导电颗粒的ACF。因此,可以防止由ACF的非均匀分布的导电颗粒引起的短路缺陷或开路故障,并且可以稳定半导体芯片100和电子装置之间的连接结构。
图5A是根据另一示例性实施例沿图3的剖面线I-I'截取的图3的连接端子的剖视图。图5B是根据另一示例性实施例沿图3的剖面线II-II'截取的图3的连接端子的剖视图。在图5A和图5B中,与图3、图4A和图4B示出的实施例相似或相同的组成元件用相同的附图标记来表示,并且将省略其详细描述。
参照图5A和图5B,导电焊盘121和导电涂层122c中的至少一个可以由两层或更多层形成。例如,考虑到导电焊盘121和/或导电涂层122c的电阻值或界面特性,导电焊盘121和导电涂层122c中的至少一个可以形成为包括两层或更多层导电层的叠压结构。
导电焊盘121可以形成为包括其中至少一个区域叠置的第一导电层121a和第二导电层121b的叠压结构。为了描述方便,图5A和图5B示出了第一导电层121a和第二导电层121b具有相同的面积且彼此完全叠置,但发明构思不限于此。即,可以对第一导电层121a和第二导电层121b的尺寸(面积,厚度等)以及第一导电层121a和第二导电层121b的设置结构进行各种改变。
导电涂层122c可以形成为包括其中至少一个区域叠置的第三导电层122c1和第四导电层122c2的叠压结构。例如,可以通过使用导电材料涂覆聚合物层122b的表面两次来稳定地确保凸起122的导电性。
图6是根据发明的原理构造的电子装置的透视图。图7是沿图6的剖面线III-III'截取的图6的电子装置的剖视图。根据示例性实施例,图6和图7将显示装置示出为电子装置的示例,但发明构思不限于显示装置。在图6和图7中,与图1至图5的实施例中描述的部件类似的部件用相同的附图标记来表示,为了清楚起见,其详细描述是不必要的且省略其详细描述。
参照图6和图7,电子装置(例如,显示装置)包括显示面板200和安装在显示面板200上的半导体芯片100。
显示面板200可以包括在至少有效区域AA中彼此叠置的第一基底210和第二基底220以及设置在第一基底210的非有效区域NA中的多个连接焊盘211。有效区域AA是至少设置有像素(未示出)的区域,并且可以指显示图像的区域。非有效区域NA指除了有效区域AA以外的剩余区域,并且可以包括例如布线区域、焊盘区域和/或各种虚设区域。显示面板200可以是有机发光显示面板、液晶显示面板和等离子体显示面板中的一种,但显示面板200的种类不限于此。
第一基底210和第二基底220中的至少一个可以包括玻璃基底或塑料基底,但不限于此。例如,第一基底210和/或第二基底220可以是包括聚醚砜(PES)、聚丙烯酸酯、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚苯硫醚(PPS)、聚芳酯(PAR)、聚酰亚胺(PI)、聚碳酸酯(PC)、三醋酸纤维素(TAC)和醋酸丙酸纤维素(CAP)中的至少一种的柔性基底。此外,第一基底210和/或第二基底220还可以包括包含玻璃或钢化玻璃的刚性基底。第一基底210和/或第二基底220可以包括由透明材料形成的基底,但不限于此。例如,第一基底210和/或第二基底220可以是不透明和/或反射基底。
第一基底210和第二基底220中的至少一个可以包括包含无机层和有机层中的至少一层的绝缘层。例如,第二基底220可以是包括无机层和有机层中的至少一层的薄膜包封(TFE)层。
连接焊盘211可以由导电材料形成,并且可以连接到各种信号线和/或电源线(未示出)。连接焊盘211可以在显示面板200与半导体芯片100之间传输用于驱动显示面板200的各种信号和/或电力。
半导体芯片100可以安装在第一基底210上的非有效区域NA中。半导体芯片100可以是根据图1至图5B的实施例中的一个实施例的半导体芯片100。即,半导体芯片100可以包括包含基底110和至少一个导电焊盘121的主体部以及电连接到导电焊盘121的至少一个凸起122。对应的导电焊盘121和凸起122可以形成连接端子120。
半导体芯片100可以包括用于驱动显示面板200的驱动电路。例如,未示出的扫描驱动电路和/或数据驱动电路可以集成在半导体芯片100内,例如,集成在半导体芯片100的电路层上。
显示面板200的连接焊盘211中的一个和半导体芯片100的导电焊盘121中的一个可以通过凸起122彼此电连接。例如,连接焊盘211中的一个和导电焊盘121中对应的一个可以设置为使得每个连接焊盘211和导电焊盘121中对应的一个彼此成对并且彼此面对,每个连接焊盘211和面对每个连接焊盘211的对应的一个导电焊盘121可以通过设置在每个连接焊盘211与对应的一个导电焊盘121之间的相应凸起122来电连接。
每个凸起122可以是具有如图3至图5B的实施例中描述的柔顺特性的金属芯聚合物凸起。例如,每个凸起122可以包括金属芯122a、覆盖金属芯122a的表面的聚合物层122b、以及在覆盖聚合物层122b的表面的同时电连接到对应的连接焊盘211的导电涂层122c。即,每个凸起122可以电连接在对应的导电焊盘121和连接焊盘211中对应的一个之间,以使电流在导电焊盘121与连接焊盘211中的一个之间流动。
诸如非导电膜(NCF)的非导电粘合层300可以设置在显示面板200与半导体芯片100之间。非导电粘合层300可以置于显示面板200与半导体芯片100之间,以将半导体芯片100稳定地粘合到显示面板200上。
图8是根据发明的原理构造的显示面板的透视图。图9是沿图8的剖面线IV-IV'截取的图8的显示面板的剖视图。在图8和图9中,与图1至图7的实施例中描述的部件类似的部件用相同的附图标记来表示,为了清楚起见,其详细描述是不必要的且省略其详细描述。
参照图8和图9,也可以将与如参照图1至图7描述的凸起122类似的能够改善连接结构的凸起结构应用于显示面板200的焊盘部230。然而,为了避免与凸起122混淆,施加到焊盘部230的凸起结构将被称为突出焊盘213。
根据示例性实施例,显示面板200包括在至少有效区域AA中彼此叠置的第一基底210和第二基底220以及设置在第一基底210的预定区域(例如,非有效区域NA)中的焊盘部230。
第一基底210和第二基底220中的至少一个可以包括玻璃基底或塑料基底,但不限于此。此外,第一基底210和第二基底220中的至少一个可以包括刚性基底或柔性基底。此外,第一基底210和第二基底220中的至少一个可以包括包含无机层和有机层中的至少一层的薄膜包封层。
根据示例性实施例,焊盘部230包括用于与诸如半导体芯片100的外部电路装置稳定连接的突出焊盘213和分别电连接到突出焊盘213的连接焊盘211。
突出焊盘213可以布置在对应的连接焊盘211的一个表面上。例如,突出焊盘213可以布置成与连接焊盘211的未被钝化层212覆盖的暴露表面直接接触。钝化层212可以完全地覆盖第一基底210的非有效区域NA的一个表面,并且可以具有暴露连接焊盘211的预定区域的开口。
突出焊盘213可以具有与参照图1至图7描述的凸起122的结构基本相同或类似的结构。例如,突出焊盘213可以包括设置在对应的连接焊盘211的一个表面上的金属芯213a、覆盖金属芯213a的表面的聚合物层213b和覆盖聚合物层213b的表面的导电涂层213c。
突出焊盘213可以设置在对应的连接焊盘211的一个表面上并且在与第一基底210相对的方向(例如,向上方向)上突出,聚合物层213b可以覆盖金属芯213a的突出表面。例如,聚合物层213b可以完全地覆盖金属芯213a的整个暴露表面。聚合物层213b可以具有1μm至7μm的厚度,以提供可以稳定连接结构的程度的弹性,并且防止聚合物层213b在压缩工艺期间的裂纹或撕裂。
导电涂层213c可以覆盖聚合物层213b的突出表面。例如,导电涂层213c可以覆盖聚合物层213b的整个暴露表面。
根据上述实施例的显示面板200可以包括突出焊盘213,从而在连接外部电路装置时提供高度可靠的连接结构。
图10是根据发明的原理构造的电子装置的剖视图。在图10中,与图1至图9的实施例中描述的部件类似的部件用相同的附图标记来表示,为了清楚起见,其详细描述是不必要的且省略其详细描述。
参照图10,根据另一示例性实施例的电子装置(例如,显示装置)包括彼此电连接的半导体芯片100和显示面板200。非导电粘合剂层300可以设置在半导体芯片100与显示面板200之间的至少一个区域中。
显示面板200可以是参照图8和图9描述的显示面板。即,显示面板200可以是包括突出焊盘213和电连接到突出焊盘213的连接焊盘211的显示面板,所述突出焊盘213包括金属芯213a、聚合物层213b和导电涂层213c。
半导体芯片100可以包括分别连接到显示面板200的突出焊盘213的连接端子120'。每个连接端子120'可以包括导电焊盘121和电连接到导电焊盘121的凸起122'。
凸起122'可以包括电连接到导电焊盘121的金属凸起。然而,凸起122'不限于金属凸起。例如,半导体芯片100也可以是包括参照图1至图7描述的凸起122的半导体芯片。
半导体芯片100和显示面板200中的任一个,或者半导体芯片100和显示面板200两者可以包括金属芯聚合物凸起结构(凸起122或突出焊盘213)。根据另一示例性实施例,可以在半导体芯片100与显示面板200之间提供可靠的连接结构。
虽然这里已经描述了某些示例性实施例和实施方式,但是其它实施例和修改通过该描述将是明显的。因此,发明构思不限于这样的实施例,而是由给出的权利要求的更广泛的范围以及各种明显的修改和等同布置来限定。
Claims (16)
1.一种半导体芯片,所述半导体芯片包括:
基底;
一个或更多个导电焊盘,设置在所述基底上;
一个或更多个凸起,电连接到所述一个或更多个导电焊盘,
其中,所述一个或更多个凸起包括:金属芯;聚合物层,设置在所述金属芯的表面的上方;导电涂层,设置在所述聚合物层的表面的上方并且电连接到所述一个或更多个导电焊盘。
2.如权利要求1所述的半导体芯片,其中,所述聚合物层具有1μm至7μm的厚度。
3.如权利要求1所述的半导体芯片,其中,所述聚合物层直接邻近于所述金属芯的所述表面并且覆盖所述金属芯的所述表面。
4.如权利要求1所述的半导体芯片,其中,所述导电涂层直接邻近于所述聚合物层的所述表面并且覆盖所述聚合物层的所述表面。
5.如权利要求3所述的半导体芯片,其中,所述金属芯包括凸表面,聚合物层覆盖所述金属芯的所述凸表面。
6.如权利要求4所述的半导体芯片,其中,所述聚合物层包括凸表面,所述导电涂层覆盖所述聚合物层的所述凸表面。
7.如权利要求1所述的半导体芯片,其中,所述导电涂层包括一个或更多个金属层。
8.如权利要求1所述的半导体芯片,所述半导体芯片还包括:
绝缘层,设置在所述一个或更多个导电焊盘上方,并且暴露所述一个或更多个导电焊盘中的至少一个区域。
9.如权利要求8所述的半导体芯片,其中,所述一个或更多个凸起接触所述至少一个暴露的区域。
10.如权利要求1所述的半导体芯片,其中,所述一个或更多个凸起设置在所述一个或更多个导电焊盘上,并且具有从由圆顶形状和半球形状组成的组中选择的凸形状,所述凸形状在远离所述基底的方向上延伸。
11.一种电子装置,所述电子装置包括:
基底,包括多个连接焊盘;
半导体芯片,安装在所述基底上,并且具有多个导电焊盘,所述多个导电焊盘分别面对所述多个连接焊盘;
多个凸起结构,设置在所述多个连接焊盘与所述多个导电焊盘之间,所述多个凸起结构将所述多个连接焊盘分别电连接到所述多个导电焊盘,
其中,所述多个凸起结构中的至少一些包括金属芯、覆盖所述金属芯的表面的聚合物层以及覆盖所述聚合物层的表面的导电涂层。
12.如权利要求11所述的电子装置,其中,所述聚合物层具有1μm至7μm的厚度。
13.如权利要求11所述的电子装置,其中,所述金属芯包括凸表面,聚合物层覆盖所述金属芯的所述凸表面。
14.如权利要求11所述的电子装置,其中,所述聚合物层包括凸表面,所述导电涂层覆盖所述聚合物层的所述凸表面。
15.如权利要求11所述的电子装置,所述电子装置还包括:非导电粘合层,设置在所述基底与所述半导体芯片之间。
16.如权利要求11所述的电子装置,所述电子装置还包括:显示面板,包括所述基底。
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