US20050104210A1 - Use of palladium in IC manufacturing with conductive polymer bump - Google Patents
Use of palladium in IC manufacturing with conductive polymer bump Download PDFInfo
- Publication number
- US20050104210A1 US20050104210A1 US11/008,654 US865404A US2005104210A1 US 20050104210 A1 US20050104210 A1 US 20050104210A1 US 865404 A US865404 A US 865404A US 2005104210 A1 US2005104210 A1 US 2005104210A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- substrates
- palladium
- conductive polymer
- disposing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 title claims abstract description 141
- 229920001940 conductive polymer Polymers 0.000 title claims abstract description 70
- 229910052763 palladium Inorganic materials 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 173
- 238000000034 method Methods 0.000 claims abstract description 76
- 239000004593 Epoxy Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 39
- 238000002161 passivation Methods 0.000 claims description 22
- 238000007772 electroless plating Methods 0.000 claims description 16
- 229920000642 polymer Polymers 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 abstract description 31
- 239000002184 metal Substances 0.000 abstract description 31
- 238000000429 assembly Methods 0.000 abstract description 5
- 230000000712 assembly Effects 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 description 19
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 230000007613 environmental effect Effects 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000010561 standard procedure Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012736 aqueous medium Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/1132—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Definitions
- the present invention relates to an apparatus and a method for forming a conductive polymer bump on a substrate, such as a flip-chip type semiconductor die, a silicon wafer, a printed circuit board, or other substrate (hereinafter referred to generally as a “substrate”). More particularly, the present invention relates to forming a substrate having a palladium metal layer over each contact point of the substrate and forming a flexible conductive polymer bump on each contact point. The present invention also relates to assemblies and methods of connecting one or more of these substrates together or to another substrate.
- a flip chip is a semiconductor chip or die that has bumped terminations spaced around an active surface of the die and is intended for face-to-face attachment to a substrate or another semiconductor die.
- the bumped terminations of the flip chips are usually a “Ball Grid Array” (“BGA”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die, or a “Slightly Larger than Integrated Circuit Carrier” (“SLICC”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
- BGA All Grid Array
- SLICC Lightly Larger than Integrated Circuit Carrier
- the attachment of a flip chip to a substrate or another semiconductor involves aligning the solder balls on the flip chip with a plurality of contact points (configured to be a mirror image of the solder ball arrangement on the flip chip) on the facing surface of the substrate.
- a plurality of solder balls may also be formed on the facing surface of the substrate at the contact points.
- a quantity of liquid flux is often applied to the face of the chip and/or substrate, and the chip and substrate are subjected to elevated temperatures to effect reflowing or soldering of the solder balls on the chip and/or corresponding solder balls on the substrate.
- This connection technology is also referred to as “flip chip attachment” or “C4—Controlled Collapse Chip Connection.”
- High performance microelectronic devices generally comprise a number of flip chips attached to a substrate or printed circuit board (“PCB”) for electrical interconnection to other microelectronic devices.
- PCB printed circuit board
- VLSI very large scale integration
- Flip chip attachment requires the formation of contact terminals on flip chip contact sites, each consisting of a metal pad with a solder ball disposed thereon.
- Flip chip attachment also requires the formation of solder joinable sites (“bond pads”) on the metal conductors of the substrate or PCB which are a mirror-image of the solder ball arrangement on the flip chip.
- the bond pads on the substrate are usually surrounded by non-solderable barriers so that when the solder of the bond pads and of the chip contact sites melts and merges (“reflow”), the surface tension holds the semiconductor chip by solder columns, as if suspended above the substrate. After cooling, the chip is essentially welded face-down by these very small, closely spaced solder column interconnections.
- U.S. Pat. No. 5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate and a semiconductor die with a discontinuous passivation layer. The discontinuities result in vias between the contact points of the substrate and the semiconductor die. A resin with spaced conductive metal particles suspended therein is disposed within the vias to achieve electrical contact between the substrate and the semiconductor die.
- U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to Pasch relates to interconnecting conductive substrates using an interposer having conductive plastic filled vias.
- U.S. Pat. No. 5,478,007 issued Dec. 26, 1995 to Marrs relates to using conductive epoxy as a bond pad structure on a substrate for receiving a coined ball bond on a die to achieve electrical communication between the die and the substrate.
- Such flip chip and substrate attachments are generally comprised of dissimilar materials that expand at different rates on heating. The most severe stress is due to the inherently large thermal coefficient of expansion (“TCE”) mismatch between the plastic and the metal.
- TCE thermal coefficient of expansion
- These electronic packages are subject to two types of heat exposures: process cycles, which are often high in temperature but few in number; and operation cycles, which are numerous but less extreme. If either the flip chip(s) or substrate(s) are unable to repeatedly bear their share of the system thermal mismatch, the electronic package will fracture, which destroys the functionality of the electronic package.
- Burn-in is the process of electrically stressing a device, usually at an elevated temperature and voltage environment, for an adequate period of time to cause failure of marginal devices.
- a chip such as a flip chip
- the chip must be reattached and the burn-in process reinitiated. This requires considerable time and effort which results in increased production costs. Alternately, if the chip has been underfilled and subsequently breaks free during burn-in, the chip is not reworkable and must be discarded.
- TCE mismatch is also applicable to connections made with conductive polymers or resins, because after curing the polymers or resins become substantially rigid.
- the rigid connections are equally susceptible to breakage due to TCE mismatch.
- FIGS. 1 a - 1 e show a contemporary, prior art method of forming a conductive bump arrangement on a substrate.
- a passivation film 102 such as at least one layer of SiO 2 film, Si 3 N 4 film, or the like, is formed over a face surface 104 of a semiconductor wafer 100 which has a conductive electrode 106 , usually an aluminum electrode.
- the passivation film 102 is selectively etched to expose the conductive electrode 106 .
- FIG. 1 b shows a metal layer 108 applied over a face surface 110 of the passivation film 102 by deposition or sputtering.
- a second layer of etch resist film 112 is applied to a face surface 114 of the metal layer 108 .
- the second etch resist film 112 is masked, exposed, and stripped to expose a portion of the metal layer 108 corresponding to the conductive electrode 106 , as shown in FIG. 1 c .
- a solder bump 116 (generally an alloy of lead and tin) is then formed on the exposed portion of the metal layer 108 , as shown in FIG. 1 d , by any known industry technique, such as stenciling, screen printing, electroplating, electrolysis, or the like.
- the second etch resist film 112 is removed and the metal layer 108 is removed using the solder bump 116 as a mask to form the structure shown in FIG. 1 e .
- This conventional bump formation method has drawbacks. The most obvious being the large number of process steps required which results in high manufacturing costs.
- Electroless plating is a metal deposition process, usually in an aqueous medium, occurring through an exchange reaction between metal complexes in solution and the particular metal to be coated which does not require externally applied electric current.
- the process of electroless plating of palladium generally comprises dipping the semiconductor element with the exposed conductive electrodes into a palladium solution wherein the palladium selectively bonds or plates on the conductive electrodes.
- the electroless plating process is a non-vacuum, high volume, high throughput process which can be precisely controlled and uses reliable equipment.
- the entire fabrication can be performed in a less costly cleanroom environment which reduces processing time and cost.
- the '571 patent teaches forming an electroless palladium plated conductive electrode followed by the formation of a metal bump on the palladium plated conductive electrode.
- the present invention relates to an apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point.
- the apparatus and method of the present invention abate the effects of TCE mismatch and reduce the number of steps required to produce substrates.
- the present invention also relates to assemblies comprising one or more of these substrates.
- a preferred method for constructing the apparatus of the present invention comprises providing a substrate, for example a semiconductor wafer, which has at least one conductive electrode, a semiconductor chip which has at least one bond pad, or a printed circuit board.
- a passivation film such as at least one layer of SiO 2 film, Si 3 N 4 film, or the like is formed over a face surface of the substrate. The passivation film is selectively etched to expose each conductive electrode or bond pad.
- the substrate is then submersed in an electroless plating bath containing palladium in solution. The palladium, through an exchange reaction with the exposed conductive electrodes, bonds to an upper surface of the conductive electrode or bond pad thereby plating the conductive electrode or bond pad with a layer of palladium.
- the passivation layer may not be necessary when the material surrounding the conductive electrode or bond pad is inert or is not otherwise susceptible to being plated during the electroless plating process.
- a conductive polymer is preferably applied to an upper surface of the palladium layers to form a conductive polymer bump.
- the conductive polymer bump is preferably a two-stage epoxy which does not completely set, typically referred to as a “B-stage” type epoxy.
- a preferred two-stage epoxy such as RSC 3927-W/-B stage conductor, available from IMR Corporation, Nampa, Id., can be used.
- the conductive polymer used to form the conductive bump usually has a high electrical conductivity metal, such as palladium, gold, silver, or the like, dispersed therein to impart electrical conductivity to the polymer.
- the conductive polymer bump can be formed by any number of known industry standard techniques; however, the preferred method comprises stencil printing the conductive polymer onto the conductive electrode.
- the stencil printing process can be performed in one step or in multiple printing steps wherein a plurality of layers of conductive polymer are applied in succession.
- the stencil printing method for forming the conductive polymer bumps of the present invention is advantageous over presently known fabrication methods, since it is a simpler process (having fewer processing steps) and is less expensive.
- a semiconductor assembly may be fabricated by attaching substrates together in a face-to-face flip chip arrangement.
- the substrates are mechanically attached to and in electrical communication with one another via the plurality of conductive polymer bumps formed on the palladium metal layers of the first substrate, the palladium metal layers of the second substrate, or both.
- An under-fill encapsulant may be disposed between the first substrate and the second substrate for environmental protection and to enhance the attachment of the first substrate and the second substrate.
- FIGS. 1 a - 1 e illustrate side cross-sectional views of a prior art method of forming a conductive bump on a substrate
- FIGS. 2 a - 2 c illustrate side cross-sectional views of the steps of a method of forming a conductive polymer bump on a substrate of the present invention
- FIGS. 3 a - 3 c illustrate side cross-sectional views of the steps of a method of forming a conductive polymer bump on a semiconductor die of the present invention
- FIG. 4 is a side cross-sectional view of a substrate assembly of the present invention.
- FIG. 5 is a side cross-sectional view of a first embodiment of a substrate/chip assembly of the present invention.
- FIGS. 2 a - 2 c illustrate a method of forming a conductive polymer bump on a substrate, such as a silicon wafer, a printed circuit board, or the like, of the present invention.
- FIG. 2 a illustrates an exposed electrode substrate assembly 200 comprising a substrate 202 which has at least one conductive electrode 204 , usually aluminum electrodes, disposed thereon.
- a passivation film 208 may be formed over a face surface 206 of the substrate 202 .
- the passivation film 208 is selectively etched to expose the conductive electrode 204 .
- the exposed electrode substrate assembly 200 is immersed in an electroless plating bath containing palladium in solution, whereby through an exchange reaction the exposed conductive electrodes 204 are selectively plated with a palladium layer 210 atop an upper surface 212 of the conductive electrode 204 , as shown in FIG. 2 b .
- a conductive polymer is applied to an upper surface 214 of the palladium layer 210 to form a conductive polymer bump 216 .
- the conductive polymer bump 216 preferably comprises a two-stage epoxy which does not completely set.
- the conductive polymer used to form the conductive polymer bump 216 preferably has a high electrical conductivity metal, such as palladium, gold, silver, or the like, dispersed therein.
- the conductive polymer bump 216 is preferably formed by stencil printing or stenciling the conductive polymer onto the conductive electrode 204 .
- the passivation film 208 may be stripped from the substrate 202 .
- FIGS. 3 a - 3 c illustrate a method of forming a conductive polymer bump on a printed circuit board of the present invention.
- FIG. 3 a illustrates an exposed bond pad chip assembly 300 comprising a printed circuit board 302 which has at least one bond pad 304 , usually copper pads, disposed thereon.
- the bond pad 304 has a lead 306 (shown in shadow) within the printed circuit board 302 attached to a lower surface 308 of the bond pad 304 .
- a passivation film 310 such as at least one layer of resist polyimide film, or the like, is formed over a face surface 312 of the printed circuit board 302 .
- the passivation film 310 is selectively etched to expose the bond pad 304 .
- the exposed bond pad chip assembly 300 is immersed in an electroless plating bath containing palladium in solution, whereby through an exchange reaction the exposed bond pads 304 are selectively plated with a palladium layer 314 atop an upper surface 316 of the bond pad 304 , as shown in FIG. 3 b .
- a conductive polymer is applied to an upper surface 318 of the palladium layer 314 to form a conductive polymer bump 320 .
- the conductive polymer bump 320 preferably comprises a two-stage epoxy which does not completely set.
- the conductive polymer used to form the conductive polymer bump 320 preferably has a metal, such as palladium, gold, silver, or the like, dispersed therein.
- the conductive polymer bump 320 can be formed in a manner discussed for the conductive polymer bump 216 of FIG. 2 .
- the passivation film 310 may be stripped from the printed circuit board 302 .
- FIG. 4 illustrates a substrate assembly 400 of the present invention.
- the substrate assembly 400 comprises a first substrate 402 with a plurality of conductive electrodes 404 disposed on a facing surface 406 of the first substrate 402 .
- a palladium metal layer 408 is disposed on each conductive electrode 404 by electroless plating.
- the substrate assembly 400 further comprises a second substrate 410 with a plurality of conductive electrodes 412 disposed on a facing surface 414 of the second substrate 410 .
- a palladium metal layer 416 is also disposed on each conductive electrode 412 .
- the first substrate 402 and the second substrate 410 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 418 extending between the first substrate palladium metal layers 408 and the second substrate palladium metal layers 416 .
- An under-fill encapsulant 420 may be disposed between the first substrate 402 and the second substrate 410 for environmental protection and to enhance the attachment of the first substrate 402 and the second substrate 410 .
- FIG. 5 illustrates a first embodiment of a substrate/chip assembly 500 of the present invention.
- the substrate/chip assembly 500 comprises a substrate 502 with a plurality of conductive electrodes 504 disposed on a facing surface 506 of the substrate 502 .
- a palladium metal layer 508 is disposed on each conductive electrode 504 by electroless plating.
- the substrate/chip assembly 500 further comprises a semiconductor chip 510 with a plurality of bond pads 512 disposed on a facing surface 514 of the semiconductor chip 510 .
- a palladium metal layer 516 is also disposed on each bond pad 512 .
- the substrate 502 and the semiconductor chip 510 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 518 extending between the substrate palladium metal layers 508 and the semiconductor die palladium metal layers 516 .
- An under-fill encapsulant 520 may be disposed between the substrate 502 and the semiconductor die 510 for environmental protection and to enhance the attachment of the substrate 502 and the semiconductor chip 510 .
- FIG. 6 illustrates a second embodiment of a substrate/chip assembly 600 of the present invention.
- the substrate/chip assembly 600 comprises a substrate 602 with a plurality of conductive electrodes 604 disposed on a facing surface 606 of the substrate 602 .
- the conductive electrodes 604 may comprise any suitable type metal electrode, such as aluminum.
- the substrate/chip assembly 600 further comprises a semiconductor chip 610 with a plurality of bond pads 612 disposed on a facing surface 614 of the semiconductor chip 610 .
- a palladium metal layer 616 is also disposed on each bond pad 612 .
- the substrate 602 and the semiconductor chip 610 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 618 extending between the substrate conductive electrodes 604 and the semiconductor die palladium metal layers 616 .
- the conductive material in the conductive polymer bumps 618 is capable of making electrical contact with the conductive electrodes 604 and penetrating any coating thereon whether an oxide coating or a passivation layer coating.
- An under-fill encapsulant 620 may be disposed between the substrate 602 and the semiconductor die 610 for environmental protection and to enhance the attachment of the substrate 602 and the semiconductor chip 610 .
- FIGS. 4, 5 and 6 show substrates and/or semiconductor chips which use the palladium layered structures of the present invention, one of the substrates and/or semiconductor chips could be one of industry standard manufacture.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Abstract
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The present invention also relates to assemblies comprising one or more of these substrates.
Description
- This application is a divisional of application Ser. No. 10/430,616, filed May 5, 2003, pending, which is a continuation of application Ser. No. 10/116,962, filed Apr. 5, 2002, now U.S. Pat. No. 6,558,979, issued May 6, 2003, which is a continuation of application Ser. No. 09/645,947, filed Aug. 25, 2000, now U.S. Pat. No. 6,413,862, issued Jul. 2, 2002, which is a continuation of application Ser. No. 09/227,072, filed Jan. 5, 1999, now U.S. Pat. No. 6,159,769, issued Dec. 12, 2000, which is a divisional of application Ser. No. 08/651,816, filed May 21, 1996, now U.S. Pat. No. 5,925,930, issued Jul. 20, 1999.
- 1. Field of the Invention
- The present invention relates to an apparatus and a method for forming a conductive polymer bump on a substrate, such as a flip-chip type semiconductor die, a silicon wafer, a printed circuit board, or other substrate (hereinafter referred to generally as a “substrate”). More particularly, the present invention relates to forming a substrate having a palladium metal layer over each contact point of the substrate and forming a flexible conductive polymer bump on each contact point. The present invention also relates to assemblies and methods of connecting one or more of these substrates together or to another substrate.
- 2. State of the Art
- A flip chip is a semiconductor chip or die that has bumped terminations spaced around an active surface of the die and is intended for face-to-face attachment to a substrate or another semiconductor die. The bumped terminations of the flip chips are usually a “Ball Grid Array” (“BGA”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die, or a “Slightly Larger than Integrated Circuit Carrier” (“SLICC”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
- The attachment of a flip chip to a substrate or another semiconductor involves aligning the solder balls on the flip chip with a plurality of contact points (configured to be a mirror image of the solder ball arrangement on the flip chip) on the facing surface of the substrate. A plurality of solder balls may also be formed on the facing surface of the substrate at the contact points. A quantity of liquid flux is often applied to the face of the chip and/or substrate, and the chip and substrate are subjected to elevated temperatures to effect reflowing or soldering of the solder balls on the chip and/or corresponding solder balls on the substrate. This connection technology is also referred to as “flip chip attachment” or “C4—Controlled Collapse Chip Connection.”
- High performance microelectronic devices generally comprise a number of flip chips attached to a substrate or printed circuit board (“PCB”) for electrical interconnection to other microelectronic devices. For example, a very large scale integration (“VLSI”) chip may be electrically connected to a substrate, printed circuit board, or other next level packaging substrate.
- Flip chip attachment requires the formation of contact terminals on flip chip contact sites, each consisting of a metal pad with a solder ball disposed thereon. Flip chip attachment also requires the formation of solder joinable sites (“bond pads”) on the metal conductors of the substrate or PCB which are a mirror-image of the solder ball arrangement on the flip chip. The bond pads on the substrate are usually surrounded by non-solderable barriers so that when the solder of the bond pads and of the chip contact sites melts and merges (“reflow”), the surface tension holds the semiconductor chip by solder columns, as if suspended above the substrate. After cooling, the chip is essentially welded face-down by these very small, closely spaced solder column interconnections.
- It is also known in the art that conductive polymers or resins can be utilized in lieu of solder balls. U.S. Pat. No. 5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate and a semiconductor die with a discontinuous passivation layer. The discontinuities result in vias between the contact points of the substrate and the semiconductor die. A resin with spaced conductive metal particles suspended therein is disposed within the vias to achieve electrical contact between the substrate and the semiconductor die. U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to Pasch relates to interconnecting conductive substrates using an interposer having conductive plastic filled vias. U.S. Pat. No. 5,478,007 issued Dec. 26, 1995 to Marrs relates to using conductive epoxy as a bond pad structure on a substrate for receiving a coined ball bond on a die to achieve electrical communication between the die and the substrate.
- Such flip chip and substrate attachments (collectively “electronic packages”) are generally comprised of dissimilar materials that expand at different rates on heating. The most severe stress is due to the inherently large thermal coefficient of expansion (“TCE”) mismatch between the plastic and the metal. These electronic packages are subject to two types of heat exposures: process cycles, which are often high in temperature but few in number; and operation cycles, which are numerous but less extreme. If either the flip chip(s) or substrate(s) are unable to repeatedly bear their share of the system thermal mismatch, the electronic package will fracture, which destroys the functionality of the electronic package.
- As an electronic package dissipates heat to its surroundings during operation, or as the ambient system temperature changes, differential thermal expansions cause stresses to be generated in the interconnection structures (e.g., solder ball bonds) between the semiconductor die and the substrate. These stresses produce instantaneous elastic and, most often, plastic strain, as well as time-dependent (plastic and anelastic) strains in the joint, especially within its weakest segment. Thus, the TCE mismatch between chip and substrate will cause a shear displacement to be applied on each terminal which can fracture the solder connection.
- The problem with TCE mismatch becomes evident during the process of burn-in. Burn-in is the process of electrically stressing a device, usually at an elevated temperature and voltage environment, for an adequate period of time to cause failure of marginal devices. When a chip, such as a flip chip, breaks free from the substrate due to TCE mismatch, defective bonds, or the like, the chip must be reattached and the burn-in process reinitiated. This requires considerable time and effort which results in increased production costs. Alternately, if the chip has been underfilled and subsequently breaks free during burn-in, the chip is not reworkable and must be discarded.
- The problems with TCE mismatch are also applicable to connections made with conductive polymers or resins, because after curing the polymers or resins become substantially rigid. The rigid connections are equally susceptible to breakage due to TCE mismatch.
-
FIGS. 1 a-1 e show a contemporary, prior art method of forming a conductive bump arrangement on a substrate. First, as shown inFIG. 1 a, apassivation film 102, such as at least one layer of SiO2 film, Si3N4 film, or the like, is formed over aface surface 104 of asemiconductor wafer 100 which has aconductive electrode 106, usually an aluminum electrode. Thepassivation film 102 is selectively etched to expose theconductive electrode 106.FIG. 1 b shows ametal layer 108 applied over aface surface 110 of thepassivation film 102 by deposition or sputtering. A second layer ofetch resist film 112 is applied to aface surface 114 of themetal layer 108. The secondetch resist film 112 is masked, exposed, and stripped to expose a portion of themetal layer 108 corresponding to theconductive electrode 106, as shown inFIG. 1 c. A solder bump 116 (generally an alloy of lead and tin) is then formed on the exposed portion of themetal layer 108, as shown inFIG. 1 d, by any known industry technique, such as stenciling, screen printing, electroplating, electrolysis, or the like. The secondetch resist film 112 is removed and themetal layer 108 is removed using thesolder bump 116 as a mask to form the structure shown inFIG. 1 e. This conventional bump formation method has drawbacks. The most obvious being the large number of process steps required which results in high manufacturing costs. - U.S. Pat. No. 4,970,571 issued Nov. 13, 1990 to Yamakawa et al. (the '571 patent) relates to a bump formation method which addresses the problems associated with conventional processing methods by using electroless plating of palladium on the conductive electrodes. Electroless plating is a metal deposition process, usually in an aqueous medium, occurring through an exchange reaction between metal complexes in solution and the particular metal to be coated which does not require externally applied electric current. The process of electroless plating of palladium generally comprises dipping the semiconductor element with the exposed conductive electrodes into a palladium solution wherein the palladium selectively bonds or plates on the conductive electrodes. The electroless plating process is a non-vacuum, high volume, high throughput process which can be precisely controlled and uses reliable equipment. The entire fabrication can be performed in a less costly cleanroom environment which reduces processing time and cost. The '571 patent teaches forming an electroless palladium plated conductive electrode followed by the formation of a metal bump on the palladium plated conductive electrode.
- The benefits of using palladium in integrated circuits are discussed in U.S. Pat. No. 4,182,781 issued Jan. 8, 1980, to Hooper et al. (the '781 patent). The '781 patent teaches that palladium forms a unique barrier metal in bump metallization systems which increases yield and reliability of integrated circuit devices designed for flip-chip attachment. It is also disclosed that palladium is compatible with aluminum and has a thermal coefficient of expansion that is sufficiently close to aluminum so that no significant stress problems result. However, the '781 patent does not teach using an electroless plating process to coat the conductive electrode with palladium. However, electroless plating is used to form the copper or nickel bump on the palladium coated conductive electrode.
- It would be advantageous to develop a more efficient technique for forming conductive bumps on a flip chip which eliminates some of the steps required by present industry standard techniques while also abating the effects of TCE mismatch using commercially-available, widely-practiced semiconductor device fabrication techniques.
- The present invention relates to an apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The apparatus and method of the present invention abate the effects of TCE mismatch and reduce the number of steps required to produce substrates. The present invention also relates to assemblies comprising one or more of these substrates.
- A preferred method for constructing the apparatus of the present invention comprises providing a substrate, for example a semiconductor wafer, which has at least one conductive electrode, a semiconductor chip which has at least one bond pad, or a printed circuit board. A passivation film such as at least one layer of SiO2 film, Si3N4 film, or the like is formed over a face surface of the substrate. The passivation film is selectively etched to expose each conductive electrode or bond pad. The substrate is then submersed in an electroless plating bath containing palladium in solution. The palladium, through an exchange reaction with the exposed conductive electrodes, bonds to an upper surface of the conductive electrode or bond pad thereby plating the conductive electrode or bond pad with a layer of palladium.
- It is, of course, understood that the passivation layer may not be necessary when the material surrounding the conductive electrode or bond pad is inert or is not otherwise susceptible to being plated during the electroless plating process.
- A conductive polymer is preferably applied to an upper surface of the palladium layers to form a conductive polymer bump. The conductive polymer bump is preferably a two-stage epoxy which does not completely set, typically referred to as a “B-stage” type epoxy. For example, a preferred two-stage epoxy such as RSC 3927-W/-B stage conductor, available from IMR Corporation, Nampa, Id., can be used. The conductive polymer used to form the conductive bump usually has a high electrical conductivity metal, such as palladium, gold, silver, or the like, dispersed therein to impart electrical conductivity to the polymer.
- The conductive polymer bump can be formed by any number of known industry standard techniques; however, the preferred method comprises stencil printing the conductive polymer onto the conductive electrode. The stencil printing process can be performed in one step or in multiple printing steps wherein a plurality of layers of conductive polymer are applied in succession. The stencil printing method for forming the conductive polymer bumps of the present invention is advantageous over presently known fabrication methods, since it is a simpler process (having fewer processing steps) and is less expensive.
- A semiconductor assembly may be fabricated by attaching substrates together in a face-to-face flip chip arrangement. The substrates are mechanically attached to and in electrical communication with one another via the plurality of conductive polymer bumps formed on the palladium metal layers of the first substrate, the palladium metal layers of the second substrate, or both. An under-fill encapsulant may be disposed between the first substrate and the second substrate for environmental protection and to enhance the attachment of the first substrate and the second substrate.
- The use of a two-step curing epoxy virtually eliminates the problems associated with TCE mismatch. Since the two-step curing epoxy never completely sets to form a rigid matrix, the connections will have an amount of “give” or “flex” during the thermal expansion and contraction of the substrates, while still making a reliable substrate-to-substrate electrical connection. This, in turn, reduces the failure rate of semiconductor assemblies during burn-in and during general use.
- While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
-
FIGS. 1 a-1 e illustrate side cross-sectional views of a prior art method of forming a conductive bump on a substrate; -
FIGS. 2 a-2 c illustrate side cross-sectional views of the steps of a method of forming a conductive polymer bump on a substrate of the present invention; -
FIGS. 3 a-3 c illustrate side cross-sectional views of the steps of a method of forming a conductive polymer bump on a semiconductor die of the present invention; -
FIG. 4 is a side cross-sectional view of a substrate assembly of the present invention; -
FIG. 5 is a side cross-sectional view of a first embodiment of a substrate/chip assembly of the present invention; and -
FIG. 6 is a side cross-sectional view of a second embodiment of a substrate/chip assembly of the present invention. -
FIGS. 2 a-2 c illustrate a method of forming a conductive polymer bump on a substrate, such as a silicon wafer, a printed circuit board, or the like, of the present invention.FIG. 2 a illustrates an exposedelectrode substrate assembly 200 comprising asubstrate 202 which has at least oneconductive electrode 204, usually aluminum electrodes, disposed thereon. Apassivation film 208 may be formed over aface surface 206 of thesubstrate 202. Thepassivation film 208 is selectively etched to expose theconductive electrode 204. - The exposed
electrode substrate assembly 200 is immersed in an electroless plating bath containing palladium in solution, whereby through an exchange reaction the exposedconductive electrodes 204 are selectively plated with apalladium layer 210 atop anupper surface 212 of theconductive electrode 204, as shown inFIG. 2 b. As shown inFIG. 2 c, a conductive polymer is applied to anupper surface 214 of thepalladium layer 210 to form aconductive polymer bump 216. Theconductive polymer bump 216 preferably comprises a two-stage epoxy which does not completely set. The conductive polymer used to form theconductive polymer bump 216 preferably has a high electrical conductivity metal, such as palladium, gold, silver, or the like, dispersed therein. Theconductive polymer bump 216 is preferably formed by stencil printing or stenciling the conductive polymer onto theconductive electrode 204. - It is, of course, understood that the
passivation film 208 may be stripped from thesubstrate 202. -
FIGS. 3 a-3 c illustrate a method of forming a conductive polymer bump on a printed circuit board of the present invention.FIG. 3 a illustrates an exposed bondpad chip assembly 300 comprising a printedcircuit board 302 which has at least onebond pad 304, usually copper pads, disposed thereon. Thebond pad 304 has a lead 306 (shown in shadow) within the printedcircuit board 302 attached to alower surface 308 of thebond pad 304. Optionally, apassivation film 310 such as at least one layer of resist polyimide film, or the like, is formed over aface surface 312 of the printedcircuit board 302. Thepassivation film 310 is selectively etched to expose thebond pad 304. - The exposed bond
pad chip assembly 300 is immersed in an electroless plating bath containing palladium in solution, whereby through an exchange reaction the exposedbond pads 304 are selectively plated with apalladium layer 314 atop anupper surface 316 of thebond pad 304, as shown inFIG. 3 b. As shown inFIG. 3 c, a conductive polymer is applied to anupper surface 318 of thepalladium layer 314 to form aconductive polymer bump 320. Theconductive polymer bump 320 preferably comprises a two-stage epoxy which does not completely set. The conductive polymer used to form theconductive polymer bump 320 preferably has a metal, such as palladium, gold, silver, or the like, dispersed therein. Theconductive polymer bump 320 can be formed in a manner discussed for theconductive polymer bump 216 ofFIG. 2 . - It is, of course, understood that the
passivation film 310 may be stripped from the printedcircuit board 302. -
FIG. 4 illustrates asubstrate assembly 400 of the present invention. Thesubstrate assembly 400 comprises afirst substrate 402 with a plurality ofconductive electrodes 404 disposed on a facingsurface 406 of thefirst substrate 402. Apalladium metal layer 408 is disposed on eachconductive electrode 404 by electroless plating. Thesubstrate assembly 400 further comprises asecond substrate 410 with a plurality ofconductive electrodes 412 disposed on a facingsurface 414 of thesecond substrate 410. Apalladium metal layer 416 is also disposed on eachconductive electrode 412. Thefirst substrate 402 and thesecond substrate 410 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 418 extending between the first substratepalladium metal layers 408 and the second substrate palladium metal layers 416. An under-fill encapsulant 420 may be disposed between thefirst substrate 402 and thesecond substrate 410 for environmental protection and to enhance the attachment of thefirst substrate 402 and thesecond substrate 410. -
FIG. 5 illustrates a first embodiment of a substrate/chip assembly 500 of the present invention. The substrate/chip assembly 500 comprises asubstrate 502 with a plurality ofconductive electrodes 504 disposed on a facingsurface 506 of thesubstrate 502. Apalladium metal layer 508 is disposed on eachconductive electrode 504 by electroless plating. The substrate/chip assembly 500 further comprises asemiconductor chip 510 with a plurality ofbond pads 512 disposed on a facingsurface 514 of thesemiconductor chip 510. Apalladium metal layer 516 is also disposed on eachbond pad 512. Thesubstrate 502 and thesemiconductor chip 510 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 518 extending between the substratepalladium metal layers 508 and the semiconductor die palladium metal layers 516. An under-fill encapsulant 520 may be disposed between thesubstrate 502 and the semiconductor die 510 for environmental protection and to enhance the attachment of thesubstrate 502 and thesemiconductor chip 510. -
FIG. 6 illustrates a second embodiment of a substrate/chip assembly 600 of the present invention. The substrate/chip assembly 600 comprises asubstrate 602 with a plurality ofconductive electrodes 604 disposed on a facingsurface 606 of thesubstrate 602. Theconductive electrodes 604 may comprise any suitable type metal electrode, such as aluminum. The substrate/chip assembly 600 further comprises asemiconductor chip 610 with a plurality ofbond pads 612 disposed on a facingsurface 614 of thesemiconductor chip 610. Apalladium metal layer 616 is also disposed on eachbond pad 612. Thesubstrate 602 and thesemiconductor chip 610 are mechanically attached to and in electrical communication with one another via a plurality of conductive polymer bumps 618 extending between the substrateconductive electrodes 604 and the semiconductor die palladium metal layers 616. The conductive material in the conductive polymer bumps 618 is capable of making electrical contact with theconductive electrodes 604 and penetrating any coating thereon whether an oxide coating or a passivation layer coating. An under-fill encapsulant 620 may be disposed between thesubstrate 602 and the semiconductor die 610 for environmental protection and to enhance the attachment of thesubstrate 602 and thesemiconductor chip 610. - It is, of course, understood that, although the assemblies shown in
FIGS. 4, 5 and 6 show substrates and/or semiconductor chips which use the palladium layered structures of the present invention, one of the substrates and/or semiconductor chips could be one of industry standard manufacture. - Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims (43)
1. A method for forming a semiconductor assembly having a plurality of substrates, each substrate having at least one conductive electrode, comprising:
applying a layer of palladium on a portion of the at least one conductive electrode of one substrate of the plurality of substrates; and
disposing a two-stage conductive polymer bump between a portion of the at least one conductive electrode having the layer of palladium thereon of the one substrate of the plurality of substrates and a portion of the at least one conductive electrode of another substrate of the plurality of substrates for forming an electrical contact therebetween.
2. The method of claim 1 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage conductive polymer bump including palladium therein on a portion of the layer of palladium.
3. The method of claim 1 , further comprising:
applying a passivation layer over a portion of a surface of the one substrate of the plurality of substrates having the at least one conductive electrode.
4. The method of claim 3 , further comprising:
etching a portion of the passivation layer to expose a portion of the at least one conductive electrode.
5. The method of claim 1 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage epoxy bump on a portion of layer of palladium.
6. The method of claim 1 , wherein applying the layer of palladium on a portion of the at least one conductive electrode of the one substrate comprises:
immersing the one substrate of the plurality of substrates in an electroless plating solution containing palladium dispersed therein.
7. The method of claim 1 , wherein disposing a two-stage conductive polymer bump comprises applying a layer of a polymer with a silk screen to form the two-stage conductive polymer bump.
8. The method of claim 1 , wherein disposing a two-stage conductive polymer bump comprises applying multiple layers of a polymer with a silk screen to form the two-stage conductive polymer bump.
9. The method of claim 1 , wherein the one substrate of the plurality of substrates comprises a silicon wafer.
10. The method of claim 1 , wherein the one substrate of the plurality of substrates comprises a printed circuit board.
11. The method of claim 1 , wherein the one substrate of the plurality of substrates comprises a semiconductor die having the at least one conductive electrode comprising at least one bond pad.
12. A method for forming a bump on a substrate for a semiconductor assembly having a plurality of substrates, each substrate having at least one conductive electrode, comprising:
applying a layer of palladium on a portion of the at least one conductive electrode of one substrate of the plurality of substrates; and
disposing a two-stage conductive polymer bump between a portion of the at least one conductive electrode having the layer of palladium thereon of the one substrate of the plurality of substrates and a portion of the at least one conductive electrode of another substrate of the plurality of substrates for forming an electrical contact therebetween.
13. The method of claim 12 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage conductive polymer bump including palladium therein on a portion of the layer of palladium.
14. The method of claim 12 , further comprising:
applying a passivation layer over a portion of a surface of the one substrate of the plurality of substrates having the at least one conductive electrode.
15. The method of claim 14 , further comprising:
etching a portion of the passivation layer to expose a portion of the at least one conductive electrode.
16. The method of claim 12 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage epoxy bump on a portion of the layer of palladium.
17. The method of claim 12 , wherein applying the layer of palladium on a portion of the at least one conductive electrode of the one substrate comprises:
immersing the one substrate of the plurality of substrates in an electroless plating solution containing palladium dispersed therein.
18. The method of claim 12 , wherein disposing a two-stage conductive polymer bump comprises applying a layer of a polymer with a silk screen to form the two-stage conductive polymer bump.
19. The method of claim 12 , wherein disposing a two-stage conductive polymer bump comprises applying multiple layers of a polymer with a silk screen to form the two-stage conductive polymer bump.
20. The method of claim 12 , wherein the one substrate of the plurality of substrates comprises a silicon wafer.
21. The method of claim 12 , wherein the one substrate of the plurality of substrates comprises a printed circuit board.
22. The method of claim 12 , wherein the one substrate of the plurality of substrates comprises a semiconductor die having the at least one conductive electrode comprising at least one bond pad.
23. A method for forming a bump on a bond pad of a semiconductor assembly having a plurality of substrates, each substrate having at least one conductive electrode having a bond pad, comprising:
applying a layer of palladium on a portion of the at least one conductive electrode of one substrate of the plurality of substrates; and
disposing a two-stage conductive polymer bump between a portion of the at least one conductive electrode having the layer of palladium thereon of the one substrate of the plurality of substrates and a portion of the at least one conductive electrode of another substrate of the plurality of substrates for forming an electrical contact therebetween.
24. The method of claim 23 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage conductive polymer bump including palladium therein on a portion of the layer of palladium.
25. The method of claim 23 , further comprising:
applying a passivation layer over a portion of a surface of the one substrate of the plurality of substrates having the at least one conductive electrode.
26. The method of claim 25 , further comprising:
etching a portion of the passivation layer to expose a portion of the at least one conductive electrode.
27. The method of claim 23 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage epoxy bump on a portion of the layer of palladium.
28. The method of claim 23 , wherein applying the layer of palladium on a portion of the at least one conductive electrode of the one substrate comprises:
immersing the one substrate of the plurality of substrates in an electroless plating solution containing palladium dispersed therein.
29. The method of claim 23 , wherein disposing a two-stage conductive polymer bump comprises applying a layer of a polymer with a silk screen to form the two-stage conductive polymer bump.
30. The method of claim 23 , wherein disposing a two-stage conductive polymer bump comprises applying multiple layers of a polymer with a silk screen to form the two-stage conductive polymer bump.
31. The method of claim 23 , wherein the one substrate of the plurality of substrates comprises a silicon wafer.
32. The method of claim 23 , wherein the one substrate of the plurality of substrates comprises a printed circuit board.
33. The method of claim 23 , wherein the one substrate of the plurality of substrates comprises a semiconductor die having the at least one conductive electrode comprising at least one bond pad.
34. A method for forming a semiconductor assembly having a plurality of substrates, each substrate having at least one conductive electrode having a pad, comprising:
applying a layer of palladium on a portion of the pad of the at least one conductive electrode of one substrate of the plurality of substrates; and
disposing a two-stage conductive polymer bump between a portion of the pad of the at least one conductive electrode having the layer of palladium thereon of the one substrate of the plurality of substrates and a portion of the pad of the at least one conductive electrode of another substrate of the plurality of substrates for forming an electrical contact therebetween.
35. The method of claim 34 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage conductive polymer bump including palladium therein on a portion of the layer of palladium.
36. The method of claim 34 , further comprising:
applying a passivation layer over a portion of a surface of the one substrate of the plurality of substrates having the pad of the at least one conductive electrode.
37. The method of claim 36 , further comprising:
etching a portion of the passivation layer to expose a portion the pad of the at least one conductive electrode.
38. The method of claim 34 , wherein disposing a two-stage conductive polymer bump comprises disposing a two-stage epoxy bump on a portion of the layer of palladium.
39. The method of claim 34 , wherein applying the layer of palladium on a portion of the pad of the at least one conductive electrode of the one substrate comprises:
immersing the one substrate of the plurality of substrates in an electroless plating solution containing palladium dispersed therein.
40. The method of claim 34 , wherein disposing a two-stage conductive polymer bump comprises applying a layer of a polymer with a silk screen to form the two-stage conductive polymer bump.
41. The method of claim 34 , wherein disposing a two-stage conductive polymer bump comprises applying multiple layers of a polymer with a silk screen to form the two-stage conductive polymer bump.
42. The method of claim 34 , wherein the one substrate of the plurality of substrates comprises a silicon wafer.
43. The method of claim 34 , wherein the one substrate of the plurality of substrates comprises a printed circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/008,654 US20050104210A1 (en) | 1996-05-21 | 2004-12-09 | Use of palladium in IC manufacturing with conductive polymer bump |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/651,816 US5925930A (en) | 1996-05-21 | 1996-05-21 | IC contacts with palladium layer and flexible conductive epoxy bumps |
US09/227,072 US6159769A (en) | 1996-05-21 | 1999-01-05 | Use of palladium in IC manufacturing |
US09/645,947 US6413862B1 (en) | 1996-05-21 | 2000-08-25 | Use of palladium in IC manufacturing |
US10/116,962 US6558979B2 (en) | 1996-05-21 | 2002-04-05 | Use of palladium in IC manufacturing with conductive polymer bump |
US10/430,616 US6939744B2 (en) | 1996-05-21 | 2003-05-05 | Use of palladium in IC manufacturing with conductive polymer bump |
US11/008,654 US20050104210A1 (en) | 1996-05-21 | 2004-12-09 | Use of palladium in IC manufacturing with conductive polymer bump |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/430,616 Division US6939744B2 (en) | 1996-05-21 | 2003-05-05 | Use of palladium in IC manufacturing with conductive polymer bump |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050104210A1 true US20050104210A1 (en) | 2005-05-19 |
Family
ID=26921132
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/116,962 Expired - Lifetime US6558979B2 (en) | 1996-05-21 | 2002-04-05 | Use of palladium in IC manufacturing with conductive polymer bump |
US10/430,616 Expired - Fee Related US6939744B2 (en) | 1996-05-21 | 2003-05-05 | Use of palladium in IC manufacturing with conductive polymer bump |
US11/008,654 Abandoned US20050104210A1 (en) | 1996-05-21 | 2004-12-09 | Use of palladium in IC manufacturing with conductive polymer bump |
US11/145,632 Expired - Fee Related US7335988B2 (en) | 1996-05-21 | 2005-06-06 | Use of palladium in IC manufacturing with conductive polymer bump |
US12/024,712 Expired - Fee Related US7759240B2 (en) | 1996-05-21 | 2008-02-01 | Use of palladium in IC manufacturing with conductive polymer bump |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/116,962 Expired - Lifetime US6558979B2 (en) | 1996-05-21 | 2002-04-05 | Use of palladium in IC manufacturing with conductive polymer bump |
US10/430,616 Expired - Fee Related US6939744B2 (en) | 1996-05-21 | 2003-05-05 | Use of palladium in IC manufacturing with conductive polymer bump |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/145,632 Expired - Fee Related US7335988B2 (en) | 1996-05-21 | 2005-06-06 | Use of palladium in IC manufacturing with conductive polymer bump |
US12/024,712 Expired - Fee Related US7759240B2 (en) | 1996-05-21 | 2008-02-01 | Use of palladium in IC manufacturing with conductive polymer bump |
Country Status (1)
Country | Link |
---|---|
US (5) | US6558979B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070084629A1 (en) * | 2004-08-31 | 2007-04-19 | Bernier William E | Low stress conductive polymer bump |
US20080119038A1 (en) * | 1996-05-21 | 2008-05-22 | Micron Technology, Inc. | Use of palladium in ic manufacturing with conductive polymer bump |
US20080289863A1 (en) * | 2007-05-25 | 2008-11-27 | Princo Corp. | Surface finish structure of multi-layer substrate and manufacturing method thereof |
WO2008151472A1 (en) | 2007-06-15 | 2008-12-18 | Princo Corp. | Multilayer board surface-treated configuration and the producing method thereof |
US10141292B2 (en) | 2016-10-13 | 2018-11-27 | Samsung Display Co., Ltd. | Driving chip bump having irregular surface profile, display panel connected thereto and display device including the same |
US10923365B2 (en) * | 2018-10-28 | 2021-02-16 | Richwave Technology Corp. | Connection structure and method for forming the same |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6924171B2 (en) * | 2001-02-13 | 2005-08-02 | International Business Machines Corporation | Bilayer wafer-level underfill |
JP2002270611A (en) * | 2001-03-14 | 2002-09-20 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
JP2004281530A (en) * | 2003-03-13 | 2004-10-07 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
TWI225694B (en) * | 2003-04-23 | 2004-12-21 | Advanced Semiconductor Eng | Flip chip package |
CN100356559C (en) * | 2003-09-24 | 2007-12-19 | 财团法人工业技术研究院 | Crystal coated packing structure and its mfg method |
US9929080B2 (en) * | 2004-11-15 | 2018-03-27 | Intel Corporation | Forming a stress compensation layer and structures formed thereby |
US20070235872A1 (en) * | 2006-03-28 | 2007-10-11 | Ping-Chang Wu | Semiconductor package structure |
US8049249B1 (en) | 2006-09-14 | 2011-11-01 | Marvell International Ltd. | Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same |
US20080213991A1 (en) * | 2007-03-02 | 2008-09-04 | Airdio Wireless Inc. | Method of forming plugs |
TWI341628B (en) * | 2008-02-12 | 2011-05-01 | Taiwan Tft Lcd Ass | Contact structure and bonding structure |
CN102044513A (en) * | 2009-10-21 | 2011-05-04 | 日月光半导体制造股份有限公司 | Semiconductor component |
US8138019B2 (en) * | 2009-11-03 | 2012-03-20 | Toyota Motor Engineering & Manufactruing North America, Inc. | Integrated (multilayer) circuits and process of producing the same |
US8193610B2 (en) | 2010-08-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP |
JP5644286B2 (en) * | 2010-09-07 | 2014-12-24 | オムロン株式会社 | Electronic component surface mounting method and electronic component mounted substrate |
US8476760B2 (en) * | 2010-11-03 | 2013-07-02 | Texas Instruments Incorporated | Electroplated posts with reduced topography and stress |
FR2978607A1 (en) | 2011-07-28 | 2013-02-01 | Commissariat Energie Atomique | METHOD FOR ASSEMBLING A MICROELECTRONIC CHIP DEVICE IN A FABRIC, A CHIP DEVICE, AND A FABRIC INCORPORATING A CHILLED CHIP DEVICE |
US9030017B2 (en) * | 2012-11-13 | 2015-05-12 | Invensas Corporation | Z-connection using electroless plating |
US9478498B2 (en) * | 2013-08-05 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through package via (TPV) |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4182781A (en) * | 1977-09-21 | 1980-01-08 | Texas Instruments Incorporated | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating |
US4442966A (en) * | 1980-10-15 | 1984-04-17 | U.S. Philips Corporation | Method of simultaneously manufacturing multiple electrical connections between two electrical elements |
US4970571A (en) * | 1987-09-24 | 1990-11-13 | Kabushiki Kaisha Toshiba | Bump and method of manufacturing the same |
US5034345A (en) * | 1989-08-21 | 1991-07-23 | Fuji Electric Co., Ltd. | Method of fabricating a bump electrode for an integrated circuit device |
US5048744A (en) * | 1988-12-23 | 1991-09-17 | International Business Machines Corporation | Palladium enhanced fluxless soldering and bonding of semiconductor device contacts |
US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
US5258577A (en) * | 1991-11-22 | 1993-11-02 | Clements James R | Die mounting with uniaxial conductive adhesive |
US5468995A (en) * | 1994-07-05 | 1995-11-21 | Motorola, Inc. | Semiconductor device having compliant columnar electrical connections |
US5468681A (en) * | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5485038A (en) * | 1993-07-15 | 1996-01-16 | Hughes Aircraft Company | Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers |
US5486721A (en) * | 1993-04-10 | 1996-01-23 | W.C. Heraeus Gmbh | Lead frame for integrated circuits |
US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5492863A (en) * | 1994-10-19 | 1996-02-20 | Motorola, Inc. | Method for forming conductive bumps on a semiconductor device |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US5674780A (en) * | 1995-07-24 | 1997-10-07 | Motorola, Inc. | Method of forming an electrically conductive polymer bump over an aluminum electrode |
US5677566A (en) * | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
US5707902A (en) * | 1995-02-13 | 1998-01-13 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US5739053A (en) * | 1992-10-27 | 1998-04-14 | Matsushita Electric Industrial Co., Ltd. | Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step |
US5808360A (en) * | 1996-05-15 | 1998-09-15 | Micron Technology, Inc. | Microbump interconnect for bore semiconductor dice |
US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
US5940679A (en) * | 1995-01-06 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Method of checking electric circuits of semiconductor device and conductive adhesive for checking usage |
US6072236A (en) * | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
US6249051B1 (en) * | 1994-05-06 | 2001-06-19 | Industrial Technology Research Institute | Composite bump flip chip bonding |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4746942A (en) | 1985-11-23 | 1988-05-24 | Michel Moulin | Photocomposing machine and method |
US4956619A (en) | 1988-02-19 | 1990-09-11 | Texas Instruments Incorporated | Spatial light modulator |
US5497253A (en) | 1988-07-18 | 1996-03-05 | Northrop Grumman Corporation | Multi-layer opto-electronic neural network |
US5083857A (en) | 1990-06-29 | 1992-01-28 | Texas Instruments Incorporated | Multi-level deformable mirror device |
EP0537982A2 (en) | 1991-10-14 | 1993-04-21 | Fujitsu Limited | Semiconductor device having improved leads |
US5384155A (en) | 1992-06-04 | 1995-01-24 | Texas Instruments Incorporated | Silver spot/palladium plate lead frame finish |
JPH06186901A (en) | 1992-12-18 | 1994-07-08 | Komatsu Ltd | Three-dimensional image display device |
US5378888A (en) | 1993-08-16 | 1995-01-03 | Northrop Grumman Corporation | Holographic system for interactive target acquisition and tracking |
US5493437A (en) | 1993-09-13 | 1996-02-20 | Motorola | External communication link for a credit card pager |
US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
JPH086481A (en) | 1994-03-31 | 1996-01-12 | Texas Instr Inc <Ti> | Holographic-image generating method using space optical modulator and holographic image display system |
JPH0845938A (en) | 1994-07-27 | 1996-02-16 | Toshiba Corp | Semiconductor device and its manufacture |
US5757446A (en) | 1994-10-14 | 1998-05-26 | Energy Conversion Devices, Inc. | Liquid crystal display matrix array employing ovonic threshold switching devices to isolate individual pixels |
US6558979B2 (en) | 1996-05-21 | 2003-05-06 | Micron Technology, Inc. | Use of palladium in IC manufacturing with conductive polymer bump |
US5925930A (en) | 1996-05-21 | 1999-07-20 | Micron Technology, Inc. | IC contacts with palladium layer and flexible conductive epoxy bumps |
US6525821B1 (en) | 1997-06-11 | 2003-02-25 | Ut-Battelle, L.L.C. | Acquisition and replay systems for direct-to-digital holography and holovision |
EP0891875B1 (en) | 1997-07-18 | 2003-10-01 | Ricoh Company, Ltd. | Reversible thermosensitive recording medium, method of producing the medium, information recording devices using the medium, and image formation and erasing method using the medium |
US6503690B1 (en) | 1997-08-12 | 2003-01-07 | Matsushita Electric Industrial Co., Ltd. | Optical information recording medium, method for producing the same, and method for recording and reproducing optical information |
US5844709A (en) | 1997-09-30 | 1998-12-01 | The United States Of America As Represented By The Secretary Of The Navy | Multiple quantum well electrically/optically addressed spatial light modulator |
US6271957B1 (en) | 1998-05-29 | 2001-08-07 | Affymetrix, Inc. | Methods involving direct write optical lithography |
US6189208B1 (en) * | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
US6205107B1 (en) | 1998-10-05 | 2001-03-20 | International Business Machines Corporation | Architectures for high-capacity content-addressable holographic databases |
US6486996B1 (en) | 1998-10-27 | 2002-11-26 | Teloptics Corporations | Discrete element light modulating microstructure devices |
US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
US6115123A (en) | 1999-04-12 | 2000-09-05 | Northrop Grumman Corporation | Holographic laser aimpoint selection and maintenance |
US6314014B1 (en) | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
US6646773B2 (en) | 2001-05-23 | 2003-11-11 | Board Of Regents, The University Of Texas System | Digital micro-mirror holographic projection |
US6480438B1 (en) | 2001-06-12 | 2002-11-12 | Ovonyx, Inc. | Providing equal cell programming conditions across a large and high density array of phase-change memory cells |
-
2002
- 2002-04-05 US US10/116,962 patent/US6558979B2/en not_active Expired - Lifetime
-
2003
- 2003-05-05 US US10/430,616 patent/US6939744B2/en not_active Expired - Fee Related
-
2004
- 2004-12-09 US US11/008,654 patent/US20050104210A1/en not_active Abandoned
-
2005
- 2005-06-06 US US11/145,632 patent/US7335988B2/en not_active Expired - Fee Related
-
2008
- 2008-02-01 US US12/024,712 patent/US7759240B2/en not_active Expired - Fee Related
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4182781A (en) * | 1977-09-21 | 1980-01-08 | Texas Instruments Incorporated | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating |
US4442966A (en) * | 1980-10-15 | 1984-04-17 | U.S. Philips Corporation | Method of simultaneously manufacturing multiple electrical connections between two electrical elements |
US4970571A (en) * | 1987-09-24 | 1990-11-13 | Kabushiki Kaisha Toshiba | Bump and method of manufacturing the same |
US5048744A (en) * | 1988-12-23 | 1991-09-17 | International Business Machines Corporation | Palladium enhanced fluxless soldering and bonding of semiconductor device contacts |
US5034345A (en) * | 1989-08-21 | 1991-07-23 | Fuji Electric Co., Ltd. | Method of fabricating a bump electrode for an integrated circuit device |
US5468681A (en) * | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
US5237130A (en) * | 1989-12-18 | 1993-08-17 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
US5258577A (en) * | 1991-11-22 | 1993-11-02 | Clements James R | Die mounting with uniaxial conductive adhesive |
US5739053A (en) * | 1992-10-27 | 1998-04-14 | Matsushita Electric Industrial Co., Ltd. | Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step |
US5486721A (en) * | 1993-04-10 | 1996-01-23 | W.C. Heraeus Gmbh | Lead frame for integrated circuits |
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5485038A (en) * | 1993-07-15 | 1996-01-16 | Hughes Aircraft Company | Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers |
US6504105B1 (en) * | 1993-10-28 | 2003-01-07 | International Business Machines Corporation | Solder ball connections and assembly process |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US6249051B1 (en) * | 1994-05-06 | 2001-06-19 | Industrial Technology Research Institute | Composite bump flip chip bonding |
US5468995A (en) * | 1994-07-05 | 1995-11-21 | Motorola, Inc. | Semiconductor device having compliant columnar electrical connections |
US5492863A (en) * | 1994-10-19 | 1996-02-20 | Motorola, Inc. | Method for forming conductive bumps on a semiconductor device |
US5940679A (en) * | 1995-01-06 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Method of checking electric circuits of semiconductor device and conductive adhesive for checking usage |
US5707902A (en) * | 1995-02-13 | 1998-01-13 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5677566A (en) * | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
US5674780A (en) * | 1995-07-24 | 1997-10-07 | Motorola, Inc. | Method of forming an electrically conductive polymer bump over an aluminum electrode |
US6072236A (en) * | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
US5808360A (en) * | 1996-05-15 | 1998-09-15 | Micron Technology, Inc. | Microbump interconnect for bore semiconductor dice |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080119038A1 (en) * | 1996-05-21 | 2008-05-22 | Micron Technology, Inc. | Use of palladium in ic manufacturing with conductive polymer bump |
US7759240B2 (en) * | 1996-05-21 | 2010-07-20 | Micron Technology, Inc. | Use of palladium in IC manufacturing with conductive polymer bump |
US20070084629A1 (en) * | 2004-08-31 | 2007-04-19 | Bernier William E | Low stress conductive polymer bump |
US7442878B2 (en) * | 2004-08-31 | 2008-10-28 | International Business Machines Corporation | Low stress conductive polymer bump |
US20080289863A1 (en) * | 2007-05-25 | 2008-11-27 | Princo Corp. | Surface finish structure of multi-layer substrate and manufacturing method thereof |
US8294039B2 (en) | 2007-05-25 | 2012-10-23 | Princo Middle East Fze | Surface finish structure of multi-layer substrate and manufacturing method thereof |
WO2008151472A1 (en) | 2007-06-15 | 2008-12-18 | Princo Corp. | Multilayer board surface-treated configuration and the producing method thereof |
EP2161976A1 (en) * | 2007-06-15 | 2010-03-10 | Princo Corp. | Multilayer board surface-treated configuration and the producing method thereof |
EP2161976A4 (en) * | 2007-06-15 | 2011-07-13 | Princo Corp | Multilayer board surface-treated configuration and the producing method thereof |
US10141292B2 (en) | 2016-10-13 | 2018-11-27 | Samsung Display Co., Ltd. | Driving chip bump having irregular surface profile, display panel connected thereto and display device including the same |
US10923365B2 (en) * | 2018-10-28 | 2021-02-16 | Richwave Technology Corp. | Connection structure and method for forming the same |
TWI729544B (en) * | 2018-10-28 | 2021-06-01 | 立積電子股份有限公司 | Connection structure and method for forming the same |
Also Published As
Publication number | Publication date |
---|---|
US7335988B2 (en) | 2008-02-26 |
US20030199160A1 (en) | 2003-10-23 |
US20020115279A1 (en) | 2002-08-22 |
US6939744B2 (en) | 2005-09-06 |
US20050218510A1 (en) | 2005-10-06 |
US7759240B2 (en) | 2010-07-20 |
US6558979B2 (en) | 2003-05-06 |
US20080119038A1 (en) | 2008-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6413862B1 (en) | Use of palladium in IC manufacturing | |
US7759240B2 (en) | Use of palladium in IC manufacturing with conductive polymer bump | |
US6780675B2 (en) | Flip-chip technique for chip assembly | |
US6686268B2 (en) | Method of forming overmolded chip scale package and resulting product | |
US7314817B2 (en) | Microelectronic device interconnects | |
US6906417B2 (en) | Ball grid array utilizing solder balls having a core material covered by a metal layer | |
US6689678B2 (en) | Process for fabricating ball grid array package for enhanced stress tolerance | |
US5783465A (en) | Compliant bump technology | |
US6245594B1 (en) | Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly | |
US6103551A (en) | Semiconductor unit and method for manufacturing the same | |
US6844052B2 (en) | Method for underfilling semiconductor components | |
US6707149B2 (en) | Low cost and compliant microelectronic packages for high i/o and fine pitch | |
US5897336A (en) | Direct chip attach for low alpha emission interconnect system | |
US20020030261A1 (en) | Multi-flip-chip semiconductor assembly | |
JPH08255965A (en) | Microchip module assembly | |
US6335271B1 (en) | Method of forming semiconductor device bump electrodes | |
US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
US20020086515A1 (en) | Method of manufacturing bump electrodes and a method of manufacturing a semiconductor device | |
US6960518B1 (en) | Buildup substrate pad pre-solder bump manufacturing | |
US6831361B2 (en) | Flip chip technique for chip assembly | |
KR100310037B1 (en) | Method for fabricating flexible printed circuit boad with a plurality of chip | |
JPH1187561A (en) | Semiconductor device, semiconductor chip mounting member, semiconductor chip and production thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |