TWI727277B - 半導體結構及半導體結構形成方法 - Google Patents
半導體結構及半導體結構形成方法 Download PDFInfo
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- TWI727277B TWI727277B TW108108055A TW108108055A TWI727277B TW I727277 B TWI727277 B TW I727277B TW 108108055 A TW108108055 A TW 108108055A TW 108108055 A TW108108055 A TW 108108055A TW I727277 B TWI727277 B TW I727277B
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- 238000000034 method Methods 0.000 title claims description 112
- 239000004065 semiconductor Substances 0.000 title claims description 67
- 239000000758 substrate Substances 0.000 claims abstract description 224
- 230000008878 coupling Effects 0.000 claims abstract description 6
- 238000010168 coupling process Methods 0.000 claims abstract description 6
- 238000005859 coupling reaction Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 143
- 239000002184 metal Substances 0.000 claims description 143
- 239000000463 material Substances 0.000 claims description 100
- 239000004020 conductor Substances 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 27
- 238000000059 patterning Methods 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 136
- 230000008569 process Effects 0.000 description 84
- 229920002120 photoresistant polymer Polymers 0.000 description 45
- 238000005530 etching Methods 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 18
- 239000011231 conductive filler Substances 0.000 description 13
- 230000001681 protective effect Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
實施例提供一種用於將垂直取向的組件的頂部電極耦合
到基底的高高寬比通孔,其中組件的頂部電極藉由導電橋接件耦合到通孔,且其中組件的底部電極耦合到基底。一些實施例藉由組件晶圓來安裝組件且在將組件安裝到基底的同時將組件分離。一些實施例將各別的組件安裝到基底。
Description
本發明的實施例是有關於一種半導體結構及其形成方法。
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度持續提高,半導體行業經歷快速增長。在很大程度上,此種積體密度的提高來自於最小特徵尺寸(minimum feature size)的重複減小,此使得更多組件能夠整合到給定區域中。隨著近來對更小的電子元件的需求增長,對更小且更具創造性的半導體晶粒封裝技術的需要也在增加。
一種形成半導體結構的方法,所述方法包括以下步驟。將組件基底的底部電極結合到半導體基底的第一金屬接墊。將組件基底圖案化以形成組件元件。在半導體基底上形成間隙填充材料以包封組件元件。鄰近組件元件形成第一通孔開口,第一通孔開口延伸穿過間隙填充材料且暴露出半導體基底的第二金屬接墊。在第一通孔開口中形成第一通孔。將組件元件的頂部電極耦
合到第一通孔的頂部,耦合提供上部電極與第二金屬接墊之間的電連接。
一種形成半導體結構的方法,所述方法包括以下步驟。將第一組件元件及第二組件元件分別結合到半導體基底的第一金屬接墊及第二金屬接墊,第一組件元件相鄰於第二組件元件。設置在橫向上環繞第一組件元件及第二組件元件的間隙填充材料。在第一組件元件與第二組件元件之間蝕刻出通孔開口以暴露出半導體基底的第三金屬接墊。在通孔開口中形成通孔。將第一組件元件的頂部電極藉由通孔耦合到第三金屬接墊。
一種半導體結構,所述半導體結構包括半導體基底、第一組件、間隙填充材料、第一金屬通孔以及導電橋接件。半導體基底具有設置在半導體基底的頂表面處的第一金屬接墊及第二金屬接墊。第一組件具有底部電極及與底部電極相對的頂部電極,頂部電極耦合到第一金屬接墊。間隙填充材料位於半導體基底上且在橫向上包封第一組件。第一金屬通孔鄰近第一組件設置在間隙填充材料內。第一金屬通孔設置在第二金屬接墊正上方且電耦合到第二金屬接墊。導電橋接件將第一組件的頂部電極耦合到第一金屬通孔的頂部部分。
10:組件貼合區域
20:結載
10A:第一組件貼合區域
10B:第二組件貼合區域
50、301、305、361、365、373:組件元件
101、501:基底
105、109、109A、109B、113、133、137:金屬接墊
115:導電特徵
117:硬罩幕
121、129、341、337:光阻
125、340:晶種層
131:導電材料
201:組件基底
201s:組件基底
205:承載基底
209:貼合層
210:蝕刻停止層
219、223、610:接觸件
227:介電層
309、509:保護介電膜
313、513:間隙填充材料
316、516:通孔開口
321:組件元件
325:組件元件
329、529:擴散障壁
331、531:導電填充物
333:通孔
338:開口
339、510:上部電極
345:導電橋接件層
349、354、381、545:導電橋接件
357:發光部分
359、559:鈍化層
369:導電橋接件
370、372、374、376、378、380、382:配置
402、404、406:封裝
410:切割線
505:底部電極
533:通孔
605:連接件
615:打線結合件
A-A:線
h1、h2、h3、h4:高度
L1、L2、L3、L4、L5、L6、L7、L8、L9、L10:層
w1、w2、w3、w4:寬度
包含附圖以便進一步理解本發明,且附圖併入本說明書中並構成本說明書的一部分。附圖說明本發明的實施例,並與描述一起用於解釋本發明的原理。結合附圖閱讀以下詳細說明,會最好地理解本發明的各個方面。應注意,根據本行業中的標準慣
例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1到圖5示出根據一些實施例的形成高高寬比(aspect ratio)通孔的中間過程的各個圖式。
圖6到圖7示出根據一些實施例的組件基底。
圖7a示出根據一些實施例的示例性組件元件。
圖8到圖27、圖27a、圖28a及圖29到圖35示出根據一些實施例的形成高高寬比通孔的中間過程的各個圖式。
圖36示出根據一些實施例的組件。
圖37到圖46示出根據一些實施例的形成高高寬比通孔的中間過程的各個圖式。
圖47到圖50示出根據一些實施例的具有高高寬比通孔的各種封裝。
以下揭露內容提供諸多不同的實施例或實例來實施本發明的不同特徵。下文闡述組件及配置的具體實例以使本發明簡潔。當然,這些只只是實例並不旨在進行限制。舉例來說,在以下說明中,第一特徵形成在第二特徵上或形成在第二特徵上可包括第一特徵與第二特徵形成為直接接觸的實施例,且也可包括額外特徵可形成在第一特徵與第二特徵之間以使第一特徵與第二特徵不可直接接觸的實施例。另外,本發明可在各種實例中重複使用參考編號及/或字母。此重複是出於簡潔及清晰目的,且本質上並不
規定所述的各種實施例及/或佈置之間的關係。
此外,為易於說明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個組件或特徵與另一(其他)組件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括組件在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或其他取向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
本發明實施例在垂直安裝在基底上的組件之間提供高高寬比通孔。垂直安裝的組件具有頂部電極或上部電極以及底部電極。底部電極可安裝到基底且頂部電極藉由高高寬比通孔耦合到基底。通孔將組件的頂部電極耦合到下伏的基底。由於通孔具有高的高寬比(例如,高度對寬度之比介於約2與約10之間,例如約5),因此通孔能夠減小組件之間的間距。本發明實施例可包括積體被動元件(integrated passive device,IPD)或者具有被動元件晶粒的表面安裝元件(surface mount device,SMD)封裝。然而,各種實施例也可應用於其他類型的封裝,例如具有主動元件晶粒的封裝。
圖1到圖35示出根據一些實施例的形成高高寬比通孔的過程的中間步驟及圖式。圖36到圖46示出根據其他實施例的形成高高寬比通孔的過程的中間步驟及圖式。圖1到圖35包括各種
俯視圖,這些俯視圖未在圖36到圖46中重複示出,但這些俯視圖應被理解為相似地代表圖36到圖46所示實施例。
在圖1到圖7中,製備基底以接納安裝到基底的表面的組件基底。在圖7到圖8中,製備將被安裝到基底的組件基底。在圖9到圖14中,將組件基底安裝到基底且在將組件基底安裝到基底的同時從組件基底形成組件。在圖15到圖33中,從所安裝的組件的頂部電極到基底中的接觸接墊形成通孔。在圖34到圖35中,根據一些實施例,將基底單體化以形成封裝元件,例如積體被動元件或表面安裝元件。
現參照圖1,圖1示出基底101,基底101可具有或可不具有形成在基底101中的主動組件或被動組件(未示出)。基底101可為半導體材料(例如,矽、矽鍺或類似材料)且可根據基底101的設計而具有摻雜區。在一些實施例中,基底101可為晶圓或晶圓的一部分。在一些實施例中,基底101可具有形成在基底101中的至少一個元件。基底101的頂部部分具有形成在基底101中的導電特徵115,導電特徵115包括金屬接墊105、金屬接墊109及金屬接墊113。在一些實施例中,導電特徵115中的一個或多個導電特徵115可耦合到基底101中的對應的元件。在一些實施例中,導電特徵115可為重佈線結構(未示出)的一部分或者可直接上覆在重佈線結構(未示出)上,所述重佈線結構(未示出)對基底101的信號線、電源線及接地線進行路由(route)。應理解,基底101可為較大的基底的局部代表形式,在所述較大的基底中,
導電特徵115包括另外的金屬接墊。
圖1示出組件貼合區域10的第一組件貼合區域10A及第二組件貼合區域10B。在圖1所示的橫截面中,第二組件貼合區域10B看起來與第一組件貼合區域10A交疊,然而,如由虛線所示,第二組件貼合區域10B的一部分位於與圖1所表示的圖式不同的平面中(參見圖6)。圖1所示橫截面僅為實例且各個組件貼合區域可基於佈局來不同地定義。例如參見圖30,圖30包括其他(但並非全部的)佈局的可能性。此將在以下進一步詳細地解釋。
繼續參照圖1,在基底101及導電特徵115之上形成硬罩幕117。在一些實施例中,硬罩幕117由包含聚合物(例如,聚苯並惡唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)等)的介電質形成。在其他實施例中,硬罩幕117由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borophosphosilicate glass,BPSG)、氟矽酸鹽玻璃(fluorosilicate glass,FSG);或類似材料。也可使用其他材料。硬罩幕117可藉由例如旋轉塗布(spin coating)、化學氣相沉積(chemical vapor deposition,CVD)、疊層(laminating)、類似製程或其組合等任何可接受的沉積製程來形成。
可在硬罩幕117上上覆光阻121且可使用可接受的微影技術將光阻121圖案化。光阻121可藉由旋轉塗布或類似製程來形成且可被暴露至光以進行圖案化。所述圖案化穿過光阻121形
成開口,所述開口對應於導電特徵115的一個或多個下伏的金屬接墊(例如,金屬接墊105及金屬接墊113)。光阻121中的開口可為與金屬接墊105和/或金屬接墊113大約相同的大小、比金屬接墊105和/或金屬接墊113大、或者比金屬接墊105和/或金屬接墊113小。
在圖2中,光阻121的圖案可藉由合適的蝕刻技術轉移到硬罩幕117以暴露出導電特徵115的對應的金屬接墊105及金屬接墊113,導電特徵115的對應的金屬接墊105及金屬接墊113將被用於將組件貼合到基底101。光阻121可在對硬罩幕117的蝕刻過程中被消耗,且在對硬罩幕117的蝕刻過程之後,可藉由任何合適的技術來移除餘留的光阻121的任何部分,例如藉由使用氧電漿等進行的灰化製程或剝除製程。
現參照圖3,在硬罩幕117以及藉由硬罩幕117暴露出的任何被暴露出的部分(例如,導電特徵115及基底101的一些部分)之上形成晶種層125。在一些實施例中,晶種層125是金屬層,其可為單個層或者可為包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層125包括鈦層及位於所述鈦層之上的銅層。晶種層125可使用例如物理氣相沉積(physical phase deposition,PVD)或類似製程來形成。接著在晶種層125上形成光阻129並將光阻129圖案化。光阻129可藉由旋轉塗布或類似製程來形成且可被暴露至光以進行圖案化。光阻的圖案對應於導電特徵115的一個或多個金屬接墊(例如,金屬接墊105及金屬接墊113)的
圖案,導電特徵115的所述一個或多個金屬接墊將被用於將組件貼合到基底101。所述圖案化穿過光阻形成開口以暴露出導電特徵115之上的晶種層125的一些部分。光阻129中的開口可大於或小於硬罩幕117中的圖案開口或者可為與硬罩幕117中的圖案開口大約相同的大小。
現參照圖4,在光阻129的開口中以及在晶種層125的被暴露出的部分上形成導電材料131,由此在導電特徵115的被暴露出的金屬接墊105及金屬接墊113中的每一者上形成凸塊。導電材料131可藉由鍍覆(例如,電鍍或無電鍍覆)或類似製程來形成。導電材料131可包括金屬,例如銀、焊料合金、銦、銅、鈦、鎢、鋁或類似材料。
在圖5中,移除光阻129以及晶種層125的上面未形成有導電材料131的部分。光阻129可藉由可接受的灰化製程或剝除製程(例如使用氧電漿或類似製程)來移除。一旦光阻129被移除,便例如藉由使用可接受的蝕刻製程(例如藉由濕蝕刻或乾蝕刻)來移除晶種層125的被暴露出的部分。晶種層125的其餘部分及導電材料131會形成金屬接墊133及金屬接墊137。
圖6示出根據一些實施例的俯視圖。線A-A示出在圖1到圖5、圖9到圖10、圖12到圖13、圖15到圖18及圖21到圖25所示圖式中所使用的橫截面。第一組件貼合區域10A及第二組件貼合區域10B由虛線描繪出。金屬接墊109A以虛影(phantom)形式(其為不可見的)示出在第一組件貼合區域10A中且金屬接
墊109B以虛影形式(其為不可見的)示出在第二組件貼合區域10B中。金屬接墊133被示出在第一組件貼合區域10A中且金屬接墊137被示出在第二組件貼合區域10B中。儘管圖中示出其他組件貼合區域,然而應理解,可包括任何數目的貼合區域。另外,圖6所示基底可為基底晶圓的一部分,如上所述。基底101的一些部分或硬罩幕117的一些部分也可為可見的,如圖6所示。
現參照圖7,結構20的組件基底201被示出為藉由貼合層209貼合到承載基底205。在一些實施例中,承載基底205可為由矽或另一種材料(例如GaAs或類似材料)製成的半導體基底。在其他實施例中,承載基底205可為玻璃承載基底、陶瓷承載基底或類似基底。承載基底205可具有介於約50μm與800μm之間(例如約200μm)的厚度。承載基底205可為晶圓,以使得可在承載基底205上同時形成多個封裝。承載基底205可為由多個組件元件形成的晶圓的一部分。貼合層209可由聚合物系材料形成,所述聚合物系材料可與承載基底205一起從組件基底201移除。在一些實施例中,貼合層209是在受熱時會失去其粘合性質的環氧樹脂系熱釋放材料,例如光熱轉換(Light-to-Heat-Conversion,LTHC)釋放塗層。在其他實施例中,貼合層209可為在被暴露至紫外(ultra-violet,UV)光時會失去其粘合性質的紫外膠。貼合層209可被作為液體進行分配並進行固化,或者可為被層疊到承載基底205上的層疊膜(laminate film)。貼合層209的頂表面及底表面可具有高的共面(co-planarity)程度。
組件基底201可在一個或多個層中包括主動元件或被動元件。在一些實施例中,組件基底201可包括先被形成的且藉由貼合層209被貼合到承載基底的一個或多個層。可接著執行另外的處理來生成另外的層、元件和/或其他特徵。在其他實施例中,使用承載基底205作為用於形成組件基底201的平臺,藉由沉積或形成組件基底201的各個層而在承載基底205上形成組件基底201的各個層,所述過程的實例會在以下進行闡述。在這些實施例中,可在承載基底205與組件基底201之間形成蝕刻停止層210而非貼合層209。蝕刻停止層210可包含介電材料(例如,氮化矽、氧化矽、氮氧化矽或類似材料),所述介電材料具有與組件基底201的第一層的材料不同的蝕刻速率。在一些實施例中,蝕刻停止層210是藉由金屬有機化學氣相沉積(Metal-Organic Chemical Vapor Deposition,MOCVD)形成的磊晶生長材料(例如,InGaP、AlAs或InP),所述磊晶生長材料在隨後對移除承載基底205進行的蝕刻具有強的耐化學蝕刻性,以對組件基底201的各個層進行保護。
組件基底201可包括矽基底或GaAs基底(但是,也可使用其他合適的基底),矽基底或GaAs基底可具有形成在矽基底或GaAs基底中的被摻雜部分和/或未被摻雜的部分。組件基底201的層(例如,層L1至層L10)也可包含金屬、介電質、半導體III-V族磊晶層等等。組件基底201的每一個層可介於約30nm與約300nm之間,例如約70nm。組件基底201可為任何數目的合適的層,例如介於2個層與100個層之間,例如60個層。組件基底201的
總厚度可介於約2μm與約30μm之間,例如約10μm。預期還存在以及可使用其他尺寸的組件基底201的多個層。組件基底201的多個層可在組件基底201的結構內形成組件元件。組件元件可包括例如以下元件:二極體、鐳射二極體、發光二極體(light emitting diode,LED)、金屬-絕緣體-金屬二極體、功率放大器或其他半導體元件。候選的組件可視情況包括上述元件的任何組合。
參照圖7a,根據一些實施例,發光二極體元件被示出為對於組件基底201來說可形成的一個具體的組件基底201s的非限制性實例。但是,所屬領域中的技術人員將理解,此僅為發光二極體的實例且可使用另外的層或不同的層來形成發光二極體。另外,儘管提供以下闡述的層中的每一者的示例性厚度,然而應理解,基於需要以及所形成的元件的特性而定,這些層可比以下所規定的厚或薄。還應理解,可視需要提供另外的層(包括堆疊在彼此上的多個相同的層)以形成期望厚度。
組件基底201s的層L1可為發光二極體元件(例如,發光二極體陰極)的歐姆層,例如p型P-摻雜GaN層。層L1可為例如約50nm到約200nm厚。組件基底201s的層L2到層L5可分別包含約300nm的AlGaN,且分別具有介於約10%到90%之間的不同的鋁(Al)組合物。組件基底201s的層L6是多量子阱層(multiple quantum well layer,MQW),且多量子阱層可為約50nm到200nm厚的InGaN層。組件基底201s的層L7到層L10可為分
別介於約50nm到約200nm厚的n型P摻雜GaN層。組件基底201s的層L1到層L10可一同包括發光二極體的主動部分。
可考慮組件基底201的多個層的其他可能,包括用於形成例如以下元件的層:二極體、鐳射二極體、發光二極體、金屬-絕緣體-金屬二極體、功率放大器、表面安裝元件、積體封裝元件或其他半導體元件。
返回參照圖7,組件元件可形成在組件基底201內以使得組件元件中的每一者具有設置在組件基底201的一個表面的第一電極以及設置在組件基底201的相對的表面的第二電極。組件基底201的最外部層可包括介電層以保護組件元件的電極。
圖8示出在組件基底201上形成接觸件219及接觸件223。接觸件219對應於形成在組件基底內的特定的組件的第一接觸件且接觸件223對應於形成在組件基底內的另一特定的組件的第一接觸件。可在以下所述的進一步處理步驟中將各個組件單體化。接觸件219及接觸件223可使用與以上針對金屬接墊133及金屬接墊137(參見圖5)闡述的製程相似的製程藉由以下操作形成。藉由微影圖案化製程暴露出組件基底201的對應的電極、沉積晶種層以及在晶種層上電鍍導電材料。可使用其他合適的製程來形成接觸件219及接觸件223。所屬領域中的技術人員將理解,可藉由類似的方式為其他組件形成其他接觸件。接觸件219及接觸件223的材料可包括金(Au)、鎳(Ni)、鍺(Ge)、鍺金(GeAu)、鋁(Al)、鈦(Ti)、鉑(Pt)、焊料、類似材料或其組合。在一些
實施例中,接觸件219及接觸件223的寬度可介於約3μm與45μm之間,例如約8μm。在一些實施例中,接觸件219及接觸件223的厚度可介於約0.1μm與5μm之間,例如約0.5μm。預期還存在以及可使用其他尺寸的接觸件219及接觸件223。
現參照圖9,將組件基底201的接觸件219結合到基底101的金屬接墊133且將組件基底201的接觸件223結合到基底101的金屬接墊137。將組件基底201的接觸件219與基底101上的金屬接墊133對齊且將組件基底201的接觸件223與基底101上的金屬接墊137對齊。在一些實施例中,在接觸件219與金屬接墊133之間以及在接觸件223與金屬接墊137之間可使用焊料材料。在其他實施例中,接觸件219可直接結合到金屬接墊133且接觸件223可直接結合到金屬接墊137而不使用共熔材料(eutectic material)(例如,焊料)以使接觸件219與金屬接墊133之間的介面和接觸件223與金屬接墊137之間的介面不含有共熔材料。
現參照圖10,將承載基底205移除。在一些實施例中,可藉由對貼合層209進行降解從而釋放承載基底205來移除承載基底205。在其他實施例中,可藉由化學蝕刻製程來移除承載基底205,且可使用蝕刻停止層210來防止損壞下伏的組件元件。在藉由化學蝕刻製程移除承載基底205之後,可藉由進一步蝕刻製程來將蝕刻停止層210移除。在一些實施例中,可藉由其他適當的手段移除承載基底205,例如藉由化學機械製研磨(chemical
mechanical planarization,CMP)或其他合適的手段來移除。
圖11示出圖10所示元件的俯視圖。組件基底201被示出為晶圓,然而組件基底201可為晶圓的一部分。硬罩幕117的一些部分或基底101的一些部分也可為可見的。
現參照圖12,在組件基底201之上形成介電層227並將介電層227圖案化。介電層227可使用與以上針對圖1所示硬罩幕117闡述的材料及製程相似的材料及製程來形成,不再對其進行贅述。介電層227可使用合適的圖案化製程(例如,以上針對圖1闡述的圖案化製程)來進行圖案化。介電層227可具有介於約0.2μm與約5μm之間(例如約2μm)的厚度,但是預期還存在其他厚度。介電層227可用作罩幕來界定組件基底201的將成為貼合到基底101的單體化組件的部分。從介電層227暴露出的組件基底201的部分將在後續處理中被移除。
圖13示出在將組件元件從組件基底201分離的單體化製程之後的被單體化的組件元件301及組件元件305。在一些實施例中,使用乾蝕刻來將介電層227的圖案轉移到組件基底201的每一個層。在一些實施例中,硬罩幕117也可根據介電層227的圖案被完全地或部分地蝕刻。可使用其他合適的蝕刻製程。在對組件基底201進行蝕刻以形成組件元件301及組件元件305之後,可使用清潔製程來移除由蝕刻產生的殘渣。在對組件基底201進行蝕刻之後,可選擇性地移除介電層227。在一些實施例中,組件元件301和/或組件元件305可包括以兩個或更多個組件元件的集
群方式接合的多個組件元件。應理解,儘管圖中示出兩個組件元件,然而在圖中未示出的基底101的其他區域中可形成另外的組件元件。
圖14示出圖13所示元件的俯視圖。組件元件301及組件元件305之上的介電層227是可見的,且描繪出設置在基底101的相應的金屬接墊105及金屬接墊113之上的組件元件301及組件元件305中的每一者的橫向延伸部。硬罩幕117的一些部分或基底101的一些部分也可為可見的。
現參照圖15,形成環繞組件元件301及組件元件305的保護介電膜309。保護介電膜309可包含任何合適的介電材料,例如(舉例來說)Al2O3、AlN、SiN、SiOx、其他合適的介電質或其多層式組合。保護介電膜309可使用任何合適的沉積技術(包括例如化學氣相沉積、電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)、原子層沉積(atomic layer deposition,ALD)等)來形成。保護介電膜309可沉積到介於0.05μm與0.2μm之間(例如約0.1μm)的厚度,但是預期存在其他厚度。
在圖16中,在整個結構之上沉積間隙填充材料313,由此對組件元件301及305進行包封。組件元件301及305可被完全包封、在橫向上(在組件元件301及305的各個側周圍)以及在垂直方向上(在組件元件301及305的頂上)進行包封。間隙填充材料313可包括例如藉由旋轉塗布或其他合適的製程沉積的聚合物(例如聚醯亞胺、聚苯並惡唑(PBO)、苯並環丁烯(BCB)
等等)。在一些實施例中,間隙填充材料313可為另一種絕緣材料(例如SiOx)或另一種合適的材料。間隙填充材料313可藉由任何合適的製程來沉積,例如藉由化學氣相沉積或類似製程來沉積。
現參照圖17,將圖16所示結構平坦化以使間隙填充材料313的頂部齊平。在一些實施例中,間隙填充材料313的一部分可餘留在組件元件301及組件元件305之上,而在其他實施例中,間隙填充材料313的頂部可被平坦化以使得間隙填充材料313的最上表面與組件元件301的最上表面齊平。平坦化可藉由任何合適的手段來執行,例如藉由化學機械研磨或類似手段來執行。
現參照圖18,鄰近組件元件301和/或組件元件305中的一者(舉例來說,在兩個相鄰的組件元件之間,如圖18所示)形成通孔開口316。通孔開口316暴露出對應的金屬接墊109。在一些實施例中,可形成其他通孔開口,包括鄰近通孔開口316形成其他通孔開口。可使用另外的通孔開口進行耦合以從基底101中的對應的金屬接墊形成通孔。通孔開口316可由任何合適的微影圖案化製程製成,所述製程的實例在以上針對圖1進行了闡述。舉例來說,在間隙填充材料313之上沉積光阻(未示出)(所述光阻被圖案化以在光阻中形成對應於將形成的通孔的開口(例如通孔開口316)的開口),且使用乾蝕刻製程來使光阻的開口延伸穿過間隙填充材料313以暴露出基底101(參見圖1)的對應的金屬接墊(例如,金屬接墊109)。在一些實施例中,通孔開口可具有
包含間隙填充材料313的側壁,而在一些實施例中,組件的側壁上的保護介電膜309可在通孔開口蝕刻期間被暴露出並用作通孔開口316的一個或多個側壁。蝕刻製程可為非等向性的以使包括通孔開口316在內的通孔開口的側壁在製程變化內是垂直的。通孔開口316可具有約0.5μm到約10μm(例如,約1μm)的寬度w1或臨界尺寸以及約1μm到約100μm(例如,約10μm)的高度h1,但是預期存在其他尺寸。通孔開口316可具有高度對寬度之比介於約2與10之間(例如,約5)的高的高寬比。
圖19示出根據一些實施例的圖18所示元件的俯視圖。具體來說,圖19示出形成在組件元件301與組件元件305之間的三個通孔開口316。圖19還示出形成在組件元件321與組件元件325之間的兩個通孔開口316。可根據組件元件中的每一者的大小設定及電要求形成任何數目的通孔開口。舉例來說,可能期望對一些組件元件提供另外的電力,使得多個通孔開口316旨在由一些組件元件使用。
圖20示出根據一些實施例的圖18所示元件的俯視圖。具體來說,圖20示出通孔開口316也可為橢圓形的,通孔開口316也可對應於橢圓形的下伏的金屬接墊,例如金屬接墊109(參見圖18)。通孔開口316(以及通孔開口316的對應的下伏的金屬接墊)可被形成為在俯視圖中呈任何合適的形狀(例如,圓形、正方形、矩形、細長的等等)。
現參照圖21,在所述結構之上以及向通孔開口116中沉
積擴散障壁329。擴散障壁329防止隨後形成的通孔的材料被蛭吸(leeching)或擴散到環繞的間隙填充材料313中。擴散障壁329可由Ti、TiN、TaN、其他合適的材料或其多層式組合形成。擴散障壁329可藉由濺鍍或其他合適的沉積技術形成,例如藉由化學氣相沉積、電漿增強化學氣相沉積、原子層沉積或類似技術形成。
在形成擴散障壁之後,在圖22中,根據一些實施例,藉由鍍覆製程來以導電材料填充通孔開口316(參見圖21),由此在通孔開口316中以及在間隙填充材料313及組件元件(包括組件元件301及組件元件305)之上形成導電填充物331。導電填充物331可包含銅或其他合適的金屬材料,例如鎢(W)或鋁(Al)。可使用其他合適的沉積技術。
參照圖23,可使用平坦化製程來使導電填充物331的頂表面及擴散障壁329的頂表面與間隙填充材料313的頂表面齊平。所述平坦化製程還將移除延伸超過通孔開口316(參見圖21)的導電填充物331的一些部分以及擴散障壁329的一些部分。擴散障壁329與導電填充物331一同形成導電的通孔333。導電的通孔333可具有介於約0.5μm與約10μm之間(例如,約1μm)的寬度w2或臨界尺寸以及介於約1μm與約100μm之間(例如,約10μm)的高度h2,但是預期存在其他尺寸。導電的通孔333可具有高度對寬度之比介於約2與10之間(例如,約5)的高的高寬比。可根據通孔333的導電材料而使用任何合適的平坦化製程,包括化學機械研磨或蝕刻製程或其組合。在一些實施例中,所述
平坦化製程可使導電填充物331的頂表面以及擴散障壁329的頂表面與保護介電膜309的頂表面或介電層227的頂表面齊平。在形成通孔333之後,組件元件301的頂部及組件元件305的頂部可比通孔333的頂部更靠近基底101。換句話說,通孔333的頂部可比組件元件301及305從基底101突出得更遠。
參照圖24及圖25,藉由微影圖案化及蝕刻製程暴露出組件元件301的頂部及組件元件305的頂部。在圖24中,使用與以上針對圖1所闡述的材料及製程相似的材料及製程來對光阻337進行沉積及圖案化。光阻337的圖案對應於下伏的組件元件,例如組件元件301及組件元件305。在圖25中,藉由合適的蝕刻製程暴露出組件元件(包括組件元件301及組件元件305)的上部電極339(例如,最上層或最上層的一部分)。間隙填充材料313(如果存在)的一些部分、保護介電膜309的一些部分及介電層227的一些部分可被移除以形成開口338,開口338會暴露出組件元件的上部電極339。
圖26示出根據一些實施例的圖25所示結構的俯視圖。組件元件301的橫向延伸部的輪廓、組件元件305的橫向延伸部的輪廓、組件元件321的橫向延伸部的輪廓及組件元件325的橫向延伸部的輪廓以虛線示出。圖26所示佈局相似於圖19所示佈局,但是所屬領域中的技術人員將理解,預期存在其他佈局,例如圖20所示佈局或圖29到圖32所示佈局或類似佈局。
參照圖27,在所述結構之上形成導電橋接件層345以將
組件元件的上部電極339橋接到通孔333的最上表面。在一些實施例中,可在導電橋接件層345的導電材料之前沉積光阻341並將光阻341圖案化,其中所述圖案中的開口對應於導電橋接件層345的導電橋接件(參見圖28)的期望佈局。導電橋接件層345可由導電材料(例如,銅、鈦、鉑、銀、鋁、金)、其他合適的材料或其多層式組合形成。導電橋接件層345可藉由蒸鍍沉積、濺鍍、化學氣相沉積或其他合適的製程形成。
參照圖28,在形成導電橋接件層345之後,可將光阻341移除(例如藉由剝除或灰化),由此也將導電橋接件層345的未使用的部分移除並形成導電橋接件349及導電橋接件354。在一些實施例中,導電橋接件可被形成為部分地覆蓋組件元件(包括組件元件301及組件元件305)的上部電極339。在一些實施例中,組件元件的上部電極339的一些部分可保持未被導電橋接件(例如,導電橋接件349及導電橋接件354)覆蓋。舉例來說,在其中組件元件301或組件元件305是發光二極體的實施例中,發光部分357可保持從導電橋接件349及導電橋接件354暴露出。導電橋接件349及導電橋接件354可完全地或部分地環繞但不覆蓋發光部分357。舉例來說,以下所論述的圖29示出組件元件301及組件元件305,組件元件301及組件元件305分別有上部電極339的一些部分保持未被對應的導電橋接件349及導電橋接件354覆蓋。在一些實施例中,導電橋接件可跨越多個組件元件。舉例來說,以下所論述的圖30示出組件元件361及組件元件365,組件元件361
與組件元件365藉由共用的導電橋接件369橋接在一起。
現參照圖27a及圖28a,圖27a及圖28a示出根據其他實施例形成導電橋接件。在一些實施例中,導電橋接件349及導電橋接件354可如以上針對圖27所闡述地一樣形成。在其他實施例中,可在開口338(參見圖25)中以及在間隙填充材料313之上形成晶種層340。晶種層340可為單個金屬層或者可為包括由不同材料形成的多個子層的複合金屬層。可使用例如物理氣相沉積或類似製程來形成晶種層340。接著在晶種層340上形成光阻341並將光阻341圖案化。光阻341可藉由旋轉塗布或類似製程來形成且可被暴露至光以進行圖案化。光阻341的圖案對應於將形成的導電橋接件的負性圖案。所述圖案化穿過光阻341形成開口以暴露出晶種層340。
參照圖28a,在圖27a之後,在光阻341的開口中以及在晶種層340的被暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如,電鍍或無電鍍覆或類似製程)來形成。導電材料可包括金屬,例如銅、鈦、鈀、銀、鋁、金或類似金屬。接著,移除光阻341以及晶種層340的上面未形成有導電材料的部分。光阻341可藉由可接受的灰化製程或剝除製程被移除。在移除光阻341之後,例如藉由使用可接受的蝕刻製程(例如藉由濕蝕刻或乾蝕刻)來移除晶種層340的被暴露出的部分。晶種層340的其餘部分與導電材料形成導電橋接件349及導電橋接件354。
圖29到圖32示出根據一些實施例的結構(例如圖28或
圖28a所示結構)的俯視圖。所屬領域中的技術人員將理解,組件元件的所示佈局僅為許多可能的配置的實例且不旨在進行限制。本文所論述的組件元件及通孔的佈局或類似佈局中的任意者可視需要被組合在相同的基底上。
圖29示出根據一些實施例的圖28或圖28a所示結構的俯視圖。組件元件301的上部電極被示出為藉由導電橋接件349耦合到兩個通孔333。相鄰的組件元件305的上部電極被示出為藉由導電橋接件354耦合到兩個通孔333。藉由導電橋接件354耦合的所述兩個通孔333設置在組件元件305與另一個組件元件325之間。組件元件321鄰近組件元件325設置,其中在組件元件321與組件元件325之間設置有兩個通孔333。一個導電橋接件被示出為將組件元件321的上部電極耦合到通孔333中的一個通孔333,且另一個導電橋接件被示出為將組件元件325的上部電極耦合到通孔333中的另一通孔333。預期存在其他配置且以下提供另外的實例。
圖30示出根據一些實施例的圖28或圖28a所示結構的俯視圖。在圖30中,根據特定元件佈局示出另外的組件元件。圖30示出耦合到兩個通孔333的組件元件301的配置370。另一配置372示出耦合到四個通孔333的組件元件373,其中兩個通孔333位於組件元件373的一側處且另外兩個通孔333位於組件元件373的另一側處。可根據例如向組件元件供應的電力的量來對任何數目的通孔333進行耦合。另一配置374示出橋接到單個通孔333
的組件元件321。另一配置376示出至少兩個組件元件361及365以及至少一個其他通孔333,所述至少兩個組件元件(組件元件361及組件元件365)具有藉由導電橋接件369橋接到彼此的上部電極。另一配置378示出第一個組件元件321以及第二個組件元件325,第一個組件元件321橋接到兩個相鄰的通孔中的第一個通孔333,第二個組件元件325橋接到所述兩個相鄰的通孔中的第二個通孔333。配置378相似於第一組件貼合區域10A及第二組件貼合區域10B,如針對圖6所闡述。
圖31示出根據一些實施例的圖28或圖28a所示結構的俯視圖。在一些實施例中,多個組件元件(例如,組件元件301與組件元件305)可保持連續,例如以實現更高的功率或更強韌(robust)的元件。配置380示出具有兩個上部電極的組件元件,所述兩個上部電極分別藉由一個或多個導電橋接件(例如,導電橋接件349及354)耦合到一個或多個通孔333。
圖32示出根據一些實施例的圖28或圖28a所示結構的俯視圖。相似於以上針對圖31所論述,在一些實施例中,多個組件元件(例如,組件元件301、組件元件305、組件元件321及組件元件325)可保持連續,例如以實現更高的功率或更強韌的元件。配置382示出具有四個上部電極339的組件元件,所述四個上部電極339分別藉由一個或多個導電橋接件(例如,導電橋接件349、354及381)耦合到一個或多個通孔333。
參照圖33,在組件元件301及組件元件305之上形成鈍
化層359以提供對間隙填充材料313、導電橋接件349、導電橋接件354以及組件元件301及組件元件305的實體保護及電性保護。在一些實施例中,鈍化層359可使用合適的沉積製程由非有機材料(例如,氧化矽、未被摻雜的矽酸鹽玻璃、氮氧化矽等)形成。也可使用其他合適的鈍化材料。
圖34到圖35示出將基底101單體化成包括一個或多個在垂直方向上對齊的組件元件的封裝。圖34示出位於封裝402與封裝404之間以及封裝404與封裝406之間的切割線410。每一個封裝包括多個在垂直方向上對齊的組件元件(例如,組件元件301與組件元件305),所述多個在垂直方向上對齊的組件元件具有藉由一個或多個通孔333耦合到下伏的基底101的上部電極339。圖35示出分別相似地位於封裝402與封裝404之間以及封裝404與封裝406之間的切割線410。圖35所示封裝中的每一者包括多個在垂直方向上對齊的組件元件(例如,組件元件301與組件元件305),所述多個在垂直方向上對齊的組件元件具有藉由一個或多個通孔333耦合到下伏的基底的上部電極339。圖35所示封裝還示出在封裝的組件元件與側壁之間可定位有通孔333。
基底101的單體化可藉由任何合適的製程來執行。舉例來說,單體化可藉由機械鋸/刀片、鐳射、蝕刻、其組合或類似製程來進行。將基底101單體化成多個封裝可採用多個來回(pass)執行。
圖36到圖46示出根據一些實施例的形成高高寬比通孔
的中間過程的圖式。圖36到圖46中所繪示的製程相似於以上針對圖1到圖35所闡述的製程,只是組件元件(參見圖13)是預先形成的。在圖36到圖46中,將各個組件結合到基底且形成封裝,所述封裝使用高高寬比通孔來將在垂直方向上對齊的組件的頂部電極耦合到下伏的基底晶圓。
參照圖36,圖36示出預先形成的組件元件50。組件元件50可相似於作為將組件基底201結合到基底101以及將組件基底單體化成組件元件的過程的一部分而形成的組件元件(例如,組件元件301及組件元件305(參見圖7到圖13))。組件元件50可具有底部電極505及上部電極510。底部電極505可具有介於約3μm與45μm之間(例如約8μm)的寬度。上部電極510可具有單電極配置或雙電極配置。上部電極510可被取向為處於組件元件50的上表面的周邊,例如在期望使上部電極510對於組件元件50的上部電極而言保持處於視線之外的情形中。在一些實施例中,底部電極505和/或上部電極510可包含金、銅或其他導電接墊。在一些實施例中,底部電極505和/或上部電極510可包括焊料凸塊。
組件元件50也可具有包括一系列任何數目的層的基底501,所述一系列任何數目的層一同提供組件元件50的操作特性。基底501的每一個層可介於約30nm與約300nm之間,例如約70nm。基底501可為任何數目的合適的層,例如介於2個層與100個層之間,例如60個層。基底501的總厚度可介於約2μm與約
30μm之間,例如約10μm。預期還存在以及可使用其他尺寸的基底501的層。基底501的總寬度可介於約6μm與90μm之間,例如約20μm。預期還存在以及可使用基底501的大小的其他尺寸。組件元件50可為例如以下元件:二極體、鐳射二極體、發光二極體、金屬-絕緣體-金屬二極體、功率放大器或其他半導體元件。候選組件可包括上述元件的任何組合。
可與組件元件50的基底501對應的示例性元件可相同於或相似於以上針對圖7a闡述的組件基底201。
參照圖37,在如上所述在圖5之後進行處理時提供基底101,基底101具有形成在基底101中的金屬接墊105、金屬接墊109及金屬接墊113。使用拾取及放置製程或其他合適的組件轉移製程將組件元件50結合到基底101。拾取及放置製程可選擇各別組件元件50並將每一個組件元件50結合到基底101的對應的接觸接墊(例如,金屬接墊133或金屬接墊137)。在一些實施例中,可將每一個組件元件50貼合到位於基底101的接觸接墊之上的拾取及放置裝置的承載、膠帶或傳輸臂,並被結合到所述接觸接墊。在一些實施例中,可使用質傳技術(mass transfer technology)(相似於在製作微型發光二極體元件時使用的技術)來將組件元件50轉移到基底101的對應的接觸接墊。在一些實施例中,所述結合可藉由直接金屬對金屬結合(例如,銅對銅結合或金對金結合)來執行。在其他實施例中,所述結合可藉由焊料接頭來執行。
參照圖38,形成環繞組件元件50的保護介電膜509。保
護介電膜509可使用與以上針對保護介電膜309(圖15)論述的材料及製程相似的材料及製程來形成,不再對其進行贅述。
參照圖39,可在整個結構之上沉積間隙填充材料513。間隙填充材料513可使用與以上針對間隙填充材料313(圖16)論述的材料及製程相似的材料及製程來形成,不再對其進行贅述。
參照圖40,將圖39所示結構平坦化以使間隙填充材料513的頂部齊平。在一些實施例中,可執行所述平坦化以暴露出組件元件50的上部電極510,而在其他實施例中,所述平坦化可使間隙填充材料513的一部分留在上部電極510之上。平坦化可藉由任何合適的手段執行,例如藉由化學機械研磨或類似手段執行。
參照圖41,鄰近組件元件50中的一者形成通孔開口516。在一些實施例中,通孔開口516形成在兩個相鄰的組件元件50之間。通孔開口516暴露出基底101的金屬接墊109。可視佈局及設計的情況來形成另外的通孔開口。通孔開口516可使用與以上針對通孔開口316(圖18)論述的製程及材料相似的製程及材料來形成,不再對其進行贅述。通孔開口516可具有約0.5μm到約10μm(例如,約1μm)的寬度w3或臨界尺寸以及約1μm到約100μm(例如,約10μm)的高度h3,但是預期存在其他尺寸。通孔開口516可具有高度對寬度之比介於約2與10之間(例如,約5)的高的高寬比。
參照圖42,在所述結構之上以及向通孔開口516中形成擴散障壁529。擴散障壁529防止隨後形成的通孔的材料被蛭吸或擴散到環繞的間隙填充材料中。擴散障壁529可使用與以上針對擴散障壁329(圖21)論述的製程及材料相似的製程及材料來形成,不再對其進行贅述。
參照圖43,根據一些實施例,在形成擴散障壁529之後,藉由鍍覆製程以導電材料填充通孔開口516(參見圖42),由此在通孔開口516中以及在間隙填充材料513及組件元件50之上形成導電填充物531。導電填充物531的材料可包括銅或其他合適的金屬材料,例如鎢或鋁。可使用其他合適的沉積技術。
參照圖44,可使用平坦化製程來使導電填充物531的材料的頂表面齊平並將延伸超過通孔開口516(參見圖42)的導電填充物531的一些部分以及擴散障壁529的一些部分移除。擴散障壁529與導電填充物531一同形成導電的通孔533。導電的通孔533可具有介於約0.5μm與約10μm之間(例如,約1μm)的寬度w4或臨界尺寸以及介於約1μm與約100μm之間(例如,約10μm)的高度h4,但是預期存在其他尺寸。導電的通孔533可具有高度對寬度之比介於約2與10之間(例如,約5)的高的高寬比。可根據通孔533的導電材料而使用任何合適的平坦化製程,包括化學機械研磨或蝕刻製程或其組合。在一些實施例中,所述平坦化製程可使導電填充物531的頂表面以及擴散障壁529的頂表面與保護介電膜509的頂表面齊平。在形成通孔533之後,組
件元件50的頂部可比通孔533的頂部更靠近基底101。換句話說,通孔533的頂部可比組件元件50從基底101突出得更遠。
參照圖45,藉由微影圖案化及蝕刻製程暴露出組件元件50的頂部以及組件元件50的上部電極510,此相似於以上針對圖24及圖25所闡述,不再對其進行贅述。在所述結構之上形成導電橋接件545以將組件元件50的上部電極510橋接到通孔533的最上表面。導電橋接件545可使用與以上針對圖27及圖28所示導電橋接件349及導電橋接件354或者針對圖27a及圖28a所示導電橋接件349及導電橋接件354所論述的製程及材料相似的製程及材料形成,不再對其進行贅述。
在一些實施例中,導電橋接件545可被形成為部分地覆蓋組件元件50的頂表面。舉例來說,在其中組件元件50是發光二極體的實施例中,組件元件50的發光部分可保持從導電橋接件545暴露出。在一些實施例中,導電橋接件545可跨越多個組件元件50。以上所論述的圖29到圖32的俯視圖可相似於這些實施例的俯視圖。
參照圖46,在組件元件50之上形成鈍化層559以提供對導電橋接件545及組件元件50的實體保護及電保護。在一些實施例中,鈍化層559可使用合適的沉積製程由非有機材料(例如,氧化矽、未被摻雜的矽酸鹽玻璃、氮氧化矽等)形成。也可使用其他合適的鈍化材料。
可將基底101單體化成由一個或多個在垂直方向上對齊
的組件元件形成的封裝。單體化可使用與針對圖34及圖35闡述的製程及材料相似的製程及材料來執行,不再對其進行贅述。所得封裝中的每一者可包括多個在垂直方向上對齊的組件元件50,所述多個在垂直方向上對齊的組件元件50具有藉由一個或多個通孔533耦合到下伏的基底的上部電極。
參照圖47及圖48,在一些實施例中,在單體化之前或在單體化之後,圖33(圖47)所示封裝或圖46(圖48)所示封裝可具有連接件605,連接件605形成在基底101的背側表面處以安裝在另一封裝或元件上。基底101的背側表面可被處理成暴露出導電特徵,例如藉由薄化、鐳射穿孔、圖案化或其組合進行處理。連接件605可為焊料球,例如微凸塊、受控塌陷晶粒連接(controlled collapse chip connection,C4)凸塊、球柵陣列(ball grid array,BGA)球等。連接件605可例如使用球安裝技術來形成。在其他實施例中,連接件605可在移除光阻之前形成,所述光阻用於界定形成在被暴露出的導電特徵上的凸塊下金屬(under bump metallurgy,UBM)層(未示出)的圖案。舉例來說,凸塊下金屬可使用與以上針對金屬接墊133(圖4到圖5)所闡述的晶種層、圖案化光阻及鍍覆製程相似的晶種層、圖案化光阻及鍍覆製程來形成。在形成凸塊下金屬之後,可另外執行鍍錫以在凸塊下金屬上形成焊料層。接著如上所述移除光阻以及移除晶種層的上面未形成有導電材料的部分。在移除光阻及晶種層之後,可執行回焊製程以形成焊料球(例如,連接件605)。
參照圖49及圖50,在一些實施例中,在單體化之前或在單體化之後,圖33(圖49)所示封裝或圖46(圖50)所示封裝可具有打線結合接墊,所述打線結合接墊形成在基底101的頂表面處的周邊部分以耦合到另一封裝或板。在基底101中可提前形成接觸件610。單體化製程或蝕刻製程可對間隙填充材料313的側壁或間隙填充材料513的側壁進行修剪以暴露出基底101的周邊部分。可使用蝕刻來暴露出先前形成的接觸件610。在將封裝安裝到另一個封裝或元件之後,打線結合製程可將打線結合件615貼合到另一封裝或元件的對應的導體。
一個實施例是一種形成半導體結構的方法,所述方法包括將組件基底的底部電極結合到半導體基底的第一金屬接墊。將組件基底圖案化以形成組件元件。在半導體基底上形成間隙填充材料以包封組件元件。鄰近組件元件形成第一通孔開口,第一通孔開口延伸穿過間隙填充材料且暴露出半導體基底的第二金屬接墊。在第一通孔開口中形成第一通孔。將組件元件的頂部電極耦合到第一通孔的頂部,耦合提供上部電極與第二金屬接墊之間的電連接。
一些實施例可包括所述形成半導體結構的方法的以下另外的特徵或方面中的一者或多者。所述方法還可包括以下步驟。在將組件基底圖案化以形成組件元件後,在組件元件上形成保護層。所述方法還可包括暴露出組件元件的頂表面以從間隙填充材料暴露出頂部電極。耦合可包括在第一通孔的頂部與上部電極之
間形成導電橋接件。形成導電橋接件可包括以下步驟。將光阻圖案化以覆蓋頂部電極的部分及間隙填充材料的部分。在被圖案化的光阻上以及在頂部電極及第一通孔的頂部上沉積第一導電材料。剝除光阻,剝除使得光阻上的第一導電材料的部分被移除。將組件基底圖案化可包括蝕刻以穿透組件基底的一個或多個層。將組件基底的底部電極結合到半導體基底的第一金屬接墊可包括在半導體基底的第一金屬接墊與組件基底的底部電極之間進行直接金屬對金屬結合。將組件基底的底部電極結合到半導體基底的第一金屬接墊可包括在半導體基底的第一金屬接墊與組件基底的底部電極之間形成焊料接頭。形成第一通孔可包括以下步驟。在第一通孔開口中及在間隙填充材料上沉積障壁層。使用第一導電材料填充第一通孔開口,第一導電材料在橫向上延伸超過第一通孔開口的側壁。將第一導電材料及障壁層平坦化,以使第一通孔的頂部與間隙填充材料的最上表面齊平。所述方法還可包括鄰近第一通孔形成第二通孔。第二通孔的頂部耦合到組件元件的上部電極。這些另外的特徵或方面可組合到上述其他實施例中。
另一個實施例是一種形成半導體結構的方法,所述方法包括以下步驟。將第一組件元件及第二組件元件分別結合到半導體基底的第一金屬接墊及第二金屬接墊,第一組件元件相鄰於第二組件元件。設置在橫向上環繞第一組件元件及第二組件元件的間隙填充材料。在第一組件元件與第二組件元件之間蝕刻出通孔開口以暴露出半導體基底的第三金屬接墊。在通孔開口中形成通
孔。將第一組件元件的頂部電極藉由通孔耦合到第三金屬接墊。
一些實施例可包括所述形成半導體結構的方法的以下另外的特徵或方面中的一者或多者。所述方法還可包括在第一組件元件及第二組件元件上沉積保護層。將第一組件元件結合到半導體基底的第一金屬接墊可包括在半導體基底的第一金屬接墊與第一組件元件的底部電極之間進行直接金屬對金屬結合,其中第一金屬接墊與底部電極的介面不含有焊料材料。形成通孔可包括以下步驟。在通孔開口中及在間隙填充材料上沉積障壁層。使用第一導電材料填充通孔開口,第一導電材料在間隙填充材料上延伸。將第一導電材料及障壁層平坦化以使通孔的頂部與間隙填充材料的最上表面齊平。通孔可為第一通孔,且所述方法還可包括以下步驟。鄰近第一通孔形成第二通孔。將第二組件元件的頂部電極耦合到第二通孔的頂部。這些另外的特徵或方面可組合到上述其他實施例中。
另一個實施例是一種半導體結構,所述半導體結構包括半導體基底、第一組件、間隙填充材料、第一金屬通孔以及導電橋接件。半導體基底具有設置在半導體基底的頂表面處的第一金屬接墊及第二金屬接墊。第一組件具有底部電極及與底部電極相對的頂部電極,頂部電極耦合到第一金屬接墊。間隙填充材料位於半導體基底上且在橫向上包封第一組件。第一金屬通孔鄰近第一組件設置在間隙填充材料內。第一金屬通孔設置在第二金屬接墊正上方且電耦合到第二金屬接墊。導電橋接件將第一組件的頂
部電極耦合到第一金屬通孔的頂部部分。
一些實施例可包括以下另外的特徵或方面中的一者或多者。所述半導體結構可具有第一組件的頂部電極。第一組件的頂部電極比第一金屬通孔的頂部部分更靠近半導體基底。所述半導體結構可具有第一組件的頂表面的第一部分。第一組件的頂表面的第一部分被導電橋接件環繞,第一部分未被導電橋接件覆蓋。所述半導體結構還可包括鄰近第一組件及第一金屬通孔設置在間隙填充材料內的第二金屬通孔,其中導電橋接件還將第一組件的頂部電極耦合到第二金屬通孔的頂部部分。這些另外的特徵或方面可組合到上述其他實施例中。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應理解,其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本發明的精神及範圍,而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
101:基底
105、109、113、133、137:金屬接墊
117:硬罩幕
501:基底
505:底部電極
509:保護介電膜
510:上部電極
513:間隙填充材料
533:通孔
545:導電橋接件
559:鈍化層
610:接觸件
615:打線結合件
Claims (10)
- 一種形成半導體結構的方法,包括:將組件基底的底部電極結合到半導體基底的第一金屬接墊;將所述組件基底圖案化以形成組件元件;在所述半導體基底上形成間隙填充材料以包封所述組件元件;鄰近所述組件元件形成第一通孔開口,所述第一通孔開口延伸穿過所述間隙填充材料且暴露出所述半導體基底的第二金屬接墊;在所述第一通孔開口中形成第一通孔,所述第一通孔的下表面延伸到所述間隙填充材料下方;以及將所述組件元件的頂部電極耦合到所述第一通孔的頂部,所述耦合提供所述頂部電極與所述第二金屬接墊之間的電連接。
- 如申請專利範圍第1項所述的方法,更包括:暴露出所述組件元件的頂表面以從所述間隙填充材料暴露出所述頂部電極。
- 如申請專利範圍第1項所述的方法,其中將所述組件基底的所述底部電極結合到所述半導體基底的所述第一金屬接墊包括在所述半導體基底的所述第一金屬接墊與所述組件基底的所述底部電極之間進行直接金屬對金屬結合。
- 如申請專利範圍第1項所述的方法,其中將所述組件基底的所述底部電極結合到所述半導體基底的所述第一金屬接墊包 括在所述半導體基底的所述第一金屬接墊與所述組件基底的所述底部電極之間形成焊料接頭。
- 如申請專利範圍第1項所述的方法,其中形成所述第一通孔包括:在所述第一通孔開口中及在所述間隙填充材料上沉積障壁層;使用第一導電材料填充所述第一通孔開口,所述第一導電材料在橫向上延伸超過所述第一通孔開口的側壁;以及將所述第一導電材料及所述障壁層平坦化,以使所述第一通孔的所述頂部與所述間隙填充材料的最上表面齊平。
- 一種形成半導體結構的方法,包括:將第一組件元件及第二組件元件分別結合到半導體基底的第一金屬接墊及第二金屬接墊,所述第一組件元件相鄰於所述第二組件元件;設置在橫向上環繞所述第一組件元件及所述第二組件元件的間隙填充材料,所述間隙填充材料完全填充所述第一組件元件及所述第二組件元件之間的間隙;在所述第一組件元件與所述第二組件元件之間蝕刻出通孔開口,以暴露出所述半導體基底的第三金屬接墊;在所述通孔開口中形成通孔;以及將所述第一組件元件的頂部電極藉由所述通孔耦合到所述第三金屬接墊。
- 如申請專利範圍第6項所述的方法,其中將所述第一組件元件結合到所述半導體基底的所述第一金屬接墊包括在所述半導體基底的所述第一金屬接墊與所述第一組件元件的底部電極之間進行直接金屬對金屬結合,其中所述第一金屬接墊與所述底部電極的介面不含有焊料材料。
- 如申請專利範圍第6項所述的方法,其中形成所述通孔包括:在所述通孔開口中及在所述間隙填充材料上沉積障壁層;使用第一導電材料填充所述通孔開口,所述第一導電材料在所述間隙填充材料上延伸;以及將所述第一導電材料及所述障壁層平坦化,以使所述通孔的頂部與所述間隙填充材料的最上表面齊平。
- 一種半導體結構,包括:半導體基底,具有設置在所述半導體基底的頂表面的第一金屬接墊及第二金屬接墊;第一組件,具有底部電極及與所述底部電極相對的頂部電極,所述頂部電極耦合到所述第一金屬接墊;間隙填充材料,位於所述半導體基底上且在橫向上包封所述第一組件;第一金屬通孔,鄰近所述第一組件設置在所述間隙填充材料內,所述第一金屬通孔設置在所述第二金屬接墊正上方且電耦合到所述第二金屬接墊;以及 導電橋接件,將所述第一組件的所述頂部電極耦合到所述第一金屬通孔的頂部部分;其中,所述第一組件的所述頂部電極比所述第一金屬通孔的所述頂部部分更靠近所述半導體基底。
- 如申請專利範圍第9項所述的半導體結構,其中所述第一組件的頂表面的第一部分被所述導電橋接件環繞,所述第一部分未被所述導電橋接件覆蓋。
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