TW202343707A - 封裝結構 - Google Patents
封裝結構 Download PDFInfo
- Publication number
- TW202343707A TW202343707A TW112101837A TW112101837A TW202343707A TW 202343707 A TW202343707 A TW 202343707A TW 112101837 A TW112101837 A TW 112101837A TW 112101837 A TW112101837 A TW 112101837A TW 202343707 A TW202343707 A TW 202343707A
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- Prior art keywords
- semiconductor die
- bonding
- enhancement component
- wafer stack
- disposed
- Prior art date
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Abstract
提供一種包括晶片堆疊結構、熱增強組件及第一絕緣包封體的封裝結構。熱增強組件堆疊在晶片堆疊結構之上並熱耦合到晶片堆疊結構,其中熱增強組件的第一側向尺寸大於晶片堆疊結構的第二側向尺寸。第一絕緣包封體側向地包封熱增強組件及晶片堆疊結構。
Description
半導體元件用於各種電子應用,作為實例,例如個人電腦、手機、數位照相機及其他電子設備。半導體元件通常通過以下步驟製造;在半導體基底之上依序沉積絕緣材料層或介電材料層、導電材料層及半導電材料層,並使用微影將各種材料層圖案化以在其上形成電路組件及元件。通常將數十或數百個積體電路製造在單個半導體晶圓上。通過沿切割道鋸切積體電路來單體化個別的晶粒。個別的晶粒隨後被個別封裝在例如多晶片模塊(multi-chip module)中或其他類型的封裝中。在半導體製造中,半導體封裝的散熱性能受到高度關注。
以下揭露提供用於實施所提供標的的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本發明。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於…之下(beneath)」、「位於…下方(below)」、「下部的(lower)」、「位於…上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的取向之外,所述空間相對性用語還旨在囊括器件在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向),且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
也可包括其他特徵及製程。舉例而言,可包括測試結構,以幫助對三維(three dimensional;3D)封裝或三維積體電路(three dimensional integrated circuit;3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊(test pad),以允許對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用,以提高良率並降低成本。
根據各種示例性實施例提供封裝及其形成方法。示出了形成封裝的中間階段。討論了實施例的變化。在各個視圖及說明性的實施例中,相同的附圖標記用於表示相同的元件。
圖1A至圖1M是示意性示出根據本揭露的一些實施例的用於製造晶片堆疊結構的製程流程的橫截面圖。
參考圖1A,提供包括半導體晶粒的晶圓10。晶圓10中的半導體晶粒可為邏輯晶粒、系統晶片(System on Chip;SoC)晶粒或其他合適的半導體晶粒。舉例而言,晶圓10是通過N5製程製造的。晶圓10可包括半導體基底12(例如,半導體基底)、嵌置在半導體基底12中的基底穿孔14、設置在半導體基底12上的內連線結構16以及設置在內連線結構16上的接合介電層18a,其中基底穿孔14電性連接到內連線結構16。半導體晶圓10的半導體基底12可包括晶體矽晶圓。取決於設計要求(例如,p型基底或n型基底),半導體基底12可包括各種摻雜區域。在一些實施例中,摻雜區域可摻雜有p型摻質或n型摻質。摻雜區域可摻雜諸如硼或BF2的p型摻質、諸如磷或砷的n型摻質及/或其組合。摻雜區域可配置用於n型鰭型場效應晶體管(Fin-type Field Effect Transistors;FinFET)及/或p型FinFET。在一些替代的實施例中,半導體基底12由一些其他合適的元素半導體(諸如金剛石或鍺)、合適的化合物半導體(諸如砷化鎵、碳化矽、砷化銦或磷化銦)或合適的合金半導體(諸如碳化矽鍺、磷化砷化鎵或磷化鎵銦)製成。
可藉由通過例如蝕刻、磨削、雷射技術、其組合等在半導體基底12中形成凹槽來形成基底穿孔14。可通過例如化學氣相沉積(chemical vapor deposition;CVD)、原子層沉積(atomic layer deposition;ALD)、物理氣相沉積(physical vapor deposition;PVD)、熱氧化、其組合等在半導體基底12的前側之上以及在開口中共形地沉積薄阻障層。阻障層可包括氮化物或氮氧化物,例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合等。在薄阻障層之上以及在開口中沉積導電材料。導電材料可通過電化學電鍍製程、CVD、ALD、PVD、其組合等形成。導電材料的實例為銅、鎢、鋁、銀、金、其組合等。可通過例如化學機械拋光從半導體基底12的前側移除多餘的導電材料及阻障層。因此,在一些實施例中,基底穿孔14可包括導電材料及位於導電材料與半導體基底12之間的薄阻障層。
內連線結構16可包括一個或多個介電層(例如,一個或多個層間介電(interlayer dielectric;ILD)層、金屬間介電(intermetal dielectric;IMD)層等)及嵌置在一個或多個介電層中的內連線佈線,且內連線佈線電性連接到形成在半導體基底12中的半導體元件(例如,FinFETs)及/或基底穿孔14。一個或多個介電層的材料可包括氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他合適的介電材料。內連線佈線可包括金屬佈線。舉例而言,內連線佈線包括銅佈線、銅墊、鋁墊或其組合。在一些實施例中,基底穿孔14延伸穿過內連線結構16的一層或多層並延伸進入半導體基底12。
接合介電層18a的材料可為氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他合適的介電材料。接合介電層18a可藉由通過化學氣相沉積(CVD)製程(例如,電漿增強CVD製程或其他合適的製程)沉積介電材料來形成。
參考圖1A及圖1B,通過沿切割道SL1執行的晶圓鋸切製程單體化半導體晶圓10,從而獲得單體化的半導體晶粒20。每一單體化的半導體晶粒20可包括半導體基底12、嵌置在半導體基底12中的基底穿孔14、設置在半導體基底12上的內連線結構16及設置在內連線結構16上的接合介電層18a。如圖1B所示,基底穿孔14埋入半導體基底12及內連線結構16中。在此階段,基底穿孔14並未自半導體基底12的背表面暴露。
參考圖1C,單體化的半導體晶粒20被拾取並以並排方式放置在載體C1上,使得單體化的半導體晶粒20的前表面接合到載體C1。載體C1可為半導體晶圓,例如矽晶圓。載體C1可具有圓形俯視形狀,且可具有矽晶圓的大小。舉例而言,載體C1可具有8英寸直徑、12英寸直徑等。單體化的半導體晶粒20通過晶片到晶圓(chip-to-wafer)接合製程接合到載體C1。執行接合製程以將單體化的半導體晶粒20的接合介電層18a與載體C1接合。接合製程可為直接接合製程。在執行上述直接接合製程之後,可在接合介電層18a與載體C1之間形成半導體到介電(semiconductor-to-dielectric)接合界面,例如矽到氮化矽(Si-SiN
x)接合界面。
參考圖1D,在載體C1之上形成絕緣包封體材料以覆蓋與載體C1接合的單體化的半導體晶粒20。絕緣包封體材料可為通過包覆模製(over-molding)製程形成的模製化合物(例如,環氧樹脂或其他合適的樹脂)。絕緣包封體材料填充相鄰的單體化的半導體晶粒20之間的間隙並覆蓋單體化的半導體晶粒20的背表面。在載體C1之上形成絕緣包封體材料之後,部分地移除半導體晶粒20的絕緣包封體材料及半導體基底12,使得半導體晶粒20的半導體基底12變薄,並形成側向地包封半導體晶粒20的絕緣包封體22。可通過諸如化學機械研磨(Chemical Mechanical Polish;CMP)製程及/或機械研磨製程的平坦化製程部分地移除半導體晶粒20的絕緣包封體材料及半導體基底12。在執行上述的平坦化製程之後,絕緣包封體22的厚度實質上等於半導體晶粒20的厚度。也就是說,絕緣包封體22的頂表面與半導體晶粒20的背表面實質上齊平。如圖1D所示,在執行上述平坦化製程之後,基底穿孔14在此階段自半導體基底12的背表面暴露。基底穿孔14可自半導體基底12的背表面突出。
參考圖1E,可在半導體基底12的背表面及絕緣包封體22的頂表面之上形成介電材料以覆蓋暴露的基底穿孔14。介電材料可為或可包括氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他合適的介電材料。可執行諸如化學機械研磨(CMP)製程及/或機械研磨製程的平坦化製程以部分地移除介電材料,從而在半導體基底12的背表面及絕緣包封體22的頂表面上形成平坦化層24。平坦化層24的頂表面與基底穿孔14的頂端實質上齊平。
在形成平坦化層24之後,在平坦化層24之上形成接合結構26,接合結構26包括接合介電層26a及嵌置在接合介電層26a中的接合導體26b。接合介電層26a的材料可為氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0及y>0)或其他合適的介電材料,且接合導體26b可為導電通孔(例如,銅通孔)、導電墊(例如,銅墊)或其組合。接合結構26可藉由以下製程來形成:通過化學氣相沉積(CVD)製程(例如,電漿增強CVD製程或其他合適的製程)沉積介電材料;圖案化介電材料以形成包括開口或通孔的接合介電層26a;以及在開口中或在被定義在接合介電層26a中的通孔中填充導電材料,以形成嵌置在接合介電層26a中的接合導體26b。在一些實施例中,用於形成接合導體26b的導電材料可通過化學氣相沉積(CVD)製程(例如,電漿增強CVD製程或其他合適的製程)然後是平坦化製程(例如,化學機械研磨(CMP)製程及/或機械研磨製程)來形成。
在形成接合結構26之後,在接合結構26上提供半導體晶粒30。半導體晶粒30可為邏輯晶粒、系統晶片(SoC)晶粒或其他合適的半導體晶粒。舉例而言,半導體晶粒30是通過N3製程製造的。半導體晶粒20及半導體晶粒30可執行相同的功能或不同的功能。舉例而言,半導體晶粒20及半導體晶粒30是系統晶片(SoC)晶粒。半導體晶粒30中的每一個可分別包括半導體基底32及設置在半導體基底32上的內連線結構34。此外,在半導體晶粒30的內連線結構34上可形成接合結構36。接合結構36包括接合介電層36a及嵌置在接合介電層36a中的接合導體36b。接合介電層36a的材料可為氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0及y>0)或其他合適的介電材料,且接合導體36b可為導電通孔(例如,銅通孔)、導電墊(例如,銅墊)或其組合。接合結構36可藉由以下製程來形成:通過化學氣相沉積(CVD)製程(例如,電漿增強CVD製程或其他合適的製程)沉積介電材料;圖案化介電材料以形成包括開口或通孔的接合介電層36a;以及在開口中或在被定義在接合介電層36a中的通孔中填充導電材料,以形成嵌置在接合介電層36a中的接合導體36b。在一些實施例中,用於形成接合導體36b的導電材料可通過化學氣相沉積(CVD)製程(例如,電漿增強CVD製程或其他合適的製程)然後是平坦化製程(例如,化學機械研磨(CMP)製程及/或機械研磨製程)來形成。
執行接合製程(例如,晶片到晶圓接合製程)以接合形成在半導體晶粒30上的接合結構36與接合結構26的接合區域。接合製程可為混合接合製程,混合接合製程包括介電到介電(dielectric-to-dielectric)接合及金屬到金屬(metal-to-metal)接合。在執行上述接合製程之後,接合介電層26a與接合介電層36a之間形成介電到介電接合界面,接合導體26b及接合導體36b之間形成金屬到金屬接合界面。在執行接合製程之後,半導體晶粒30通過接合結構36及接合結構26電性連接到半導體晶粒20。
如圖1E所示,半導體晶粒30可設置在半導體晶粒20上方。半導體晶粒20的側向尺寸(例如,寬度及/或長度)可大於半導體晶粒30的側向尺寸(例如,寬度及/或長度)。換句話說,半導體晶粒20的佔用空間可大於半導體晶粒30的佔用空間。由於接合結構36僅與接合結構26的接合區域接合,因此接合介電層26a的部分不被接合結構36覆蓋。
參考圖1F及圖1G,形成絕緣包封體材料38以覆蓋半導體晶粒30的背表面、半導體晶粒30的側壁以及接合介電層26a的未被接合結構36覆蓋的部分。絕緣包封體材料38可為通過包覆模製製程形成的模製化合物(例如環氧樹脂或其他合適的樹脂)。絕緣包封體材料38填充相鄰的半導體晶粒30之間的間隙。在形成絕緣包封體材料38之後,部分地移除絕緣包封體材料38直到暴露出半導體晶粒30的半導體基底32,從而形成絕緣包封體40。可通過諸如化學機械研磨(CMP)製程及/或機械研磨製程的平坦化製程來部分地移除絕緣包封體材料38。在執行上述平坦化製程之後,絕緣包封體40的頂表面與半導體晶粒30的背表面實質上齊平。
參考圖1H,提供載體C2,載體C2包括形成在其上的剝離層42。在一些實施例中,載體C2為玻璃基板、陶瓷載體等。載體C2可具有圓形俯視形狀,且具有玻璃基板的大小。舉例而言,載體C2可具有8英寸直徑、12英寸直徑等。剝離層42可由聚合物系材料(例如,光熱轉換(Light To Heat Conversion;LTHC)材料)形成,隨後其可與載體C2一起被移除。在一些實施例中,剝離層42由環氧樹脂系熱釋放材料形成。在其他實施例中,剝離層42由紫外線(ultra-violet;UV)膠形成。剝離層42可作為液體被分配並固化。在替代實施例中,剝離層42為層壓膜且被層壓到載體C2上。剝離層42的頂表面實質上是平面的。
執行接合製程(例如,晶圓到晶圓(wafer-to-wafer)接合製程)以將形成在載體C1上的所得結構與由載體C2承載的剝離層42接合。在將形成在載體C1上的所得結構與由載體C2承載的剝離層42接合之後,絕緣包封體40的頂表面及半導體晶粒30的背表面與剝離層42接觸。
參考圖1H及圖1I,在將形成在載體C1上的所得結構與由載體C2承載的剝離層42接合之後,載體C1從接合介電層18a及絕緣包封體22剝離,從而暴露出接合介電層18a及絕緣包封體22。
參考圖1I及圖1J,接合介電層18a被圖案化以形成開口,使得內連線結構16的最頂部內連線佈線自形成在接合介電層18a中的開口暴露。可通過微影製程來形成接合介電層18a中的開口。可形成包括形成在其中的開口的鈍化層44以覆蓋接合介電層18a,使得內連線結構16的最頂部內連線佈線自鈍化層44的開口暴露。可通過微影製程來形成鈍化層44中的開口。被定義在鈍化層44中的開口的寬度可小於被定義在接合介電層18a中的開口的寬度。鈍化層44可覆蓋接合介電層18a的頂表面及絕緣包封體22的頂表面。鈍化層44可進一步延伸到被定義在接合介電層18a中的開口中,使得鈍化層44與內連線結構16的最頂部內連線佈線接觸。
在形成鈍化層44之後,在鈍化層44之上形成導電端子46。導電端子46電性連接到內連線結構16的內連線接線,且導電端子46自鈍化層44突出。導電端子46中的每一個可分別包括導電柱46a及設置在導電柱46a上的焊料頂蓋46b。導電柱46a填充被定義在鈍化層44中的開口並自鈍化層44突出。焊料頂蓋46b覆蓋導電柱46a的頂表面。在形成導電端子46之後,可執行晶片探針檢測(chip probing)製程以提升良率。導電端子46的形成可包括在鈍化層44之上形成晶種層(未示出),在晶種層之上形成諸如光阻層的圖案化罩幕(未示出),然後在暴露的晶種層上進行電鍍製程。隨後移除圖案化的罩幕及晶種層的被圖案化的罩幕覆蓋的部分,留下導電端子46。可進一步執行回流(reflow)製程以重塑(re-shape)焊料頂蓋46b的輪廓。根據一些實施例,晶種層包括鈦層及鈦層之上的銅層。晶種層可使用例如物理氣相沉積(PVD)來形成。可使用諸如化學鍍來進行鍍覆。
參考圖1J及圖1K,在執行晶片探針檢測製程之後,移除焊料頂蓋46b並在鈍化層44之上形成介電層48以覆蓋導電柱46a。在一些實施例中,介電層48由聚合物形成,聚合物可為光敏材料,例如聚苯並噁唑(polybenzoxazole;PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene;BCB)等。在一些其他實施例中,介電層48由諸如氮化矽的氮化物、諸如氧化矽的氧化物、磷矽酸鹽玻璃(PhosphoSilicate Glass;PSG)、硼矽酸鹽玻璃(BoroSilicate Glass;BSG)、硼摻雜的磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass;BPSG)等形成。
參考圖1K及圖1L,執行框架安裝(frame mount)製程,使得由載體C2承載的所得結構安裝在由框架承載的膠帶TP1上。在執行框架安裝製程之後,將介電層48貼合到膠帶TP1上,隨後執行剝離製程,使載體C2從半導體晶粒30及絕緣包封體40剝離。在執行剝離製程之後,暴露出半導體晶粒30的背表面及絕緣包封體40的背表面。在剝離製程期間,剝離層42也從半導體晶粒30及絕緣包封體40清除。可通過在剝離層42上照射諸如UV光或雷射的光以分解剝離層42來執行剝離製程。
參考圖1L及圖1M,提供由另一個框架承載的膠帶TP2,其中貼合膜50形成在膠帶TP2上。由膠帶TP1承載的所得結構被轉移接合到貼合膜50上。然後,沿切割道SL2執行單體化製程,從而得到單體化的晶片堆疊結構100(即,積體電路上系統(system-on-integrated-circuit,SoIC)結構)。在單體化過程中,沿切割道SL2切割介電層48、鈍化層44、絕緣包封體22、平坦化層24、接合結構26、絕緣包封體40及貼合膜50。在一些實施例中,絕緣包封體22側向地包裝半導體晶粒20,其中絕緣包封體40的側壁與絕緣包封體22的側壁對齊。
圖2A至圖2I是示意性示出根據本揭露的一些實施例的用於製造疊PoP結構的製程流程的橫截面圖。
參考圖2A,提供載體60,載體60包括形成在其上的剝離層62。在一些實施例中,載體60為玻璃基板、陶瓷載體等。載體60可具有圓形俯視形狀,且可具有矽晶圓的大小。舉例而言,載體60可具有8英寸直徑、12英寸直徑等。剝離層62可由聚合物系材料(例如,光熱轉換(LTHC)材料)形成,隨後其可與載體60一起從將在後續步驟中形成的上覆結構移除。在一些實施例中,剝離層62由環氧樹脂系熱釋放材料形成。在其他實施例中,剝離層62由紫外線(UV)膠形成。剝離層62可作為液體被分配並固化。在替代實施例中,剝離層62為層壓膜且被層壓到載體60上。剝離層62的頂表面實質上是平面的。
參考圖2A至圖2C,包括介電層64、重分佈佈線66及介電層68的重佈線路結構61形成在剝離層62上,使得剝離層62位於載體60及重佈線路結構61的介電層64之間。如圖2A所示,介電層64形成在剝離層62上。在一些實施例中,介電層64由聚合物形成,該聚合物也可為諸如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)等的光敏材料,可使用微影製程容易地將其圖案化。在一些實施例中,介電層64由諸如氮化矽的氮化物、諸如氧化矽的氧化物、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)等形成。如圖2B所示,在介電層64之上形成重分佈佈線66。重分佈佈線66的形成可包括在介電層64之上形成晶種層(未示出),在晶種層之上形成諸如光阻層的圖案化罩幕(未示出),然後在暴露的晶種層上進行電鍍製程。隨後移除圖案化的罩幕及晶種層的被圖案化的罩幕覆蓋的部分,留下如圖2B所示的重分佈佈線66。根據一些實施例,晶種層包括鈦層及鈦層之上的銅層。晶種層可使用例如物理氣相沉積(PVD)形成。可使用例如化學鍍來進行鍍覆。如圖2C所示,在介電層64之上形成介電層68以覆蓋重分佈佈線66。介電層68的底表面與重分佈佈線66及介電層64的頂表面接觸。根據本揭露的一些實施例,介電層68由聚合物形成,其可為諸如PBO、聚醯亞胺、BCB等的感光材料。在一些實施例中,介電層68由諸如氮化矽之類的氮化物、諸如氧化矽之類的氧化物、PSG、BSG、BPSG等形成。然後圖案化介電層68以在其中形成開口70。因此,通過介電層68中的開口70暴露重分佈佈線66中的部分。出於說明性目的,圖2C及隨後的附圖示出具有單層重分佈佈線66的單個重佈線路結構61,且一些實施例可通過重複上述製程而具有多層重分佈佈線66。
參考圖2D,在由載體60承載的剝離層62之上形成重佈線路結構61之後,在重佈線路結構61上形成金屬柱72,且金屬柱72電性連接到重佈線路結構61的重分佈佈線66。在本文中,由於金屬柱72貫穿隨後形成的模製材料(如圖2G所示),金屬柱72也被替代地稱為導電穿孔(金屬柱72)。在一些實施例中,通過電鍍形成導電穿孔(金屬柱72)。導電穿孔(金屬柱72)的電鍍可包括在介電層68之上形成毯覆晶種層(未示出)並延伸到圖2C所示的開口70中,形成並圖案化光阻(未示出),以及在晶種層的通過光阻中的開口暴露的部分上電鍍導電穿孔(金屬柱72)。隨後移除光阻及晶種層的被光阻覆蓋的部分。導電穿孔(金屬柱72)的材料可包括銅、鋁等。導電穿孔(金屬柱72)可具有棒狀的形狀。導電穿孔(金屬柱72)的俯視形狀可為圓形、矩形、正方形、六邊形等。
參考圖2E,在形成導電穿孔(金屬柱72)之後,提供熱增強組件(thermal enhance component)52(即,散熱件)。在一些實施例中,熱增強組件52包括半導體基底或導電基底,半導體基底或導電基底被拾取並放置在重佈線路結構61的介電層68之上,半導體基底或導電基底通過貼合膜54貼合到重佈線路結構61的介電層68。在一些其他實施例中,熱增強組件52包括導電層(例如,銅層、銅合金層或其他合適的金屬層),導電層通過電鍍製程、分配製程(dispensing process)或其他合適的沉積製程形成在重佈線路結構61的介電層68上,且導電層與重佈線路結構61的介電層68直接接觸。換句話說,圖2E所示的貼合膜54是可選的。
在將熱增強組件52(即,散熱件)貼合到重佈線路結構61的介電層68之後,拾取至少一個單體化的晶片堆疊結構100並將其放置在熱增強組件52之上。出於說明性目的,圖2E僅示出單個晶片堆疊結構100及其周圍的導電穿孔(金屬柱72)。然而,應注意,圖2A至圖2I所示的製程步驟可在晶圓級(wafer level)執行,且可執行在設置在載體60之上的熱增強組件52、多個晶片堆疊結構100及導電穿孔(金屬柱72)上。晶片堆疊結構100及熱增強組件52被導電穿孔(金屬柱72)包圍。如圖2E所示,晶片堆疊結構100中的貼合膜50黏附到熱增強組件52。貼合膜54的側向尺寸大於貼合膜50的側向尺寸或晶片堆疊結構100的側向尺寸。換句話說,貼合膜54的佔用空間大於貼合膜50的佔用空間或晶片堆疊結構100的佔用空間。此外,熱增強組件52的側向尺寸大於貼合膜50的側向尺寸。
在一些實施例中,熱增強組件52的厚度介於約50 nm至約90 nm的範圍內,半導體晶粒30的厚度介於約120 nm至約140 nm的範圍內,貼合膜50的厚度介於約10 nm至約20 nm的範圍內,且貼合膜54的厚度介於約10 nm至約20 nm的範圍內。舉例而言,熱增強組件52的厚度約為55 nm或85 nm,半導體晶粒30的厚度約為130 nm,貼合膜50的厚度約為15 nm,貼合膜54的厚度約為15 nm。
在一些實施例中,熱增強組件52的尺寸為11 mm x 11 mm,半導體晶粒30的晶粒尺寸為6.42 mm x 6.42 mm,熱增強組件52的尺寸與半導體晶粒30的晶粒尺寸的比例約為2.93。在一些其他實施例中,熱增強組件52的尺寸為11 mm x 11 mm,半導體晶粒30的晶粒尺寸為9.2 mm x 9.2 mm,熱增強組件52的尺寸與半導體晶粒30的晶粒尺寸的比例約為1.43。當熱增強組件52的尺寸與半導體晶粒30的晶粒尺寸的比例增加時,熱增強組件52可提供更好的熱增強性能。
參考圖2F,在重佈線路結構61之上形成絕緣包封體材料76以覆蓋熱增強組件52、晶片堆疊結構100及導電穿孔(金屬柱72)。絕緣包封體材料76可為通過包覆模製製程形成的模製化合物(例如環氧樹脂或其他合適的樹脂)。絕緣包封體材料76不僅填充相鄰導電穿孔(金屬柱72)之間的間隙,還填充導電穿孔(金屬柱72)與熱增強組件52之間的間隙以及導電穿孔(金屬柱72)與晶片堆疊結構100之間的間隙。絕緣包封體材料76覆蓋晶片堆疊結構100的介電層48的頂表面。
接下來,如圖2G所示,執行諸如化學機械研磨(CMP)製程及/或機械研磨製程的平坦化製程,以部分地移除晶片堆疊結構100的絕緣包封體材料76及介電層48,直到暴露出導電穿孔(金屬柱72)及晶片堆疊結構100的導電柱46a。在減薄絕緣包封體材料76之後,如圖2G所示,形成絕緣包封體76’以側向地包封熱增強組件52、晶片堆疊結構100及導電穿孔(金屬柱72)。由於經平坦化,在製程變化內,導電穿孔(金屬柱72)貫穿絕緣包封體76’,導電穿孔(金屬柱72)的頂端與介電層48的頂表面實質上齊平或共面,且導電穿孔(金屬柱72)的頂端與絕緣包封體76’的頂表面實質上齊平或共面。在所示的示例性實施例中,執行平坦化直到暴露出晶片堆疊結構100的導電穿孔(金屬柱72)及導電柱46a。
參考圖2H,在晶片堆疊結構100及絕緣包封體76’上形成包括介電層78、重分佈佈線80、介電層82、重分佈佈線86及介電層88的重佈線路結構77。在形成重佈線路結構77之後,在重佈線路結構77上形成包括凸塊下金屬(Under-Bump Metallurgies;UBMs)92的焊料區域及設置在UBMs 92上的電性連接件94。
形成介電層78以覆蓋介電層48、導電柱46a及絕緣包封體76’。在一些實施例中,介電層78由諸如PBO、聚醯亞胺等聚合物形成。在一些其他實施例中,介電層78由氮化矽、氧化矽等形成。可在介電層78中形成開口以暴露導電穿孔(金屬柱72)及導電柱46a。可通過執行微影製程來形成介電層78中的開口。
接下來,形成重分佈佈線80以連接到導電柱46a及導電穿孔(金屬柱72)。重分佈佈線80也可內連導電柱46a與導電穿孔(金屬柱72)。重分佈佈線80可包括介電層78之上的金屬跡線(金屬線)以及延伸到被定義在介電層78中的開口中的金屬通孔以電連接到導電穿孔(金屬柱72)及導電柱46a。在一些實施例中,重分佈佈線80通過電鍍製程形成,其中每一重分佈佈線80包括晶種層(未示出)及在晶種層之上的電鍍金屬材料。晶種層及電鍍材料可由相同的材料或不同的材料形成。重分佈佈線80可包括包括鋁、銅、鎢及其合金的金屬或金屬合金。重分佈佈線80可由非焊料(non-solder)材料形成。重分佈佈線80的通孔部分可與導電穿孔(金屬柱72)的頂表面及導電柱46a物理接觸。
隨後在重分佈佈線80及介電層78之上形成介電層82。介電層82可使用聚合物形成,該聚合物可選自與介電層78相同的候選材料。舉例而言,介電層82可包括PBO、聚醯亞胺、BCB等。在一些實施例中,介電層82可包括諸如氧化矽、氮化矽、碳化矽、氮氧化矽等的無機介電材料。開口也可形成在介電層82中以暴露重分佈佈線80。被定義在介電層82中的開口的形成可通過微影製程來執行。重分佈佈線86的形成可採用與形成重分佈佈線80的類似的方法及材料。
可形成介電層88以覆蓋重分佈佈線86及介電層82,其中介電層88可為聚合物層。介電層88可選自用於形成介電層78及介電層82的相同的候選聚合物。可在介電層88中形成開口以暴露重分佈佈線86的金屬焊盤部分。被定義在介電層88中的開口的形成可通過微影製程來執行。
UBMs 92的形成可包括沉積及圖案化。電性連接件94的形成可包括將焊料放置在UBMs 92的暴露的部分上,然後對焊料進行回流以形成焊球。在一些實施例中,電性連接件94的形成包括執行電鍍步驟以在重分佈佈線86之上形成焊料區域,然後對焊料區域進行回流。在一些其他實施例中,電性連接件94包括金屬柱或金屬柱及焊料頂蓋,其也可通過電鍍形成。在本文中,包括晶片堆疊結構100、導電穿孔(金屬柱72)、絕緣包封體76’、重佈線路結構61、重佈線路結構77、UBMs 92及電性連接件94的組合結構將被稱為晶圓級封裝,其可為具有圓形俯視形狀的複合晶圓。
參考圖2H及圖2I,然後執行剝離製程,以使載體60從晶圓級封裝中剝離。在執行剝離製程之後,暴露出重佈線路結構61的介電層64。在剝離製程期間,剝離層62也從晶圓級封裝清除。可通過在剝離層62上照射諸如UV光或雷射的光以分解剝離層62來執行剝離製程。在剝離製程中,可將膠帶(未示出)黏附到介電層88及電性連接件94上。在隨後的步驟中,從晶圓級封裝中移除載體60及剝離層62。執行單體化製程以將圖2H所示的晶圓級封裝鋸切成圖2I所示的多個單體化的積體扇出封裝P1。
執行圖案化製程以在介電層64中形成開口以暴露重分佈佈線66。被定義在介電層64中的開口的形成可通過微影製程來執行。然後,提供頂部封裝P2,且頂部封裝P2與積體扇出封裝P1(即,底部封裝)接合,從而形成PoP結構。在本揭露的一些實施例中,頂部封裝P2與積體扇出封裝P1之間的接合通過電性連接件(例如,焊接區域)96執行,電性連接件96將重分佈佈線66的金屬焊盤部分連接到頂部封裝P2中的金屬焊盤。可形成底部填充劑98以填充頂部封裝P2與積體扇出封裝P1之間的間隙,使得底部填充劑98側向地包封電性連接件96,且可增強電性連接件96的可靠性。在一些實施例中,頂部封裝P2包括半導體晶粒202,其可為諸如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒等的記憶體晶粒。在一些示例性實施例中,記憶體晶粒也可接合到封裝基底204。
如圖2I所示,積體扇出封裝P1包括晶片堆疊結構100(例如,SoIC結構)、熱增強組件52(例如,散熱件)及絕緣包封體76’。晶片堆疊結構100可包括半導體晶粒20(即,底層半導體晶粒)、絕緣包封體22、半導體晶粒30(即,頂層半導體晶粒)及絕緣包封體40。半導體晶粒30被設置在半導體晶粒20與熱增強組件52之間,且半導體晶粒20被絕緣包封體22側向地包裝。絕緣包封體22及絕緣包封體40分別與絕緣包封體76’接觸。半導體晶粒30堆疊在半導體晶粒20之上,且半導體晶粒30電性連接到半導體晶粒20。絕緣包封體40設置在半導體晶粒20之上並側向地包封半導體晶粒30。熱增強組件52堆疊在晶片堆疊結構100之上並熱耦合到晶片堆疊結構100,且熱增強組件52的側向尺寸D1大於晶片堆疊結構100的側向尺寸D2。舉例而言,熱增強組件52的側向尺寸D1介於約6 mm至約11 mm的範圍內,晶片堆疊結構100的側向尺寸D2介於約6 mm至約9 mm的範圍內,第一側向尺寸D1與第二側向尺寸D2的比例(即,D1/D2)介於約1至約1.83的範圍內。絕緣包封體76’側向地包封晶片堆疊結構100及熱增強組件52。換句話說,熱增強組件52及晶片堆疊結構100被嵌置在絕緣包封體76’中。在一些實施例中,積體扇出封裝P1還可包括被絕緣包封體76’側向地包封導電穿孔(金屬柱72)、重佈線路結構61及重佈線路結構77,其中重佈線路結構61及重佈線路結構77分別設置在絕緣包封體76’的相對兩側。導電穿孔(金屬柱72)與熱增強組件52之間的最小橫向距離D3小於導電穿孔(金屬柱72)與晶片堆疊結構100之間的最小橫向距離D4。舉例而言,最小橫向距離D3大於0.2 m。
圖3是示意性示出根據本揭露的一些其他實施例的PoP結構的橫截面圖。
參考圖2I及圖3,圖3所示的PoP結構與圖2I所示的PoP結構相似,不同之處在於頂部封裝P3的電性連接件96的分布及重佈線路結構61中的重分佈佈線66。如圖3所示,電性連接件96中的至少一個第一電性連接件96a位於熱增強組件52之上,電性連接件96中的多個第二電性連接件96b電性連接到重佈線路結構61,且第二電性連接件96b不位於熱增強組件52上方。在一些實施例中,第二電性連接件96b側向地包圍第一電性連接件96a。
圖4A至圖4L是示意性示出根據本揭露的一些其他實施例的用於製造晶片堆疊結構的製程流程的橫截面圖。
參考圖4A,提供包括半導體晶粒的晶圓10。由於圖4A所示的製程與圖1A所示的相同,因此省略了關於圖4A所示的製程的詳細描述。
參考圖4B,晶圓10被拾起並放置在載體C1上,且晶圓10接合到載體C1。載體C1可為半導體晶圓,例如矽晶圓。載體C1可具有圓形俯視形狀,且可具有矽晶圓的大小。舉例而言,載體C1可具有8英寸直徑、12英寸直徑等。晶圓10通過晶片到晶圓接合製程接合到載體C1。執行接合製程以將晶圓10的接合介電層18a與載體C1接合。接合製程可為直接接合製程。在執行上述直接接合製程之後,可在接合介電層18a與載體C1之間形成半導體到介電接合界面,例如矽到氮化矽(Si-SiN
x)接合界面。
參考圖4C,執行減薄製程以部分移除晶圓10的半導體基底12,直到從半導體基底12的背表面暴露出貫穿半導體的基底穿孔14。減薄製程可為化學機械研磨(CMP)製程及/或機械研磨製程。在執行上述減薄製程之後,基底穿孔14從半導體基底12的背表面突出。
參考圖4D至圖4L,由於圖4D至圖4L所示的用於製造晶片堆疊結構300的製程與圖1E至圖1M所示的相同,因此省略了關於圖4A至圖4L所示的製程的詳細描述。
圖5A至圖5I是示意性示出根據本揭露的一些替代實施例的用於製造PoP結構的製程流程的橫截面圖。
參考圖5A至圖5D,由於圖5A至圖5D所示的製程與圖2A至圖2D所示的相同,因此省略了關於圖5A至圖5D所示的製程的詳細描述。
參考圖5E,在形成導電穿孔(金屬柱72)之後,熱增強組件52(例如,散熱件)及至少一個晶片堆疊結構300被拾取並放置在重佈線路結構61的介電層68之上。出於說明性目的,圖5E中僅示出單個晶片堆疊結構300及其周圍的導電穿孔(金屬柱72)。然而,應注意,圖5A至圖5I所示的製程步驟可在晶圓級執行,且可執行在設置在載體60之上的熱增強組件52、多個晶片堆疊結構300及導電穿孔(金屬柱72)上。如圖5E所示,晶片堆疊結構300中的貼合膜50黏附到熱增強組件52。
參考圖5F至圖5I,由於圖5F至圖5I所示的製程與圖2F至圖2I所示的相同,因此省略了關於圖5F至圖5I所示的製程的詳細描述。
如圖5I所示,積體扇出封裝P4包括晶片堆疊結構300(即,元件晶粒)、熱增強組件52(例如,散熱件)、導電穿孔(金屬柱72)、絕緣包封體76’、重佈線路結構61及重佈線路結構77。絕緣包封體76’側向地包封晶片堆疊結構300、熱增強組件52及導電穿孔(金屬柱72)。重佈線路結構61及重佈線路結構77分別設置是絕緣包封體76’ 的相對兩側。晶片堆疊結構300包括半導體晶粒20(即,底層半導體晶粒)、半導體晶粒30(即,頂層半導體晶粒)及絕緣包封體40。半導體晶粒30堆疊在半導體晶粒20之上,且半導體晶粒30電性連接到半導體晶粒20。此外,絕緣包封體40設置在半導體晶粒20之上並側向地包封半導體晶粒30。
圖6至圖9是示意性示出根據本揭露的一些實施例的各種PoP結構的橫截面圖。
參考圖2I及圖6,圖6所示的PoP結構與圖2I所示的PoP結構相似,不同之處在於積體扇出封裝P1'中的半導體晶粒20與半導體晶粒30通過導電凸塊28a接合,底部填充劑28b側向地包封導電凸塊28a。導電凸塊28a設置在半導體晶粒20與半導體晶粒30之間,且半導體晶粒20通過導電凸塊28a電性連接到半導體晶粒30。
參考圖5I及圖7,圖7所示的PoP結構與圖5I所示的PoP結構相似,不同之處在於積體扇出封裝P4'中的半導體晶粒20與半導體晶粒30通過導電凸塊28a接合,底部填充劑28b側向地包封導電凸塊28a。導電凸塊28a設置在半導體晶粒20與半導體晶粒30之間,且半導體晶粒20通過導電凸塊28a電性連接到半導體晶粒30。
參考圖6及圖8,圖8所示的PoP結構與圖6所示的PoP結構相似,不同之處在於頂部封裝P3的電性連接件96的分布及重佈線路結構61的重分佈佈線66。如圖8所示,電性連接件96中至少一個第一電性連接件96a位於熱增強組件52上方,電性連接件96中多個第二電性連接件96b電性連接到重佈線路結構61,且第二電性連接件96b不位於熱增強組件52上方。在一些實施例中,第二電性連接件96b側向地包圍第一電性連接件96a。
參考圖7及圖9,圖9所示的PoP結構與圖7所示的PoP結構相似,不同之處在於頂部封裝P3的電性連接件96的分布及重佈線路結構61的重分佈佈線66。如圖9所示,電性連接件96中至少一個第一電性連接件96a位於熱增強組件52上方,電性連接件96中多個第二電性連接件96b電性連接到重佈線路結構61,且第二電性連接件96b不位於熱增強組件52上方。在一些實施例中,第二電性連接件96b側向地包圍第一電性連接件96a。
在上述實施例中,熱增強組件(例如,矽基板、銅層、銅合金層或其他合適的熱導電材料)能夠提供熱擴散效應而不會大幅改變製程流程。熱增強組件為晶粒加厚概念提供了一種替代架構,但在保持相同的整體封裝外形尺寸的同時,提供兩倍以上的熱改進效率。此外,在一些實施例中,熱增強組件不僅提供熱增強(例如,熱增強介於約3.7%至約8.3%的範圍內),還提供有效降低面對面(face-to-face)界面處的開裂風險的機械支撐,特別是用於防止SoIC或模製SoIC(molded-SoIC)中的氧化物開裂。
根據本揭露的一些實施例,提供一種包括晶片堆疊結構、熱增強組件及第一絕緣包封體的封裝結構。所述熱增強組件堆疊在所述晶片堆疊結構之上並熱耦合到所述晶片堆疊結構,其中所述熱增強組件的第一側向尺寸大於所述晶片堆疊結構的第二側向尺寸。所述第一絕緣包封體側向地包封所述熱增強組件及所述晶片堆疊結構。在一些實施例中,所述晶片堆疊結構包括第一半導體晶粒、第二半導體晶粒以及第二絕緣包封體,其中所述第二半導體晶粒電性連接到所述第一半導體晶粒,所述第二半導體晶粒設置在所述第一半導體晶粒與所述熱增強組件之間,且所述第二絕緣包封體側向地包封所述第二半導體晶粒。在一些實施例中,所述封裝結構還包括側向地包封所述第一半導體晶粒的第三絕緣包封體,其中所述第三絕緣包封體的側壁與所述第二絕緣包封體的側壁實質上對齊。在一些實施例中,所述晶片堆疊結構還包括設置在所述第一半導體晶粒與所述第二半導體晶粒之間的導電凸塊,且所述第二半導體晶粒通過所述導電凸塊電性連接到所述第一半導體晶粒。在一些實施例中,所述晶片堆疊結構還包括第一接合結構以及第二接合結構,其中所述第一接合結構設置在所述第一半導體晶粒的背表面上;所述第二接合結構設置在所述第二半導體晶粒的前表面上,所述第一接合結構及所述第二接合結構設置在所述第一半導體晶粒與所述第二半導體晶粒之間,且所述第二半導體晶粒通過所述第一接合結構及所述第二接合結構電性連接到所述第一半導體晶粒。在一些實施例中,所述封裝結構還包括重佈線路結構,所述重佈線路結構設置在所述熱增強組件及所述第一絕緣包封體的表面之上,其中所述熱增強組件包括半導體基底或導電基底,所述半導體基底或所述導電基底通過第一貼合膜貼合到所述重佈線路結構,且所述第一貼合膜的頂表面與所述第一絕緣包封體的所述表面實質上齊平。在一些實施例中,所述封裝結構還包括重佈線路結構,所述重佈線路結構設置在所述熱增強組件及所述第一絕緣包封體的表面上,其中所述熱增強組件包括導電層,所述導電層與所述重佈線路結構接觸,所述導電層的頂表面與所述第一絕緣包封體的所述表面實質上齊平。在一些實施例中,所述封裝結構還包括第二貼合膜,所述第二貼合膜設置在所述晶片堆疊結構與所述熱增強組件之間,其中所述晶片堆疊結構通過所述第二貼合膜熱耦合到所述熱增強組件。
根據本揭露的一些其他實施例,提供包括第一封裝及第二封裝的封裝結構。所述第一封裝包括第一絕緣包封體、晶片堆疊結構、散熱件以及重佈線路結構。所述晶片堆疊結構嵌置在所述第一絕緣包封體中,且所述晶片堆疊結構包括被第二絕緣包封體包封的堆疊半導體晶粒。散熱件嵌置在所述第一絕緣包封體中,所述散熱件堆疊在所述堆疊半導體晶粒之上並熱耦合到所述晶片堆疊結構的所述堆疊半導體晶粒,其中所述散熱件的第一側向尺寸大於所述晶片堆疊結構的第二側向尺寸。所述重佈線路結構設置在所述第一絕緣包封體及所述散熱件之上。所述第二封裝設置在所述重佈線路結構之上,其中所述第二封裝包括電性連接到所述重佈線路結構的電性連接件,且所述電性連接件中的至少一個第一電性連接件位於所述散熱件上方。在一些實施例中,所述封裝結構還包括設置在所述散熱件與所述重佈線路結構之間的第一貼合膜,其中所述第一貼合膜的側向尺寸大於所述晶片堆疊結構的側向尺寸。在一些實施例中,所述封裝結構還包括設置在所述散熱件與所述晶片堆疊結構之間的第二貼合膜,其中所述第一貼合膜的所述側向尺寸大於所述第二貼合膜的側向尺寸。在一些實施例中,所述散熱件的側向尺寸大於所述第二貼合膜的所述側向尺寸。在一些實施例中,所述封裝結構還包括導電穿孔,所述導電穿孔貫穿所述第一絕緣包封體,其中所述電性連接件中的第二電性連接件電性連接到所述重佈線路結構,且所述第二電性連接件不位於所述散熱件上方。在一些實施例中,所述至少一個第一電性連接件被所述第二電性連接件包圍。
根據本揭露的一些其他實施例,提供包括晶片堆疊結構、熱增強組件、導電穿孔以及第一絕緣包封體的封裝結構。所述熱增強組件堆疊在所述晶片堆疊結構之上並熱耦合到所述晶片堆疊結構。所述導電穿孔設置為環繞所述晶片堆疊結構及所述熱增強組件。所述第一絕緣包封體側向地包封所述熱增強組件、所述晶片堆疊結構及所述導電穿孔,其中所述導電穿孔與所述熱增強組件之間的第一最小橫向距離小於所述導電穿孔與所述晶片堆疊結構之間的第二最小橫向距離。在一些實施例中,其中所述晶片堆疊結構包括第一半導體晶粒、第二半導體晶粒以及第二絕緣包封體。所述第二半導體晶粒電性連接到所述第一半導體晶粒,其中所述第二半導體晶粒設置在所述第一半導體晶粒與所述熱增強組件之間。所述第二絕緣包封體側向地包封所述第二半導體晶粒。在一些實施例中,所述封裝結構還包括側向地包封所述第一半導體晶粒的第三絕緣包封體,其中所述第三絕緣包封體的側壁與所述第二絕緣包封體的側壁對齊。在一些實施例中,所述晶片堆疊結構還包括設置在所述第一半導體晶粒與所述第二半導體晶粒之間的導電凸塊,且所述第二半導體晶粒通過所述導電凸塊電性連接到所述第一半導體晶粒。在一些實施例中,其中所述晶片堆疊結構還包括第一接合結構以及第二接合結構。所述第一接合結構設置在所述第一半導體晶粒的背表面上。所述第二接合結構設置在所述第二半導體晶粒的前表面上,其中所述第一接合結構及所述第二接合結構設置在所述第一半導體晶粒與所述第二半導體晶粒之間,且所述第二半導體晶粒通過所述第一接合結構及所述第二接合結構電性連接到所述第一半導體晶粒。在一些實施例中,所述封裝結構還包括頂部封裝,所述頂部封裝堆疊在所述熱增強組件及所述導電穿孔之上,其中所述熱增強組件設置在所述晶片堆疊結構與所述頂部封裝之間,所述頂部封裝包括位於所述熱增強組件上方的至少一個第一電性連接件及電性連接到所述重佈線路結構的第二電性連接件,且所述第二電性連接件不位於所述熱增強組件上方。
以上概述了若干實施例的特徵,以使本領域中的技術人員可更好地理解本揭露的各個方面。本領域中的技術人員應理解,其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。本領域中的技術人員還應認識到,這些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下在本文中作出各種改變、代替及變更。
10:晶圓
12、32:半導體基底
14:基底穿孔
16、34:內連線結構
18a、26a、36a:接合介電層
20、30、202:半導體晶粒
22、40、76’:絕緣包封體
24:平坦化層
26、36:接合結構
26b、36b:接合導體
28a:導電凸塊
28b、98:底部填充劑
38、76:絕緣包封體材料
42、62:剝離層
44:鈍化層
46:導電端子
46a:導電柱
46b:焊料頂蓋
48、64、68、78、82、88:介電層
50、54:貼合膜
52:熱增強組件
60、C1、C2:載體
61、77:重佈線路結構
66、80、86:重分佈佈線
70:開口
72:金屬柱
92:凸塊下金屬(UBMs)
94、96:電性連接件
96a:第一電性連接件
96b:第二電性連接件
100、300:晶片堆疊結構
204:封裝基底
D1、D2:側向尺寸
D3、D4:橫向距離
P1、P1’、P4、P4’:積體扇出封裝
P2、P3:頂部封裝
SL1、SL2:切割道
TP、TP1、TP2:膠帶
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,圖式中的各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1A至圖1M是示意性示出根據本揭露的一些實施例的用於製造晶片堆疊結構的製程流程的橫截面圖。
圖2A至圖2I是示意性示出根據本揭露的一些實施例的用於製造疊層封裝(Package-on-Package;PoP)結構的製程流程的橫截面圖。
圖3是示意性示出根據本揭露的一些其他實施例的PoP結構的橫截面圖。
圖4A至圖4L是示意性示出根據本揭露的一些其他實施例的用於製造晶片堆疊結構的製程流程的橫截面圖。
圖5A至圖5I是示意性示出根據本揭露的一些替代實施例的用於製造PoP結構的製程流程的橫截面圖。
圖6至圖9是示意性示出根據本揭露的一些實施例的各種PoP結構的橫截面圖。
18a:接合介電層
22、40、76’:絕緣包封體
24:平坦化層
26、36:接合結構
32:半導體基底
34:內連線結構
30、202:半導體晶粒
44:鈍化層
48、64、68:介電層
50、54:貼合膜
52:熱增強組件
61、77:重佈線路結構
66:重分佈佈線
72:金屬柱
92:凸塊下金屬(UBMs)
94、96:電性連接件
98:底部填充劑
100:晶片堆疊結構
204:封裝基底
P1:積體扇出封裝
P2:頂部封裝
Claims (20)
- 一種封裝結構,包括: 晶片堆疊結構; 熱增強組件,堆疊在所述晶片堆疊結構之上並熱耦合到所述晶片堆疊結構,其中所述熱增強組件的第一側向尺寸大於所述晶片堆疊結構的第二側向尺寸;以及 第一絕緣包封體,側向地包封所述熱增強組件及所述晶片堆疊結構。
- 如請求項1所述的封裝結構,其中所述晶片堆疊結構包括: 第一半導體晶粒; 第二半導體晶粒,電性連接到所述第一半導體晶粒,其中所述第二半導體晶粒設置在所述第一半導體晶粒與所述熱增強組件之間;以及 第二絕緣包封體,側向地包封所述第二半導體晶粒。
- 如請求項2所述的封裝結構,還包括側向地包封所述第一半導體晶粒的第三絕緣包封體,其中所述第三絕緣包封體的側壁與所述第二絕緣包封體的側壁實質上對齊。
- 如請求項2所述的封裝結構,其中所述晶片堆疊結構還包括設置在所述第一半導體晶粒與所述第二半導體晶粒之間的導電凸塊,且所述第二半導體晶粒通過所述導電凸塊電性連接到所述第一半導體晶粒。
- 如請求項2所述的封裝結構,其中所述晶片堆疊結構還包括: 第一接合結構,設置在所述第一半導體晶粒的背表面上;以及 第二接合結構,設置在所述第二半導體晶粒的前表面上,其中所述第一接合結構及所述第二接合結構設置在所述第一半導體晶粒與所述第二半導體晶粒之間,且所述第二半導體晶粒通過所述第一接合結構及所述第二接合結構電性連接到所述第一半導體晶粒。
- 如請求項1所述的封裝結構,還包括: 重佈線路結構,設置在所述熱增強組件及所述第一絕緣包封體的表面之上,其中所述熱增強組件包括半導體基底或導電基底,所述半導體基底或所述導電基底通過第一貼合膜貼合到所述重佈線路結構,且所述第一貼合膜的頂表面與所述第一絕緣包封體的所述表面實質上齊平。
- 如請求項1所述的封裝結構,還包括: 重佈線路結構,設置在所述熱增強組件及所述第一絕緣包封體的表面上,其中所述熱增強組件包括導電層,所述導電層與所述重佈線路結構接觸,所述導電層的頂表面與所述第一絕緣包封體的所述表面實質上齊平。
- 如請求項1所述的封裝結構,還包括: 第二貼合膜,設置在所述晶片堆疊結構與所述熱增強組件之間,其中所述晶片堆疊結構通過所述第二貼合膜熱耦合到所述熱增強組件。
- 一種封裝結構,包括: 第一封裝,包括: 第一絕緣包封體; 晶片堆疊結構,嵌置在所述第一絕緣包封體中,且所述晶片堆疊結構包括被第二絕緣包封體包封的堆疊半導體晶粒; 散熱件,嵌置在所述第一絕緣包封體中,所述散熱件堆疊在所述堆疊半導體晶粒之上並熱耦合到所述晶片堆疊結構的所述堆疊半導體晶粒,其中所述散熱件的第一側向尺寸大於所述晶片堆疊結構的第二側向尺寸;以及 重佈線路結構,設置在所述第一絕緣包封體及所述散熱件之上;以及 第二封裝,設置在所述重佈線路結構之上,其中所述第二封裝包括電性連接到所述重佈線路結構的電性連接件,且所述電性連接件中的至少一個第一電性連接件位於所述散熱件上方。
- 如請求項9所述的封裝結構,還包括設置在所述散熱件與所述重佈線路結構之間的第一貼合膜,其中所述第一貼合膜的側向尺寸大於所述晶片堆疊結構的側向尺寸。
- 如請求項10所述的封裝結構,還包括設置在所述散熱件與所述晶片堆疊結構之間的第二貼合膜,其中所述第一貼合膜的所述側向尺寸大於所述第二貼合膜的側向尺寸。
- 如請求項11所述的封裝結構,其中所述散熱件的側向尺寸大於所述第二貼合膜的所述側向尺寸。
- 如請求項9所述的封裝結構,還包括; 導電穿孔,貫穿所述第一絕緣包封體,其中所述電性連接件中的第二電性連接件電性連接到所述重佈線路結構,且所述第二電性連接件不位於所述散熱件上方。
- 如請求項13所述的封裝結構,其中所述至少一個第一電性連接件被所述第二電性連接件包圍。
- 一種封裝結構,包括: 晶片堆疊結構; 熱增強組件,堆疊在所述晶片堆疊結構之上並熱耦合到所述晶片堆疊結構; 導電穿孔,設置為環繞所述晶片堆疊結構及所述熱增強組件;以及 第一絕緣包封體,側向地包封所述熱增強組件、所述晶片堆疊結構及所述導電穿孔,其中所述導電穿孔與所述熱增強組件之間的第一最小橫向距離小於所述導電穿孔與所述晶片堆疊結構之間的第二最小橫向距離。
- 如請求項15所述的封裝結構,其中所述晶片堆疊結構包括: 第一半導體晶粒; 第二半導體晶粒,電性連接到所述第一半導體晶粒,其中所述第二半導體晶粒設置在所述第一半導體晶粒與所述熱增強組件之間;以及 第二絕緣包封體,側向地包封所述第二半導體晶粒。
- 如請求項16所述的封裝結構,還包括側向地包封所述第一半導體晶粒的第三絕緣包封體,其中所述第三絕緣包封體的側壁與所述第二絕緣包封體的側壁對齊。
- 如請求項16所述的封裝結構,其中所述晶片堆疊結構還包括設置在所述第一半導體晶粒與所述第二半導體晶粒之間的導電凸塊,且所述第二半導體晶粒通過所述導電凸塊電性連接到所述第一半導體晶粒。
- 如請求項16所述的封裝結構,其中所述晶片堆疊結構還包括: 第一接合結構,設置在所述第一半導體晶粒的背表面上;以及 第二接合結構,設置在所述第二半導體晶粒的前表面上,其中所述第一接合結構及所述第二接合結構設置在所述第一半導體晶粒與所述第二半導體晶粒之間,且所述第二半導體晶粒通過所述第一接合結構及所述第二接合結構電性連接到所述第一半導體晶粒。
- 如請求項15所述的封裝結構,還包括: 頂部封裝,堆疊在所述熱增強組件及所述導電穿孔之上,其中所述熱增強組件設置在所述晶片堆疊結構與所述頂部封裝之間,所述頂部封裝包括位於所述熱增強組件上方的至少一個第一電性連接件及電性連接到所述重佈線路結構的第二電性連接件,且所述第二電性連接件不位於所述熱增強組件上方。
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