TWI712087B - 利用犧牲閘極覆蓋間隔壁形成自對準閘極與源/汲接觸以及所得裝置 - Google Patents

利用犧牲閘極覆蓋間隔壁形成自對準閘極與源/汲接觸以及所得裝置 Download PDF

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TWI712087B
TWI712087B TW108124703A TW108124703A TWI712087B TW I712087 B TWI712087 B TW I712087B TW 108124703 A TW108124703 A TW 108124703A TW 108124703 A TW108124703 A TW 108124703A TW I712087 B TWI712087 B TW I712087B
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朱利安 弗羅吉爾
謝瑞龍
朴燦柔
慷果 程
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種方法，包括：形成主動層；在該主動層的通道區上方形成閘極結構；鄰近該閘極結構形成側間隙壁；鄰近該側間隙壁形成第一介電層；凹入該閘極結構以界定閘極空腔；在該閘極空腔中形成內間隙壁；在該閘極空腔中形成覆蓋層；凹入該第一介電層及該側間隙壁，以暴露該覆蓋層的側壁表面；移除該內間隙壁，以界定第一間隙壁空腔；在該間隙壁空腔中並接觸該覆蓋層的側壁表面形成上間隙壁；在該上間隙壁及該覆蓋層上方形成第二介電層；以及形成至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。

Description

利用犧牲閘極覆蓋間隔壁形成自對準閘極與源/汲接觸以及所得裝置
本揭露通常關於半導體裝置的製造，尤其關於用於利用犧牲閘極覆蓋間隙壁(sacrificial gate cap spacer)形成自對準閘極及源/汲接觸(source/drain contacts)的方法以及所得裝置。
通常，由於當前積體電路中的大量半導體裝置(也就是電路元件，例如電晶體、電阻器、電容器等)以及所需的複雜佈局，各半導體裝置例如電晶體、電容器等的電性連接或“線路佈置”無法在製造該些半導體裝置的同一裝置層級內建立。因此，在包括形成於該產品的該裝置層級上方的多個堆疊式“金屬化層”的金屬化系統中形成各種電性連接，其構成該積體電路(IC)產品的總體線路圖案。
為正常工作，對於典型的電晶體，針對該電晶體的導電閘極結構、源區及汲區形成獨立的導電路徑。該製程的部分包括形成通常所謂的裝置層級接觸，也就是，用於建立與該電晶體裝置的源/汲區的電性連接的多個所謂“CA接觸”結構，以及用於建立與該電晶體裝置的閘極結構的電性連接的閘極接觸結 構(有時被稱為“CB接觸”結構)。該CB閘極接觸通常垂直位於圍繞該電晶體裝置的隔離材料上方，也就是，該CB閘極接觸通常不位於主動區上方，但在一些先進架構中它可能位於主動區上方。
該CB閘極接觸通常位於隔離區上方，以避免或減少在該CB閘極接觸與形成於鄰近該電晶體的閘極結構的該電晶體的源/汲區中的導電源/汲結構(例如，溝槽矽化物(trench silicide；TS)結構)之間形成電性短路的概率。通常，也有設計規則規定在該CB閘極接觸與該導電源/汲結構之間必須保持的最小間距，以試圖防止此類電性短路。不幸的是，存在與該CB閘極接觸僅位於隔離區上方的要求相關聯的面積損失。此外，絕緣材料(通常採用至少側間隙壁的形式)位於閘極結構與位於該閘極結構的相對側上的導電源/汲結構之間。該間隙壁通常由具有例如約7-8的較高k值的氮化矽製成。由於電晶體的該物理配置，閘極-接觸(gate-to-contact)電容器被定義，其中，閘極電極充當該電容器的導電板，導電源/汲結構充當該電容器的另一個導電板，且間隙壁位於該兩個導電板之間。此閘極-接觸電容器在本質上是寄生的，因為每當開啟(on)與關閉(off)該電晶體裝置時，此電容器必須充電與放電，所有這些導致延遲該裝置的開關速度。
本揭露提供可避免或至少減少上述問題的其中一個或多個的影響的各種方法及所得裝置。
下面提供本發明的簡要總結，以提供本發明的一些態樣的基本理解。本發明內容並非詳盡概述本發明。其並非意圖識別本發明的關鍵或重要元件或劃定本發明的範圍。其唯一目的在於提供一些簡化形式的概念，作為後面所討論的更詳細說明的前序。
一般來說，本揭露關於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。一種示例裝置包括：除其它以外，主動層，位於該主動層的通道區上方的閘極結構，鄰近該閘極結構的側間隙壁，位於該閘極結構上方的覆蓋層，接觸該覆蓋層的側壁表面以及該閘極結構的上表面的一部分的上間隙壁(upper spacer)，位於該上間隙壁及該覆蓋層上方的第二介電層，以及至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。
一種示例方法包括：除其它以外，形成主動層；在該主動層的通道區上方形成閘極結構；鄰近該閘極結構形成側間隙壁；鄰近該側間隙壁形成第一介電層；凹入該閘極結構以界定閘極空腔(cavity)；在該閘極空腔中形成內間隙壁；以及在鄰近該內間隙壁的該閘極空腔中形成覆蓋層。該方法進一步包括：凹入該第一介電層及該側間隙壁，以暴露該覆蓋層的側壁表面；移除該內間隙壁，以界定鄰近該覆蓋層的第一間隙壁空腔；在該間隙壁空腔中並接觸該覆蓋層的側壁表面形成上間隙壁；在該上間隙壁及該覆蓋層上方形成第二介電層；以及形成至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。
另一種示例方法包括：除其它以外，形成主動層；在該主動層的通道區上方形成閘極結構；鄰近該閘極結構形成側間隙壁；在鄰近該側間隙壁的該主動層中形成源/汲區；鄰近該側間隙壁形成第一介電層；凹入該閘極結構以界定閘極空腔；在該閘極空腔中形成內間隙壁；以及在鄰近該內間隙壁的該閘極空腔中形成覆蓋層。該方法進一步包括：凹入該第一介電層及該側間隙壁，以暴露該覆蓋層的側壁表面；鄰近該側間隙壁並接觸該源/汲區形成源/汲接觸結構；移除該側間隙壁以界定下間隙壁空腔(lower spacer cavity)；在該下間隙壁空腔的至少上部中形成介電材料，以在鄰近該閘極結構的該下間隙壁空腔中界定氣隙；移除該內間隙壁，以界定鄰近該覆蓋層的第一間隙壁空腔；在該間隙壁空腔中並 接觸該覆蓋層的側壁表面形成上間隙壁；在該上間隙壁及該覆蓋層上方形成第二介電層；以及形成至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。
100‧‧‧裝置、半導體裝置或finFET裝置
105‧‧‧基板
110‧‧‧鰭片
115‧‧‧閘極結構
120‧‧‧側間隙壁或第一側間隙壁
125‧‧‧源/汲區
130‧‧‧介電層
135‧‧‧覆蓋空腔
140‧‧‧內間隙壁
140S‧‧‧外側壁表面
145‧‧‧覆蓋層
145S‧‧‧側壁表面
150‧‧‧接觸開口
155‧‧‧下源/汲接觸結構
160‧‧‧間隙壁空腔
165‧‧‧上間隙壁
165S1‧‧‧外表面
165S2‧‧‧內表面
170‧‧‧上源/汲接觸結構
175‧‧‧閘極接觸結構
180‧‧‧介電層
200‧‧‧裝置
205‧‧‧中間源/汲接觸結構
210‧‧‧下間隙壁空腔
215‧‧‧介電材料
220‧‧‧氣隙
CA、CB‧‧‧接觸
參照下面結合附圖所作的說明可理解本揭露，該些附圖中類似的附圖標記表示類似的元件，且其中：
第1A圖至第1J圖顯示本文中所揭露的用於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置；以及
第2A圖至第2E圖顯示本文中所揭露的用於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。
儘管本文中所揭露的發明主題容許各種修改及替代形式，但本發明主題的特定實施例以示例方式顯示於附圖中並在本文中作詳細說明。不過，應當理解，本文中有關特定實施例的說明並非意圖將本發明限於所揭露的特定形式，相反，意圖涵蓋落入由所附申請專利範圍定義的本發明的精神及範圍內的所有修改、等同及替代。
下面說明本發明的各種示例實施例。出於清楚目的，不是實際實施中的全部特徵都在本說明書中進行說明。當然，應當瞭解，在任意此類實際實施例的開發中，必須作大量的特定實施決定以實現開發者的特定目標，例如符合與系統相關及與商業相關的約束條件，該些決定將因不同實施而異。而且，應當瞭解，此類開發努力可能複雜而耗時，但其仍然是本領域的普通技術人員借助本揭露所執行的常規程序。
現在將參照附圖來說明本發明主題。附圖中示意各種結構、系統及裝置僅是出於解釋目的以及避免使本揭露與本領域技術人員已知的細節混淆，但仍包括該些附圖以說明並解釋本揭露的示例。本文中所使用的詞語和詞組的意思應當被理解並解釋為與相關領域技術人員對這些詞語及詞組的理解一致。本文中的術語或詞組的連貫使用並不意圖暗含特別的定義，亦即與本領域技術人員所理解的通常或慣用意思不同的定義。若術語或詞組意圖具有特別意思，亦即不同於本領域技術人員所理解的意思，則此類特別定義會以直接明確地提供該術語或詞組的特別定義的定義方式明確表示於說明書中。
本揭露通常關於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。在完整閱讀本申請以後，本領域的技術人員很容易明白，當前的方法可用於各種裝置，包括但不限於邏輯裝置、記憶體(memory)裝置等。現在通過參照附圖來更詳細地說明本文中所揭露的方法及裝置的各種示例實施例。
第1A圖至第1J圖顯示用於在半導體裝置100中利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法。在該示例實施例中，針對finFET裝置形成該些接觸，不過，該些技術的應用不限於特定類型的裝置，且它們可應用於構建於塊體、SOI或混合基板上的例如平面電晶體、環繞閘極(gate-all-around；GAA)奈米線電晶體、GAA奈米片電晶體等其它結構。第1A圖至第1G圖及第1I圖至第1J圖顯示基板105的剖視圖(沿裝置100的閘極長度方向，也就是，沿當該裝置操作時電流流動的方向)，在該基板105中界定有鰭片110(如虛線所界定)。在鰭片110的通道區上方形成閘極結構115，該閘極結構包括閘極絕緣層(例如，高k材料，如二氧化鉿)以及金屬閘極電極(例如，包含一個或多個層，例如阻擋層、功函數材料層、晶種層、導電填充層等)-未獨立顯示。鄰近閘極結構115形成第一側間隙壁120(例如，SiN、SiOC等)。在鄰近閘極結構115 及側間隙壁120的鰭片110中所界定的溝槽中形成源/汲區125(例如，外延生長半導體材料，例如矽鍺、矽碳、矽、矽磷等，取決於特定的電晶體裝置類型)。鄰近第一側間隙壁120形成介電層130(例如，二氧化矽、低k介電材料、超低k介電材料等)。
本文中所示的finFET裝置100可為NMOS或PMOS電晶體。此外，在基板105、鰭片110或源/汲區125中可形成各種摻雜區，例如環狀注入區、阱區等，但附圖中未顯示這些摻雜區。基板105可具有各種配置，例如所示塊體矽配置。基板105還可具有包括塊體矽層、埋置絕緣層及主動層的絕緣體上矽(silicon-on-insulator；SOI)配置，其中，在該主動層中及上方形成半導體裝置。基板105及/或鰭片110可由矽或矽鍺形成，或者它可由矽以外的材料例如鍺製成。因此，術語“基板”或“半導體基板”應當被理解為涵蓋所有半導體材料以及此類材料的所有形式。基板105可具有不同的層。例如，鰭片110可形成於在基板105的基礎層上方所形成的製程層中。
第1B圖顯示在執行蝕刻製程以凹入閘極結構115從而界定覆蓋空腔135並執行數個製程以在覆蓋空腔135的側壁上形成內間隙壁140(例如，非晶矽)以後的裝置100。執行共形沉積製程以在覆蓋空腔135中及在介電層130上方界定間隙壁層，以及執行非等向性(anisotropic)蝕刻製程以移除該間隙壁層的水平部分，從而界定內間隙壁140。
第1C圖顯示在執行沉積製程以在覆蓋空腔135中形成覆蓋層145(例如，氮化矽)並執行平坦化製程以移除位於覆蓋空腔135外部的覆蓋層145的部分以後的裝置100。
第1D圖顯示在執行一個或多個蝕刻製程以凹入介電層130，從而界定鄰近側間隙壁120的接觸開口150，以暴露源/汲區125以後的裝置100。該一個或多個蝕刻製程還降低側間隙壁120的高度，從而暴露內間隙壁140的 外側壁表面140S。儘管在第1D圖中不可見，但接觸開口150延伸於具有側間隙壁120的相鄰閘極結構115之間。為便於說明，未顯示相鄰的閘極結構115。該一個或多個蝕刻製程可包括：用以選擇性凹入介電層130的等向性(isotropic)蝕刻，接著用以降低側間隙壁120的高度的選擇性非等向性蝕刻；用以降低側間隙壁120的高度的選擇性非等向性蝕刻，接著用以選擇性凹入向源/汲區125提供保護的介電層130的等向性蝕刻；或者經定時以凹入介電層130並降低側間隙壁120的高度的非等向性蝕刻。
第1E圖顯示在接觸開口150中形成下源/汲接觸結構155(例如，溝槽矽化物)以後的裝置100。下源/汲接觸結構155可通過填充接觸開口150並執行蝕刻製程以凹入下源/汲接觸結構155來形成。
第1F圖顯示在執行選擇性蝕刻製程以移除內間隙壁140，從而在側間隙壁120與覆蓋層145之間形成間隙壁空腔160以後的裝置100。
第1G圖顯示執行數個製程以在側間隙壁120上方及間隙壁空腔160中形成上間隙壁165(例如，SiOC或者相對後續ILD介電層及覆蓋層145的材料具有蝕刻選擇性的其它材料)，從而覆蓋該覆蓋層145的側壁表面145S以後的裝置100。執行共形沉積製程以在間隙壁空腔160中以及在側間隙壁120及下源/汲接觸結構155上方界定間隙壁層，並執行非等向性蝕刻製程以移除位於下源/汲接觸結構155上方的該間隙壁層的部分，從而界定上間隙壁165。
第1H圖顯示簡化形式的裝置100的頂視圖，以顯示鰭片110及閘極結構115。將接觸源/汲區125形成CA接觸，且將接觸閘極結構115形成CB接觸。CA及CB接觸的位置及數目可變化。
第1I圖及第1J圖顯示在執行數個製程以分別形成上源/汲接觸結構170(也就是CA接觸)及閘極接觸結構175(也就是CB接觸)以後的裝置100。執行沉積製程以形成介電層180，並執行圖案化製程(例如，光刻及蝕刻)以在介 電層180中界定接觸開口，從而暴露位於CA區中的下源/汲接觸結構155的一部分並暴露位於CB區中的覆蓋層145的一部分。執行選擇性蝕刻製程，以移除覆蓋層145的暴露部分。執行一個或多個製程以沉積用於上源/汲接觸結構170及閘極接觸結構175的導電材料(例如，襯裡層、阻擋層、晶種層、填充材料(鎢、鈷)等)。利用上間隙壁165的外表面165S1自對準針對上源/汲接觸結構170的該接觸開口，且利用覆蓋層145及上間隙壁165的內表面165S2自對準閘極接觸結構175。
第2A圖至第2E圖顯示用於採用氣隙間隙壁形成裝置200的方法的替代實施例。第2A圖顯示開始於針對第1E圖中的裝置100所示的製程階段，在執行沉積製程以在下源/汲接觸結構155上方形成中間源/汲接觸結構205(例如，鎢)以後的裝置200。可沉積用於中間源/汲接觸結構205的材料，並可執行蝕刻製程以凹入該材料直至暴露側間隙壁120的頂部。
第2B圖顯示在執行選擇性蝕刻製程以移除側間隙壁120，從而界定下間隙壁空腔210以後的裝置200。
第2C圖顯示在執行沉積製程以形成介電材料215(例如，SiBCN)從而夾止下間隙壁空腔201，以界定氣隙220以後的裝置200。介電材料215可加襯(line)下間隙壁空腔210的下部，或者它可僅夾止下間隙壁空腔210的上邊界。介電材料215可被稱為側間隙壁，其中界定有氣隙。
可如第1F圖至第1J圖中所述繼續裝置200的製程，以形成上源/汲接觸結構170及閘極接觸結構175，如第2D圖及第2E圖中所示。
由於本發明可以本領域的技術人員借助本文中的教導而明白的不同但等同的方式修改並實施，因此上面所揭露的特定實施例僅為示例性質。例如，可以不同的順序執行上述製程步驟。而且，本發明並非意圖限於本文中所示 的架構或設計的細節，而是如所附申請專利範圍所述。因此，顯然，可對上面所揭露的特定實施例進行修改或變更，且所有此類變更落入本發明的範圍及精神內。要注意的是，用於說明本說明書以及所附申請專利範圍中的各種製程或結構的例如“第一”、“第二”、“第三”或者“第四”等術語的使用僅被用作此類步驟/結構的快捷參考，並不一定意味著按排列順序執行/形成此類步驟/結構。當然，依據準確的申請專利範圍語言，可能要求或者不要求此類製程的排列順序。因此，本發明請求保護的範圍如所附申請專利範圍所述。
100‧‧‧裝置、半導體裝置或finFET裝置
105‧‧‧基板
110‧‧‧鰭片
115‧‧‧閘極結構
120‧‧‧側間隙壁或第一側間隙壁
125‧‧‧源/汲區
155‧‧‧下源/汲接觸結構
165‧‧‧上間隙壁
165S2‧‧‧內表面
175‧‧‧閘極接觸結構
180‧‧‧介電層

Claims (20)

  1. 一種半導體裝置，包括：主動層；閘極結構，位於該主動層的通道區上方；側間隙壁，位於鄰近該閘極結構；覆蓋層，位於該閘極結構上方；上間隙壁，接觸該覆蓋層的側壁表面、該側間隙壁的側壁表面以及該閘極結構的上表面的一部分；介電層，位於該上間隙壁及該覆蓋層上方；以及第一接觸結構，至少部分嵌入該介電層中並接觸該上間隙壁的表面。
  2. 如申請專利範圍第1項所述的半導體裝置，進一步包括：源/汲區，位於鄰近該側間隙壁的該主動層中；以及下源/汲接觸結構，接觸該源/汲區，其中，該第一接觸結構接觸該上間隙壁的外表面及該下源/汲接觸結構。
  3. 如申請專利範圍第1項所述的半導體裝置，其中，該第一接觸結構接觸該上間隙壁的內表面及該閘極結構。
  4. 如申請專利範圍第1項所述的半導體裝置，其中，該側間隙壁包括在其中界定的氣隙。
  5. 一種形成半導體裝置的方法，該方法包括：形成主動層；在該主動層的通道區上方形成閘極結構；鄰近該閘極結構形成側間隙壁； 鄰近該側間隙壁形成第一介電層；凹入該閘極結構以界定閘極空腔；在該閘極空腔中形成內間隙壁；在鄰近該內間隙壁的該閘極空腔中形成覆蓋層；凹入該第一介電層及該側間隙壁，以暴露該覆蓋層的側壁表面；移除該內間隙壁，以界定鄰近該覆蓋層的第一間隙壁空腔；在該第一間隙壁空腔中並接觸該覆蓋層的側壁表面形成上間隙壁；在該上間隙壁及該覆蓋層上方形成第二介電層；以及形成至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。
  6. 如申請專利範圍第5項所述的方法，進一步包括：在鄰近該側間隙壁的該主動層中形成源/汲區；形成接觸該源/汲區的下源/汲接觸結構；移除該第二介電層的第一部分，以暴露該下源/汲接觸結構及該上間隙壁的外表面並界定第一接觸空腔；以及在該第一接觸空腔中形成該第一接觸結構，該第一接觸結構接觸該上間隙壁的該外表面及該下源/汲接觸結構。
  7. 如申請專利範圍第6項所述的方法，進一步包括：移除該第二介電層的第二部分，以暴露該覆蓋層；移除該覆蓋層以暴露該上間隙壁的內表面及該閘極結構，從而界定第二接觸空腔；以及 在該第二接觸空腔中形成第二接觸結構，該第二接觸結構接觸該上間隙壁的該內表面及該閘極結構。
  8. 如申請專利範圍第5項所述的方法，進一步包括：移除該第二介電層的第一部分，以暴露該覆蓋層；移除該覆蓋層以暴露該上間隙壁的內表面及該閘極結構，從而界定第一接觸空腔；以及在該第一接觸空腔中形成該第一接觸結構，該第一接觸結構接觸該上間隙壁的該內表面及該閘極結構。
  9. 如申請專利範圍第5項所述的方法，進一步包括：在移除該內間隙壁之前移除該側間隙壁，以界定下間隙壁空腔；以及在該下間隙壁空腔的至少上部中形成介電材料，從而在鄰近該閘極結構的該下間隙壁空腔中界定氣隙。
  10. 如申請專利範圍第9項所述的方法，其中，該介電材料加襯該下間隙壁空腔。
  11. 如申請專利範圍第9項所述的方法，進一步包括：在鄰近該側間隙壁的鰭片中形成源/汲區；形成接觸該源/汲區的下源/汲接觸結構；移除該第二介電層的第一部分，以暴露該下源/汲接觸結構及該上間隙壁的外表面並界定第一接觸空腔；以及在該第一接觸空腔中形成該第一接觸結構，該第一接觸結構接觸該上間隙壁的該外表面及該下源/汲接觸結構。
  12. 如申請專利範圍第11項所述的方法，進一步包括： 在該下源/汲接觸結構上方形成中間源/汲接觸結構，該中間源/汲接觸結構暴露該側間隙壁的上部；在形成該中間源/汲接觸結構以後移除該側間隙壁；以及形成該第一接觸結構，以接觸該中間源/汲接觸結構。
  13. 如申請專利範圍第12項所述的方法，其中，該中間源/汲接觸結構與該第一接觸結構包括相同的材料。
  14. 一種形成半導體裝置的方法，該方法包括：形成主動層；在該主動層的通道區上方形成閘極結構；鄰近該閘極結構形成側間隙壁；在鄰近該側間隙壁的該主動層中形成源/汲區；鄰近該側間隙壁形成第一介電層；凹入該閘極結構以界定閘極空腔；在該閘極空腔中形成內間隙壁；在鄰近該內間隙壁的該閘極空腔中形成覆蓋層；凹入該第一介電層及該側間隙壁，以暴露該覆蓋層的側壁表面；鄰近該側間隙壁並接觸該源/汲區形成下源/汲接觸結構；移除該側間隙壁以界定下間隙壁空腔；在該下間隙壁空腔的至少上部中形成介電材料，以在鄰近該閘極結構的該下間隙壁空腔中界定氣隙；移除該內間隙壁，以界定鄰近該覆蓋層的第一間隙壁空腔；在該第一間隙壁空腔中並接觸該覆蓋層的側壁表面形成上間隙壁； 在該上間隙壁及該覆蓋層上方形成第二介電層；以及形成至少部分嵌入該第二介電層中並接觸該上間隙壁的表面的第一接觸結構。
  15. 如申請專利範圍第14項所述的方法，進一步包括：移除該第二介電層的第一部分，以暴露該下源/汲接觸結構及該上間隙壁的外表面並界定第一接觸空腔；以及在該第一接觸空腔中形成該第一接觸結構，該第一接觸結構接觸該上間隙壁的該外表面及該下源/汲接觸結構。
  16. 如申請專利範圍第15項所述的方法，進一步包括：移除該第二介電層的第二部分，以暴露該覆蓋層；移除該覆蓋層以暴露該上間隙壁的內表面及該閘極結構，從而界定第二接觸空腔；以及在該第二接觸空腔中形成第二接觸結構，該第二接觸結構接觸該上間隙壁的該內表面及該閘極結構。
  17. 如申請專利範圍第14項所述的方法，進一步包括：移除該第二介電層的第一部分，以暴露該覆蓋層；移除該覆蓋層以暴露該上間隙壁的內表面及該閘極結構，從而界定第一接觸空腔；以及在該第一接觸空腔中形成該第一接觸結構，該第一接觸結構接觸該上間隙壁的該內表面及該閘極結構。
  18. 如申請專利範圍第14項所述的方法，其中，該介電材料加襯該下間隙壁空腔。
  19. 如申請專利範圍第14項所述的方法，進一步包括：在該下源/汲接觸結構上方形成中間源/汲接觸結構，該中間源/汲接觸結構暴露該側間隙壁的上部；在形成該中間源/汲接觸結構以後移除該側間隙壁；以及形成該第一接觸結構，以接觸該中間源/汲接觸結構。
  20. 如申請專利範圍第19項所述的方法，其中，該中間源/汲接觸結構與該第一接觸結構包括相同的材料。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10825721B2 (en) * 2018-10-23 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating cap on contact structure and method for forming the same
US10892338B2 (en) 2018-10-24 2021-01-12 Globalfoundries Inc. Scaled gate contact and source/drain cap
US11798838B2 (en) * 2019-03-19 2023-10-24 Intel Corporation Capacitance reduction for semiconductor devices based on wafer bonding
US10903331B2 (en) * 2019-03-25 2021-01-26 International Business Machines Corporation Positioning air-gap spacers in a transistor for improved control of parasitic capacitance
US11094578B2 (en) * 2019-05-22 2021-08-17 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same
US11264284B2 (en) * 2019-06-20 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
KR20210038762A (ko) * 2019-09-30 2021-04-08 삼성전자주식회사 반도체 장치
CN113257783B (zh) * 2020-02-10 2024-05-10 华邦电子股份有限公司 存储器装置及其制造方法
DE102020119940A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Mehrfachgatetransistorstruktur
US11476157B2 (en) * 2021-01-07 2022-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance due to reduction of off-state capacitance of back-end-of-line (BEOL) features of the MOSFET
KR20220158340A (ko) * 2021-05-24 2022-12-01 삼성전자주식회사 게이트 구조체를 갖는 반도체 소자들 및 그 형성 방법
US11664422B2 (en) 2021-06-14 2023-05-30 International Business Machines Corporation Nanosheet transistor with ultra low-k spacer and improved patterning robustness

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052029A1 (en) * 2008-08-27 2010-03-04 Wen-Kuei Huang Transistor structure and dynamic random access memory structure including the same
US20170054004A1 (en) * 2015-08-19 2017-02-23 International Business Machines Corporation Forming a gate contact in the active area

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869379A (en) 1997-12-08 1999-02-09 Advanced Micro Devices, Inc. Method of forming air gap spacer for high performance MOSFETS'
US6238987B1 (en) * 1999-09-13 2001-05-29 United Microelectronics Corp. Method to reduce parasitic capacitance
JP4932088B2 (ja) * 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
TWI298175B (en) * 2005-11-09 2008-06-21 Promos Technologies Inc Gate structure and fabricating method thereof
TW200725707A (en) * 2005-12-30 2007-07-01 Ind Tech Res Inst Method for forming titanium silicide upon a semiconductor device with lower source/drain sheet resistance
TWI323489B (en) * 2006-08-11 2010-04-11 Mosel Vitelic Inc Fabricating process and structure of trench power semiconductor device
US7994040B2 (en) * 2007-04-13 2011-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication thereof
US7741663B2 (en) 2008-10-24 2010-06-22 Globalfoundries Inc. Air gap spacer formation
CN102646589B (zh) * 2011-02-17 2015-01-07 中芯国际集成电路制造(上海)有限公司 一种mosfet制造方法
US9082746B2 (en) * 2012-01-16 2015-07-14 Infineon Technologies Austria Ag Method for forming self-aligned trench contacts of semiconductor components and a semiconductor component
TW201423869A (zh) * 2012-12-13 2014-06-16 Anpec Electronics Corp 溝渠式電晶體的製作方法
US8946075B2 (en) 2013-03-05 2015-02-03 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
KR102167625B1 (ko) 2013-10-24 2020-10-19 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9331072B2 (en) * 2014-01-28 2016-05-03 Samsung Electronics Co., Ltd. Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same
US9093467B1 (en) * 2014-02-04 2015-07-28 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US9159822B2 (en) * 2014-02-24 2015-10-13 International Business Machines Corporation III-V semiconductor device having self-aligned contacts
US9305835B2 (en) 2014-02-26 2016-04-05 International Business Machines Corporation Formation of air-gap spacer in transistor
US9147748B1 (en) * 2014-05-01 2015-09-29 Globalfoundries Inc. Methods of forming replacement spacer structures on semiconductor devices
US9536982B1 (en) * 2015-11-03 2017-01-03 International Business Machines Corporation Etch stop for airgap protection
WO2017111774A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Transistor with inner-gate spacer
TWI663729B (zh) * 2016-01-05 2019-06-21 聯華電子股份有限公司 半導體結構及其製造方法
KR102374052B1 (ko) * 2016-02-26 2022-03-14 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9761483B1 (en) 2016-03-07 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, FinFET devices and methods of forming the same
US9735246B1 (en) 2016-05-11 2017-08-15 International Business Machines Corporation Air-gap top spacer and self-aligned metal gate for vertical fets
US9786784B1 (en) * 2016-05-27 2017-10-10 Samsung Electronics Co., Ltd. Vertical field effect transistor and method of fabricating the same
US9824921B1 (en) 2016-07-06 2017-11-21 Globalfoundries Inc. Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps
US10008577B2 (en) 2016-08-01 2018-06-26 Globalfoundries Inc. Methods of forming an air-gap spacer on a semiconductor device and the resulting device
US10446653B2 (en) * 2016-11-15 2019-10-15 Globalfoundries Inc. Transistor-based semiconductor device with air-gap spacers and gate contact over active area
US9929048B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Middle of the line (MOL) contacts with two-dimensional self-alignment
TWI727068B (zh) * 2017-07-03 2021-05-11 聯華電子股份有限公司 半導體裝置以及其製作方法
US11145747B2 (en) * 2017-10-25 2021-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET structure
KR102392845B1 (ko) * 2017-11-28 2022-04-29 삼성전자주식회사 반도체 장치
US10388747B1 (en) * 2018-03-28 2019-08-20 Globalfoundries Inc. Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052029A1 (en) * 2008-08-27 2010-03-04 Wen-Kuei Huang Transistor structure and dynamic random access memory structure including the same
US20170054004A1 (en) * 2015-08-19 2017-02-23 International Business Machines Corporation Forming a gate contact in the active area

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