TW202121535A - 利用犧牲閘極覆蓋間隔壁形成自對準閘極與源／汲接觸以及所得裝置 - Google Patents

利用犧牲閘極覆蓋間隔壁形成自對準閘極與源／汲接觸以及所得裝置 Download PDF

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TW202121535A
TW202121535A TW109139013A TW109139013A TW202121535A TW 202121535 A TW202121535 A TW 202121535A TW 109139013 A TW109139013 A TW 109139013A TW 109139013 A TW109139013 A TW 109139013A TW 202121535 A TW202121535 A TW 202121535A
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semiconductor device
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TWI748737B (zh
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朱利安 弗羅吉爾
謝瑞龍
朴燦柔
慷果 程
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種裝置，包括：主動層；閘極結構，位於該主動層的通道區上方；第一側間隙壁，位於鄰近該閘極結構；閘極覆蓋層，位於該閘極結構上方，該閘極覆蓋層包括絕緣材料；以及上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的內表面。

Description

利用犧牲閘極覆蓋間隔壁形成自對準閘極與源/汲接觸以及所得裝置
本揭露通常關於半導體裝置的製造，尤其關於用於利用犧牲閘極覆蓋間隙壁(sacrificial gate cap spacer)形成自對準閘極及源/汲接觸(source/drain contacts)的方法以及所得裝置。
通常，由於當前積體電路中的大量半導體裝置(也就是電路元件，例如電晶體、電阻器、電容器等)以及所需的複雜佈局，各半導體裝置例如電晶體、電容器等的電性連接或“線路佈置”無法在製造該些半導體裝置的同一裝置層級內建立。因此，在包括形成於該產品的該裝置層級上方的多個堆疊式“金屬化層”的金屬化系統中形成各種電性連接，其構成該積體電路(IC)產品的總體線路圖案。
為正常工作，對於典型的電晶體，針對該電晶體的導電閘極結構、源區及汲區形成獨立的導電路徑。該製程的部分包括形成通常所謂的裝置層級接觸，也就是，用於建立與該電晶體裝置的源/汲區的電性連接的多個所謂“CA接觸”結構，以及用於建立與該電晶體裝置的閘極結構的電性連接的閘極接觸結 構(有時被稱為“CB接觸”結構)。該CB閘極接觸通常垂直位於圍繞該電晶體裝置的隔離材料上方，也就是，該CB閘極接觸通常不位於主動區上方，但在一些先進架構中它可能位於主動區上方。
該CB閘極接觸通常位於隔離區上方，以避免或減少在該CB閘極接觸與形成於鄰近該電晶體的閘極結構的該電晶體的源/汲區中的導電源/汲結構(例如，溝槽矽化物(trench silicide；TS)結構)之間形成電性短路的概率。通常，也有設計規則規定在該CB閘極接觸與該導電源/汲結構之間必須保持的最小間距，以試圖防止此類電性短路。不幸的是，存在與該CB閘極接觸僅位於隔離區上方的要求相關聯的面積損失。此外，絕緣材料(通常採用至少側間隙壁的形式)位於閘極結構與位於該閘極結構的相對側上的導電源/汲結構之間。該間隙壁通常由具有例如約7-8的較高k值的氮化矽製成。由於電晶體的該物理配置，閘極-接觸(gate-to-contact)電容器被定義，其中，閘極電極充當該電容器的導電板，導電源/汲結構充當該電容器的另一個導電板，且間隙壁位於該兩個導電板之間。此閘極-接觸電容器在本質上是寄生的，因為每當開啟(on)與關閉(off)該電晶體裝置時，此電容器必須充電與放電，所有這些導致延遲該裝置的開關速度。
本揭露提供可避免或至少減少上述問題的其中一個或多個的影響的各種方法及所得裝置。
下面提供本發明的簡要總結，以提供本發明的一些態樣的基本理解。本發明內容並非詳盡概述本發明。其並非意圖識別本發明的關鍵或重要元件或劃定本發明的範圍。其唯一目的在於提供一些簡化形式的概念，作為後面所討論的更詳細說明的前序。
一般來說，本揭露關於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。一種示例裝置包括：主動層；閘極結構，位於該主動層的通道區上方；第一側間隙壁，位於鄰近該閘極結構；閘極覆蓋層，位於該閘極結構上方，該閘極覆蓋層包括絕緣材料；以及上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的內表面。
一種示例裝置包括：主動層；閘極結構，位於該主動層的通道區上方，當在該閘極結構的該上表面測量時，該閘極結構朝對應於該裝置之閘極長度方向的方向具有第一寬度；第一側間隙壁，位於鄰近該閘極結構；閘極覆蓋層，位於該閘極結構上方，當在該閘極結構的該上表面測量時，該閘極覆蓋層朝對應於該裝置之該閘極長度方向的方向具有第二寬度，其中，該第二寬度小於該第一寬度；以及上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的一部分。
另一種示例裝置包括：主動層；閘極結構，位於該主動層的通道區上方，當在該閘極結構的該上表面測量時，該閘極結構朝對應於該裝置之閘極長度方向的方向具有第一寬度；第一側間隙壁，位於鄰近該閘極結構；閘極覆蓋層，位於該閘極結構上方，當在該閘極結構的該上表面測量時，該閘極覆蓋層朝對應於該裝置之該閘極長度方向的方向具有第二寬度，其中，該第二寬度小於該第一寬度；以及上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的內表面。
100:裝置、半導體裝置或finFET裝置
105:基板
110:鰭片
115:閘極結構
120:側間隙壁或第一側間隙壁
125:源/汲區
130:介電層
135:覆蓋空腔
140:內間隙壁
140S:外側壁表面
145:覆蓋層
145S:側壁表面
150:接觸開口
155:下源/汲接觸結構
160:間隙壁空腔
165:上間隙壁
165S1:外表面
165S2:內表面
170:上源/汲接觸結構
175:閘極接觸結構
180:介電層
200:裝置
205:中間源/汲接觸結構
210:下間隙壁空腔
215:介電材料
220:氣隙
CA、CB:接觸
參照下面結合附圖所作的說明可理解本揭露，該些附圖中類似的附圖標記表示類似的元件，且其中：
第1A圖至第1J圖顯示本文中所揭露的用於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置；以及
第2A圖至第2E圖顯示本文中所揭露的用於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。
儘管本文中所揭露的發明主題容許各種修改及替代形式，但本發明主題的特定實施例以示例方式顯示於附圖中並在本文中作詳細說明。不過，應當理解，本文中有關特定實施例的說明並非意圖將本發明限於所揭露的特定形式，相反，意圖涵蓋落入由所附申請專利範圍定義的本發明的精神及範圍內的所有修改、等同及替代。
下面說明本發明的各種示例實施例。出於清楚目的，不是實際實施中的全部特徵都在本說明書中進行說明。當然，應當瞭解，在任意此類實際實施例的開發中，必須作大量的特定實施決定以實現開發者的特定目標，例如符合與系統相關及與商業相關的約束條件，該些決定將因不同實施而異。而且，應當瞭解，此類開發努力可能複雜而耗時，但其仍然是本領域的普通技術人員借助本揭露所執行的常規程序。
現在將參照附圖來說明本發明主題。附圖中示意各種結構、系統及裝置僅是出於解釋目的以及避免使本揭露與本領域技術人員已知的細節混淆，但仍包括該些附圖以說明並解釋本揭露的示例。本文中所使用的詞語和詞組的意思應當被理解並解釋為與相關領域技術人員對這些詞語及詞組的理解一致。本文中的術語或詞組的連貫使用並不意圖暗含特別的定義，亦即與本領域技術人員所理解的通常或慣用意思不同的定義。若術語或詞組意圖具有特別意思， 亦即不同於本領域技術人員所理解的意思，則此類特別定義會以直接明確地提供該術語或詞組的特別定義的定義方式明確表示於說明書中。
本揭露通常關於利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法以及所得裝置。在完整閱讀本申請以後，本領域的技術人員很容易明白，當前的方法可用於各種裝置，包括但不限於邏輯裝置、記憶體(memory)裝置等。現在通過參照附圖來更詳細地說明本文中所揭露的方法及裝置的各種示例實施例。
第1A圖至第1J圖顯示用於在半導體裝置100中利用犧牲閘極覆蓋間隙壁形成自對準閘極及源/汲接觸的各種方法。在該示例實施例中，針對finFET裝置形成該些接觸，不過，該些技術的應用不限於特定類型的裝置，且它們可應用於構建於塊體、SOI或混合基板上的例如平面電晶體、環繞閘極(gate-all-around；GAA)奈米線電晶體、GAA奈米片電晶體等其它結構。第1A圖至第1G圖及第1I圖至第1J圖顯示基板105的剖視圖(沿裝置100的閘極長度方向，也就是，沿當該裝置操作時電流流動的方向)，在該基板105中界定有鰭片110(如虛線所界定)。在鰭片110的通道區上方形成閘極結構115，該閘極結構包括閘極絕緣層(例如，高k材料，如二氧化鉿)以及金屬閘極電極(例如，包含一個或多個層，例如阻擋層、功函數材料層、晶種層、導電填充層等)-未獨立顯示。鄰近閘極結構115形成第一側間隙壁120(例如，SiN、SiOC等)。在鄰近閘極結構115及側間隙壁120的鰭片110中所界定的溝槽中形成源/汲區125(例如，外延生長半導體材料，例如矽鍺、矽碳、矽、矽磷等，取決於特定的電晶體裝置類型)。鄰近第一側間隙壁120形成介電層130(例如，二氧化矽、低k介電材料、超低k介電材料等)。
本文中所示的finFET裝置100可為NMOS或PMOS電晶體。此外，在基板105、鰭片110或源/汲區125中可形成各種摻雜區，例如環狀注入 區、阱區等，但附圖中未顯示這些摻雜區。基板105可具有各種配置，例如所示塊體矽配置。基板105還可具有包括塊體矽層、埋置絕緣層及主動層的絕緣體上矽(silicon-on-insulator；SOI)配置，其中，在該主動層中及上方形成半導體裝置。基板105及/或鰭片110可由矽或矽鍺形成，或者它可由矽以外的材料例如鍺製成。因此，術語“基板”或“半導體基板”應當被理解為涵蓋所有半導體材料以及此類材料的所有形式。基板105可具有不同的層。例如，鰭片110可形成於在基板105的基礎層上方所形成的製程層中。
第1B圖顯示在執行蝕刻製程以凹入閘極結構115從而界定覆蓋空腔135並執行數個製程以在覆蓋空腔135的側壁上形成內間隙壁140(例如，非晶矽)以後的裝置100。執行共形沉積製程以在覆蓋空腔135中及在介電層130上方界定間隙壁層，以及執行非等向性(anisotropic)蝕刻製程以移除該間隙壁層的水平部分，從而界定內間隙壁140。
第1C圖顯示在執行沉積製程以在覆蓋空腔135中形成覆蓋層145(例如，氮化矽)並執行平坦化製程以移除位於覆蓋空腔135外部的覆蓋層145的部分以後的裝置100。
第1D圖顯示在執行一個或多個蝕刻製程以凹入介電層130，從而界定鄰近側間隙壁120的接觸開口150，以暴露源/汲區125以後的裝置100。該一個或多個蝕刻製程還降低側間隙壁120的高度，從而暴露內間隙壁140的外側壁表面140S。儘管在第1D圖中不可見，但接觸開口150延伸於具有側間隙壁120的相鄰閘極結構115之間。為便於說明，未顯示相鄰的閘極結構115。該一個或多個蝕刻製程可包括：用以選擇性凹入介電層130的等向性(isotropic)蝕刻，接著用以降低側間隙壁120的高度的選擇性非等向性蝕刻；用以降低側間隙壁120的高度的選擇性非等向性蝕刻，接著用以選擇性凹入向源/汲區125提供 保護的介電層130的等向性蝕刻；或者經定時以凹入介電層130並降低側間隙壁120的高度的非等向性蝕刻。
第1E圖顯示在接觸開口150中形成下源/汲接觸結構155(例如，溝槽矽化物)以後的裝置100。下源/汲接觸結構155可通過填充接觸開口150並執行蝕刻製程以凹入下源/汲接觸結構155來形成。
第1F圖顯示在執行選擇性蝕刻製程以移除內間隙壁140，從而在側間隙壁120與覆蓋層145之間形成間隙壁空腔160以後的裝置100。
第1G圖顯示執行數個製程以在側間隙壁120上方及間隙壁空腔160中形成上間隙壁165(例如，SiOC或者相對後續ILD介電層及覆蓋層145的材料具有蝕刻選擇性的其它材料)，從而覆蓋該覆蓋層145的側壁表面145S以後的裝置100。執行共形沉積製程以在間隙壁空腔160中以及在側間隙壁120及下源/汲接觸結構155上方界定間隙壁層，並執行非等向性蝕刻製程以移除位於下源/汲接觸結構155上方的該間隙壁層的部分，從而界定上間隙壁165。
第1H圖顯示簡化形式的裝置100的頂視圖，以顯示鰭片110及閘極結構115。將接觸源/汲區125形成CA接觸，且將接觸閘極結構115形成CB接觸。CA及CB接觸的位置及數目可變化。
第1I圖及第1J圖顯示在執行數個製程以分別形成上源/汲接觸結構170(也就是CA接觸)及閘極接觸結構175(也就是CB接觸)以後的裝置100。執行沉積製程以形成介電層180，並執行圖案化製程(例如，光刻及蝕刻)以在介電層180中界定接觸開口，從而暴露位於CA區中的下源/汲接觸結構155的一部分並暴露位於CB區中的覆蓋層145的一部分。執行選擇性蝕刻製程，以移除覆蓋層145的暴露部分。執行一個或多個製程以沉積用於上源/汲接觸結構170及閘極接觸結構175的導電材料(例如，襯裡層、阻擋層、晶種層、填充材料(鎢、鈷)等)。利用上間隙壁165的外表面165S1自對準針對上源/汲接觸結構170的 該接觸開口，且利用覆蓋層145及上間隙壁165的內表面165S2自對準閘極接觸結構175。
第2A圖至第2E圖顯示用於採用氣隙間隙壁形成裝置200的方法的替代實施例。第2A圖顯示開始於針對第1E圖中的裝置100所示的製程階段，在執行沉積製程以在下源/汲接觸結構155上方形成中間源/汲接觸結構205(例如，鎢)以後的裝置200。可沉積用於中間源/汲接觸結構205的材料，並可執行蝕刻製程以凹入該材料直至暴露側間隙壁120的頂部。
第2B圖顯示在執行選擇性蝕刻製程以移除側間隙壁120，從而界定下間隙壁空腔210以後的裝置200。
第2C圖顯示在執行沉積製程以形成介電材料215(例如，SiBCN)從而夾止下間隙壁空腔201，以界定氣隙220以後的裝置200。介電材料215可加襯(line)下間隙壁空腔210的下部，或者它可僅夾止下間隙壁空腔210的上邊界。介電材料215可被稱為側間隙壁，其中界定有氣隙。
可如第1F圖至第1J圖中所述繼續裝置200的製程，以形成上源/汲接觸結構170及閘極接觸結構175，如第2D圖及第2E圖中所示。
由於本發明可以本領域的技術人員借助本文中的教導而明白的不同但等同的方式修改並實施，因此上面所揭露的特定實施例僅為示例性質。例如，可以不同的順序執行上述製程步驟。而且，本發明並非意圖限於本文中所示的架構或設計的細節，而是如所附申請專利範圍所述。因此，顯然，可對上面所揭露的特定實施例進行修改或變更，且所有此類變更落入本發明的範圍及精神內。要注意的是，用於說明本說明書以及所附申請專利範圍中的各種製程或結構的例如“第一”、“第二”、“第三”或者“第四”等術語的使用僅被用作此類步驟/結構的快捷參考，並不一定意味著按排列順序執行/形成此類步驟/結構。當然，依據 準確的申請專利範圍語言，可能要求或者不要求此類製程的排列順序。因此，本發明請求保護的範圍如所附申請專利範圍所述。
100:裝置、半導體裝置或finFET裝置
105:基板
110:鰭片
115:閘極結構
120:側間隙壁或第一側間隙壁
125:源/汲區
155:下源/汲接觸結構
165:上間隙壁
165S2:內表面
175:閘極接觸結構
180:介電層

Claims (20)

  1. 一種半導體裝置，包括：
    主動層；
    閘極結構，位於該主動層的通道區上方；
    第一側間隙壁，位於鄰近該閘極結構；
    閘極覆蓋層，位於該閘極結構上方，該閘極覆蓋層包括絕緣材料；以及
    上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的內表面。
  2. 如申請專利範圍第1項所述的半導體裝置，其中，當在該閘極結構的該上表面測量時，該閘極覆蓋層朝對應於該裝置之閘極長度方向的方向具有第一寬度，以及當在該閘極結構的該上表面測量時，該閘極結構朝該閘極長度方向具有第二寬度，其中，該第一寬度小於該第二寬度。
  3. 如申請專利範圍第1項所述的半導體裝置，進一步包括閘極接觸結構，接觸該上間隙壁的內表面及該閘極結構的該上表面。
  4. 如申請專利範圍第1項所述的半導體裝置，其中，該第一側間隙壁包括在其中界定的氣隙。
  5. 如申請專利範圍第1項所述的半導體裝置，進一步包括：
    源/汲區，位於鄰近該第一側間隙壁；
    下源/汲接觸結構，接觸該源/汲區；以及
    源/汲接觸結構，接觸該上間隙壁的該外表面以及該下源/汲接觸結構。
  6. 如申請專利範圍第1項所述的半導體裝置，其中，該第一側間隙壁、該閘極覆蓋層以及該上間隙壁的每一個包括不同材料。
  7. 如申請專利範圍第1項所述的半導體裝置，其中，該上間隙壁接觸該閘極覆蓋層的該側壁表面。
  8. 一種半導體裝置，包括：
    主動層；
    閘極結構，位於該主動層的通道區上方，當在該閘極結構的該上表面測量時，該閘極結構朝對應於該裝置之閘極長度方向的方向具有第一寬度；
    第一側間隙壁，位於鄰近該閘極結構；
    閘極覆蓋層，位於該閘極結構上方，當在該閘極結構的該上表面測量時，該閘極覆蓋層朝對應於該裝置之該閘極長度方向的方向具有第二寬度，其中，該第二寬度小於該第一寬度；以及
    上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的一部分。
  9. 如申請專利範圍第8項所述的半導體裝置，進一步包括閘極接觸結構，接觸該上間隙壁的內表面及該閘極結構的該上表面。
  10. 如申請專利範圍第8項所述的半導體裝置，其中，該第一側間隙壁包括在其中界定的氣隙。
  11. 如申請專利範圍第8項所述的半導體裝置，進一步包括：
    源/汲區，位於鄰近該第一側間隙壁；
    下源/汲接觸結構，接觸該源/汲區；以及
    源/汲接觸結構，接觸該上間隙壁的該外表面以及該下源/汲接觸結構。
  12. 如申請專利範圍第8項所述的半導體裝置，其中，該上間隙壁的一部分接觸該閘極覆蓋層的側壁表面和該第一側間隙壁的內表面。
  13. 如申請專利範圍第8項所述的半導體裝置，其中，該第一側間隙壁、該閘極覆蓋層以及該上間隙壁的每一個包括不同材料。
  14. 一種半導體裝置，包括：
    主動層；
    閘極結構，位於該主動層的通道區上方，當在該閘極結構的該上表面測量時，該閘極結構朝對應於該裝置之閘極長度方向的方向具有第一寬度；
    第一側間隙壁，位於鄰近該閘極結構；
    閘極覆蓋層，位於該閘極結構上方，當在該閘極結構的該上表面測量時，該閘極覆蓋層朝對應於該裝置之該閘極長度方向的方向具有第二寬度，其中，該第二寬度小於該第一寬度；以及
    上間隙壁，接觸該閘極覆蓋層的側壁表面、該閘極結構的上表面的一部分以及該第一側間隙壁的內表面。
  15. 如申請專利範圍第14項所述的半導體裝置，進一步包括閘極接觸結構，接觸該上間隙壁的內表面及該閘極結構的該上表面。
  16. 如申請專利範圍第15項所述的半導體裝置，其中，該第一側間隙壁、該閘極覆蓋層以及該上間隙壁的每一個包括不同材料。
  17. 如申請專利範圍第14項所述的半導體裝置，其中，該第一側間隙壁包括在其中界定的氣隙。
  18. 如申請專利範圍第14項所述的半導體裝置，進一步包括：
    源/汲區，位於鄰近該第一側間隙壁；
    下源/汲接觸結構，接觸該源/汲區；以及
    源/汲接觸結構，接觸該上間隙壁的該外表面以及該下源/汲接觸結構。
  19. 如申請專利範圍第18項所述的半導體裝置，其中，該第一側間隙壁、該閘極覆蓋層以及該上間隙壁的每一個包括不同材料。
  20. 如申請專利範圍第14項所述的半導體裝置，其中，該第一側間隙壁、該閘極覆蓋層以及該上間隙壁的每一個包括不同材料。
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