CN110828554B - 形成自对准栅极及源/漏接触以及所得装置 - Google Patents

形成自对准栅极及源/漏接触以及所得装置 Download PDF

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CN110828554B
CN110828554B CN201910635745.8A CN201910635745A CN110828554B CN 110828554 B CN110828554 B CN 110828554B CN 201910635745 A CN201910635745 A CN 201910635745A CN 110828554 B CN110828554 B CN 110828554B
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CN110828554A (zh
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朱利安·弗罗吉尔
谢瑞龙
朴灿柔
程慷果
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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Abstract

本发明涉及形成自对准栅极及源/漏接触以及所得装置，其中，一种方法包括：形成主动层；在该主动层的沟道区上方形成栅极结构；邻近该栅极结构形成侧间隙壁；邻近该侧间隙壁形成第一介电层；凹入该栅极结构以界定栅极空腔；在该栅极空腔中形成内间隙壁；在该栅极空腔中形成覆盖层；凹入该第一介电层及该侧间隙壁，以暴露该覆盖层的侧壁表面；移除该内间隙壁，以界定第一间隙壁空腔；在该间隙壁空腔中并接触该覆盖层的侧壁表面形成上间隙壁；在该上间隙壁及该覆盖层上方形成第二介电层；以及形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。

Description

形成自对准栅极及源/漏接触以及所得装置
技术领域
本申请通常涉及半导体装置的制造，尤其涉及用于利用牺牲栅极覆盖间隙壁(sacrificial gate cap spacer)形成自对准栅极及源/漏接触的方法以及所得装置。
背景技术
通常，由于当前集成电路中的大量半导体装置(也就是电路元件，例如晶体管、电阻器、电容器等)以及所需的复杂布局，各半导体装置例如晶体管、电容器等的电性连接或“线路布置”无法在制造这些半导体装置的同一装置层级内建立。因此，在包括形成于该产品的该装置层级上方的多个堆叠式“金属化层”的金属化系统中形成各种电性连接，其构成该集成电路(IC)产品的总体线路图案。
为正常工作，对于典型的晶体管，针对该晶体管的导电栅极结构、源区及漏区形成独立的导电路径。该制程的部分包括形成通常所谓的装置层级接触，也就是，用于建立与该晶体管装置的源/漏区的电性连接的多个所谓“CA接触”结构，以及用于建立与该晶体管装置的栅极结构的电性连接的栅极接触结构(有时被称为“CB接触”结构)。该CB栅极接触通常垂直位于围绕该晶体管装置的隔离材料上方，也就是，该CB栅极接触通常不位于主动区上方，但在一些先进架构中它可能位于主动区上方。
该CB栅极接触通常位于隔离区上方，以避免或减少在该CB栅极接触与形成于邻近该晶体管的栅极结构的该晶体管的源/漏区中的导电源/漏结构(例如，沟槽硅化物(trenchsilicide；TS)结构)之间形成电性短路的概率。通常，也有设计规则规定在该CB栅极接触与该导电源/漏结构之间必须保持的最小间距，以试图防止此类电性短路。不幸的是，存在与该CB栅极接触仅位于隔离区上方的要求相关联的面积损失。此外，绝缘材料(通常采用至少侧间隙壁的形式)位于栅极结构与位于该栅极结构的相对侧上的导电源/漏结构之间。该间隙壁通常由具有例如约7-8的较高k值的氮化硅制成。由于晶体管的该物理配置，栅极-接触(gate-to-contact)电容器被定义，其中，栅极电极充当该电容器的导电板，导电源/漏结构充当该电容器的另一个导电板，且间隙壁位于该两个导电板之间。此栅极-接触电容器在本质上是寄生的，因为每当开启(on)与关闭(off)该晶体管装置时，此电容器必须充电与放电，所有这些导致延迟该装置的开关速度。
本申请提供可避免或至少减少上述问题的其中一个或多个的影响的各种方法及所得装置。
发明内容
下面提供本发明的简要总结，以提供本发明的一些方面的基本理解。本发明内容并非详尽概述本发明。其并非意图识别本发明的关键或重要元件或划定本发明的范围。其唯一目的在于提供一些简化形式的概念，作为后面所讨论的更详细说明的前序。
一般来说，本申请涉及利用牺牲栅极覆盖间隙壁形成自对准栅极及源/漏接触的各种方法以及所得装置。一种示例装置包括：除其它以外，主动层，位于该主动层的沟道区上方的栅极结构，邻近该栅极结构的侧间隙壁，位于该栅极结构上方的覆盖层，接触该覆盖层的侧壁表面以及该栅极结构的上表面的一部分的上间隙壁(upper spacer)，位于该上间隙壁及该覆盖层上方的第二介电层，以及至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。
一种示例方法包括：除其它以外，形成主动层；在该主动层的沟道区上方形成栅极结构；邻近该栅极结构形成侧间隙壁；邻近该侧间隙壁形成第一介电层；凹入该栅极结构以界定栅极空腔(cavity)；在该栅极空腔中形成内间隙壁；以及在邻近该内间隙壁的该栅极空腔中形成覆盖层。该方法还包括：凹入该第一介电层及该侧间隙壁，以暴露该覆盖层的侧壁表面；移除该内间隙壁，以界定邻近该覆盖层的第一间隙壁空腔；在该间隙壁空腔中并接触该覆盖层的侧壁表面形成上间隙壁；在该上间隙壁及该覆盖层上方形成第二介电层；以及形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。
另一种示例方法包括：除其它以外，形成主动层；在该主动层的沟道区上方形成栅极结构；邻近该栅极结构形成侧间隙壁；在邻近该侧间隙壁的该主动层中形成源/漏区；邻近该侧间隙壁形成第一介电层；凹入该栅极结构以界定栅极空腔；在该栅极空腔中形成内间隙壁；以及在邻近该内间隙壁的该栅极空腔中形成覆盖层。该方法还包括：凹入该第一介电层及该侧间隙壁，以暴露该覆盖层的侧壁表面；邻近该侧间隙壁并接触该源/漏区形成源/漏接触结构；移除该侧间隙壁以界定下间隙壁空腔(lower spacer cavity)；在该下间隙壁空腔的至少上部中形成介电材料，以在邻近该栅极结构的该下间隙壁空腔中界定气隙；移除该内间隙壁，以界定邻近该覆盖层的第一间隙壁空腔；在该间隙壁空腔中并接触该覆盖层的侧壁表面形成上间隙壁；在该上间隙壁及该覆盖层上方形成第二介电层；以及形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。
附图说明
参照下面结合附图所作的说明可理解本申请，这些附图中类似的附图标记表示类似的元件，且其中：
图1A至图1J显示本文中所揭示的用于利用牺牲栅极覆盖间隙壁形成自对准栅极及源/漏接触的各种方法以及所得装置；以及
图2A至图2E显示本文中所揭示的用于利用牺牲栅极覆盖间隙壁形成自对准栅极及源/漏接触的各种方法以及所得装置。
尽管本文中所揭示的发明主题容许各种修改及替代形式，但本发明主题的特定实施例以示例方式显示于附图中并在本文中作详细说明。不过，应当理解，本文中有关特定实施例的说明并非意图将本发明限于所揭示的特定形式，相反，意图涵盖落入由所附权利要求定义的本发明的精神及范围内的所有修改、等同及替代。
具体实施方式
下面说明本发明的各种示例实施例。出于清楚目的，不是实际实施中的全部特征都在本说明书中进行说明。当然，应当了解，在任意此类实际实施例的开发中，必须作大量的特定实施决定以实现开发者的特定目标，例如符合与系统相关及与商业相关的约束条件，这些决定将因不同实施而异。而且，应当了解，此类开发努力可能复杂而耗时，但其仍然是本领域的普通技术人员借助本申请所执行的常规程序。
现在将参照附图来说明本发明主题。附图中示意各种结构、系统及装置仅是出于解释目的以及避免使本申请与本领域技术人员已知的细节混淆，但仍包括这些附图以说明并解释本申请的示例。本文中所使用的词语和词组的意思应当被理解并解释为与相关领域技术人员对这些词语及词组的理解一致。本文中的术语或词组的连贯使用并不意图暗含特别的定义，亦即与本领域技术人员所理解的通常或惯用意思不同的定义。若术语或词组意图具有特别意思，亦即不同于本领域技术人员所理解的意思，则此类特别定义会以直接明确地提供该术语或词组的特别定义的定义方式明确表示于说明书中。
本申请通常涉及利用牺牲栅极覆盖间隙壁形成自对准栅极及源/漏接触的各种方法以及所得装置。在完整阅读本申请以后，本领域的技术人员很容易明白，当前的方法可用于各种装置，包括但不限于逻辑装置、存储器(memory)装置等。现在通过参照附图来更详细地说明本文中所揭示的方法及装置的各种示例实施例。
图1A至图1J显示用于在半导体装置100中利用牺牲栅极覆盖间隙壁形成自对准栅极及源/漏接触的各种方法。在该示例实施例中，针对finFET装置形成这些接触，不过，这些技术的应用不限于特定类型的装置，且它们可应用于构建于块体、SOI或混合衬底上的例如平面晶体管、环绕栅极(gate-all-around；GAA)纳米线晶体管、GAA纳米片晶体管等其它结构。图1A至图1G及图1I至图1J显示衬底105的剖视图(沿装置100的栅极长度方向，也就是，沿当该装置操作时电流流动的方向)，在该衬底105中界定有鳍片110(如虚线所界定)。在鳍片110的沟道区上方形成栅极结构115，该栅极结构包括栅极绝缘层(例如，高k材料，如二氧化铪)以及金属栅极电极(例如，包含一个或多个层，例如阻挡层、功函数材料层、晶种层、导电填充层等)-未独立显示。邻近栅极结构115形成第一侧间隙壁120(例如，SiN、SiOC等)。在邻近栅极结构115及侧间隙壁120的鳍片110中所界定的沟槽中形成源/漏区125(例如，外延生长半导体材料，例如硅锗、硅碳、硅、硅磷等，取决于特定的晶体管装置类型)。邻近第一侧间隙壁120形成介电层130(例如，二氧化硅、低k介电材料、超低k介电材料等)。
本文中所示的finFET装置100可为NMOS或PMOS晶体管。此外，在衬底105、鳍片110或源/漏区125中可形成各种掺杂区，例如环状注入区、阱区等，但附图中未显示这些掺杂区。衬底105可具有各种配置，例如所示块体硅配置。衬底105还可具有包括块体硅层、埋置绝缘层及主动层的绝缘体上硅(silicon-on-insulator；SOI)配置，其中，在该主动层中及上方形成半导体装置。衬底105及/或鳍片110可由硅或硅锗形成，或者它可由硅以外的材料例如锗制成。因此，术语“衬底”或“半导体衬底”应当被理解为涵盖所有半导体材料以及此类材料的所有形式。衬底105可具有不同的层。例如，鳍片110可形成于在衬底105的基础层上方所形成的制程层中。
图1B显示在执行蚀刻制程以凹入栅极结构115从而界定覆盖空腔135并执行数个制程以在覆盖空腔135的侧壁上形成内间隙壁140(例如，非晶硅)以后的装置100。执行共形沉积制程以在覆盖空腔135中及在介电层130上方界定间隙壁层，以及执行非等向性(anisotropic)蚀刻制程以移除该间隙壁层的水平部分，从而界定内间隙壁140。
图1C显示在执行沉积制程以在覆盖空腔135中形成覆盖层145(例如，氮化硅)并执行平坦化制程以移除位于覆盖空腔135外部的覆盖层145的部分以后的装置100。
图1D显示在执行一个或多个蚀刻制程以凹入介电层130，从而界定邻近侧间隙壁120的接触开口150，以暴露源/漏区125以后的装置100。该一个或多个蚀刻制程还降低侧间隙壁120的高度，从而暴露内间隙壁140的外侧壁表面140S。尽管在图1D中不可见，但接触开口150延伸于具有侧间隙壁120的相邻栅极结构115之间。为便于说明，未显示相邻的栅极结构115。该一个或多个蚀刻制程可包括：用以选择性凹入介电层130的等向性(isotropic)蚀刻，接着用以降低侧间隙壁120的高度的选择性非等向性蚀刻；用以降低侧间隙壁120的高度的选择性非等向性蚀刻，接着用以选择性凹入向源/漏区125提供保护的介电层130的等向性蚀刻；或者经定时以凹入介电层130并降低侧间隙壁120的高度的非等向性蚀刻。
图1E显示在接触开口150中形成下源/漏接触结构155(例如，沟槽硅化物)以后的装置100。下源/漏接触结构155可通过填充接触开口150并执行蚀刻制程以凹入下源/漏接触结构155来形成。
图1F显示在执行选择性蚀刻制程以移除内间隙壁140，从而在侧间隙壁120与覆盖层145之间形成间隙壁空腔160以后的装置100。
图1G显示执行数个制程以在侧间隙壁120上方及间隙壁空腔160中形成上间隙壁165(例如，SiOC或者相对后续ILD介电层及覆盖层145的材料具有蚀刻选择性的其它材料)，从而覆盖该覆盖层145的侧壁表面145S以后的装置100。执行共形沉积制程以在间隙壁空腔160中以及在侧间隙壁120及下源/漏接触结构155上方界定间隙壁层，并执行非等向性蚀刻制程以移除位于下源/漏接触结构155上方的该间隙壁层的部分，从而界定上间隙壁165。
图1H显示简化形式的装置100的顶视图，以显示鳍片110及栅极结构115。将接触源/漏区125形成CA接触，且将接触栅极结构115形成CB接触。CA及CB接触的位置及数目可变化。
图1I及图1J显示在执行数个制程以分别形成上源/漏接触结构170(也就是CA接触)及栅极接触结构175(也就是CB接触)以后的装置100。执行沉积制程以形成介电层180，并执行图案化制程(例如，光刻及蚀刻)以在介电层180中界定接触开口，从而暴露位于CA区中的下源/漏接触结构155的一部分并暴露位于CB区中的覆盖层145的一部分。执行选择性蚀刻制程，以移除覆盖层145的暴露部分。执行一个或多个制程以沉积用于上源/漏接触结构170及栅极接触结构175的导电材料(例如，衬里层、阻挡层、晶种层、填充材料(钨、钴)等)。利用上间隙壁165的外表面165S1自对准针对上源/漏接触结构170的该接触开口，且利用覆盖层145及上间隙壁165的内表面165S2自对准栅极接触结构175。
图2A至图2E显示用于采用气隙间隙壁形成装置200的方法的替代实施例。图2A显示开始于针对图1E中的装置100所示的制程阶段，在执行沉积制程以在下源/漏接触结构155上方形成中间源/漏接触结构205(例如，钨)以后的装置200。可沉积用于中间源/漏接触结构205的材料，并可执行蚀刻制程以凹入该材料直至暴露侧间隙壁120的顶部。
图2B显示在执行选择性蚀刻制程以移除侧间隙壁120，从而界定下间隙壁空腔210以后的装置200。
图2C显示在执行沉积制程以形成介电材料215(例如，SiBCN)从而夹止下间隙壁空腔201，以界定气隙220以后的装置200。介电材料215可加衬(line)下间隙壁空腔210的下部，或者它可仅夹止下间隙壁空腔210的上边界。介电材料215可被称为侧间隙壁，其中界定有气隙。
可如图1F至图1J中所述继续装置200的制程，以形成上源/漏接触结构170及栅极接触结构175，如图2D及图2E中所示。
由于本发明可以本领域的技术人员借助本文中的教导而明白的不同但等同的方式修改并实施，因此上面所揭示的特定实施例仅为示例性质。例如，可以不同的顺序执行上述制程步骤。而且，本发明并非意图限于本文中所示的架构或设计的细节，而是如所附权利要求所述。因此，显然，可对上面所揭示的特定实施例进行修改或变更，且所有此类变更落入本发明的范围及精神内。要注意的是，用于说明本说明书以及所附权利要求中的各种制程或结构的例如“第一”、“第二”、
“第三”或者“第四”等术语的使用仅被用作此类步骤/结构的快捷参考，并不一定意味着按排列顺序执行/形成此类步骤/结构。当然，依据准确的权利要求语言，可能要求或者不要求此类制程的排列顺序。因此，本发明请求保护的范围如所附权利要求所述。

Claims (20)

1.一种半导体装置，包括：
主动层；
栅极结构，位于该主动层的沟道区上方；
侧间隙壁，位于邻近该栅极结构；
覆盖层，位于该栅极结构上方；
上间隙壁，覆盖该覆盖层的侧壁表面，且接触该侧间隙壁的侧壁表面的一部分以及该栅极结构的上表面的一部分；
介电层，位于该上间隙壁及该覆盖层上方；以及
第一接触结构，至少部分嵌入该介电层中并接触该上间隙壁的表面。
2.如权利要求1所述的半导体装置，还包括：
源/漏区，位于邻近该侧间隙壁的该主动层中；以及
下源/漏接触结构，接触该源/漏区，其中，该第一接触结构接触该上间隙壁的外表面及该下源/漏接触结构。
3.如权利要求1所述的半导体装置，其中，该第一接触结构接触该上间隙壁的内表面及该栅极结构。
4.如权利要求1所述的半导体装置，其中，该侧间隙壁包括在其中界定的气隙。
5.一种形成半导体装置的方法，该方法包括：
形成主动层；
在该主动层的沟道区上方形成栅极结构；
邻近该栅极结构形成侧间隙壁；
邻近该侧间隙壁形成第一介电层；
凹入该栅极结构以界定栅极空腔；
在该栅极空腔中形成内间隙壁；
在邻近该内间隙壁的该栅极空腔中形成覆盖层；
凹入该第一介电层及该侧间隙壁，以暴露该覆盖层的侧壁表面；
移除该内间隙壁，以界定邻近该覆盖层的第一间隙壁空腔；
在该第一间隙壁空腔中并覆盖该覆盖层的侧壁表面且接触该侧间隙壁的侧壁表面的一部分以及该栅极结构的上表面的一部分形成上间隙壁；
在该上间隙壁及该覆盖层上方形成第二介电层；以及
形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。
6.如权利要求5所述的方法，还包括：
在邻近该侧间隙壁的该主动层中形成源/漏区；
形成接触该源/漏区的下源/漏接触结构；
移除该第二介电层的第一部分，以暴露该下源/漏接触结构及该上间隙壁的外表面并界定第一接触空腔；以及
在该第一接触空腔中形成该第一接触结构，该第一接触结构接触该上间隙壁的该外表面及该下源/漏接触结构。
7.如权利要求6所述的方法，还包括：
移除该第二介电层的第二部分，以暴露该覆盖层；
移除该覆盖层以暴露该上间隙壁的内表面及该栅极结构，从而界定第二接触空腔；以及
在该第二接触空腔中形成第二接触结构，该第二接触结构接触该上间隙壁的该内表面及该栅极结构。
8.如权利要求5所述的方法，还包括：
移除该第二介电层的第一部分，以暴露该覆盖层；
移除该覆盖层以暴露该上间隙壁的内表面及该栅极结构，从而界定第一接触空腔；以及
在该第一接触空腔中形成该第一接触结构，该第一接触结构接触该上间隙壁的该内表面及该栅极结构。
9.如权利要求5所述的方法，还包括：
在移除该内间隙壁之前移除该侧间隙壁，以界定下间隙壁空腔；以及
在该下间隙壁空腔的至少上部中形成介电材料，从而在邻近该栅极结构的该下间隙壁空腔中界定气隙。
10.如权利要求9所述的方法，其中，该介电材料加衬该下间隙壁空腔。
11.如权利要求9所述的方法，还包括：
在邻近该侧间隙壁的鳍片中形成源/漏区；
形成接触该源/漏区的下源/漏接触结构；
移除该第二介电层的第一部分，以暴露该下源/漏接触结构及该上间隙壁的外表面并界定第一接触空腔；以及
在该第一接触空腔中形成该第一接触结构，该第一接触结构接触该上间隙壁的该外表面及该下源/漏接触结构。
12.如权利要求11所述的方法，还包括：
在该下源/漏接触结构上方形成中间源/漏接触结构，该中间源/漏接触结构暴露该侧间隙壁的上部；
在形成该中间源/漏接触结构以后移除该侧间隙壁；以及
形成该第一接触结构，以接触该中间源/漏接触结构。
13.如权利要求12所述的方法，其中，该中间源/漏接触结构与该第一接触结构包括相同的材料。
14.一种形成半导体装置的方法，该方法包括：
形成主动层；
在该主动层的沟道区上方形成栅极结构；
邻近该栅极结构形成侧间隙壁；
在邻近该侧间隙壁的该主动层中形成源/漏区；
邻近该侧间隙壁形成第一介电层；
凹入该栅极结构以界定栅极空腔；
在该栅极空腔中形成内间隙壁；
在邻近该内间隙壁的该栅极空腔中形成覆盖层；
凹入该第一介电层及该侧间隙壁，以暴露该覆盖层的侧壁表面；
邻近该侧间隙壁并接触该源/漏区形成下源/漏接触结构；
移除该侧间隙壁以界定下间隙壁空腔；
在该下间隙壁空腔的至少上部中形成介电材料，以在邻近该栅极结构的该下间隙壁空腔中界定气隙；
移除该内间隙壁，以界定邻近该覆盖层的第一间隙壁空腔；
在该第一间隙壁空腔中并覆盖该覆盖层的侧壁表面且接触该侧间隙壁的侧壁表面的一部分以及该栅极结构的上表面的一部分形成上间隙壁；
在该上间隙壁及该覆盖层上方形成第二介电层；以及
形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。
15.如权利要求14所述的方法，还包括：
移除该第二介电层的第一部分，以暴露该下源/漏接触结构及该上间隙壁的外表面并界定第一接触空腔；以及
在该第一接触空腔中形成该第一接触结构，该第一接触结构接触该上间隙壁的该外表面及该下源/漏接触结构。
16.如权利要求15所述的方法，还包括：
移除该第二介电层的第二部分，以暴露该覆盖层；
移除该覆盖层以暴露该上间隙壁的内表面及该栅极结构，从而界定第二接触空腔；以及
在该第二接触空腔中形成第二接触结构，该第二接触结构接触该上间隙壁的该内表面及该栅极结构。
17.如权利要求14所述的方法，还包括：
移除该第二介电层的第一部分，以暴露该覆盖层；
移除该覆盖层以暴露该上间隙壁的内表面及该栅极结构，从而界定第一接触空腔；以及
在该第一接触空腔中形成该第一接触结构，该第一接触结构接触该上间隙壁的该内表面及该栅极结构。
18.如权利要求14所述的方法，其中，该介电材料加衬该下间隙壁空腔。
19.如权利要求14所述的方法，还包括：
在该下源/漏接触结构上方形成中间源/漏接触结构，该中间源/漏接触结构暴露该侧间隙壁的上部；
在形成该中间源/漏接触结构以后移除该侧间隙壁；以及
形成该第一接触结构，以接触该中间源/漏接触结构。
20.如权利要求19所述的方法，其中，该中间源/漏接触结构与该第一接触结构包括相同的材料。
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