TWI706521B - 半導體封裝器件及其製造方法 - Google Patents

半導體封裝器件及其製造方法 Download PDF

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TWI706521B
TWI706521B TW107107802A TW107107802A TWI706521B TW I706521 B TWI706521 B TW I706521B TW 107107802 A TW107107802 A TW 107107802A TW 107107802 A TW107107802 A TW 107107802A TW I706521 B TWI706521 B TW I706521B
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Taiwan
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substrate
semiconductor package
protective layer
package device
opening
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TW107107802A
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TW201917838A (zh
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房昱安
曾吉生
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日月光半導體製造股份有限公司
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

本發明提供一種半導體封裝器件，其包含一基板、一電子組件及一保護層。該基板具有一第一表面及與該第一表面相對之一第二表面。該基板限定穿透該基板之一第一開口。該電子組件安置於該基板之該第一表面上。該保護層安置於該基板之該第二表面上。該保護層具有鄰近該第一開口之一第一部分及安置成比該保護層之該第一部分更遠離該第一開口之一第二部分。該保護層之該第一部分具有背離該基板之該第二表面之一表面。該保護層之該第二部分具有背離該基板之該第二表面之一表面。該保護層之該第一部分之該表面與該基板之該第二表面之間的一距離大於該保護層之該第二部分之該表面與該基板之該第二表面之間的一距離。

Description

半導體封裝器件及其製造方法
本發明大體上係關於半導體封裝器件及其製造方法。本發明係關於包括排氣孔之半導體封裝器件及其製造方法。
在光學平面柵格陣列(OLGA)結構中，基板限定穿透該基板之排氣孔(或開口)。在單體化程序期間，OLGA結構附接於膠帶上以避免污染物(例如水、其他顆粒或材料碎屑)進入排氣孔進而污染或損壞晶片或晶粒。然而，由於高度差(例如，覆蓋基板上之導電襯墊或跡線之保護層的高度大於直接位於基板上之保護層的高度)，直接位於基板上的不覆蓋導電襯墊或跡線的保護層無法緊密地或氣密地附接至膠帶，如此可能在保護層與膠帶之間留下間隙。因此，污染物可經由保護層與膠帶之間的間隙進入排氣孔進而污染或損壞晶片或晶粒。
在一個態樣中，根據一些實施例，半導體封裝器件包括基板、電子組件及保護層。基板具有第一表面及與該第一表面相對之第二表面。基板限定穿透該基板之第一開口。電子組件安置於基板之第一表面上。保護層安置於基板之第二表面上。保護層具有鄰近第一開口之第一部分及比保護 層之第一部分更遠離第一開口之第二部分。保護層之第一部分具有背離基板之第二表面的表面。保護層之第二部分具有背離基板之第二表面的表面。保護層之第一部分的表面與該基板之第二表面之間的距離大於保護層之第二部分的表面與基板之第二表面之間的距離。
在另一態樣中，根據一些實施例，半導體封裝器件包括基板、電子組件、金屬結構及保護層。基板具有第一表面及與該第一表面相對之第二表面。基板限定穿透該基板之第一開口。電子組件安置於基板之第一表面上。金屬結構安置於基板之第二表面上且鄰近第一開口。保護層包括覆蓋基板之第二表面之第一部分及覆蓋金屬結構之第二部分。
在又一態樣中，根據一些實施例，半導體封裝器件包括基板、電子組件、金屬結構及保護層。基板具有第一表面及與該第一表面相對之第二表面。基板限定穿透該基板之第一開口。電子組件安置於基板之第一表面上。金屬結構安置於基板之第二表面上。保護層覆蓋金屬結構且沿基板之第二表面延伸以限定在第一開口下方之第二開口。
1:半導體封裝器件
2:半導體封裝器件
3:半導體封裝器件
4:半導體封裝器件
5:半導體封裝器件
10:基板
10h:排氣孔/開口
10c1:導電襯墊
10c2:金屬結構
11a:電子組件
11b:電子組件
12:殼體
13:保護層
13a:第一部分
13a1:表面
13b:第二部分
13b':第二部分
13b1:表面
13b1':表面
13c:第三部分
13c1:表面
13h:孔隙
15a:支撐結構
15b:透明板
40:托架
40h:開口
41:導電接頭
41a:金屬襯墊
41b:焊錫膏
41c:金屬襯墊
60:基板
60h:排氣孔
62:導電襯墊
62a:金屬結構
63a:保護層
63b:保護層
65:膠帶
101:頂部表面
102:底部表面
當結合隨附圖式閱讀時，自以下實施方式最佳地理解本發明之態樣。應注意，各種特徵可不按比例繪製，且在圖式中，為清晰論述起見，所描繪特徵之尺寸可任意增大或減小。
圖1說明根據本發明之一些實施例之半導體封裝器件的橫截面視圖。
圖2A說明根據本發明之一些實施例之半導體封裝器件的橫截面視圖。
圖2B說明根據本發明之一些實施例之半導體封裝器件的仰視圖。
圖3說明根據本發明之一些實施例之半導體封裝器件的橫截面視圖。
圖4說明根據本發明之一些實施例之半導體封裝器件的橫截面視圖。
圖5說明根據本發明之一些實施例之半導體封裝器件的橫截面視圖。
圖6A及圖6B說明製造半導體封裝器件之比較方法。
圖7說明根據本發明之一些實施例之製造半導體封裝器件之方法。
貫穿圖式及實施方式使用共同參考編號以指示相同或類似元件。將易於自結合隨附圖式作出的以下實施方式來理解本發明。
圖1說明根據本發明之第一態樣的半導體封裝器件1之一些實施例的橫截面視圖。半導體封裝器件1包括基板10、電子組件11a、電子組件11b、殼體(或封蓋)12及保護層13。
基板10可包括(例如)印刷電路板，諸如紙基銅箔層合物、複合銅箔層合物或聚合物浸漬的基於玻璃纖維之銅箔層合物。基板10可包括互連結構，諸如重佈層(RDL)或接地元件。基板10具有頂部表面101(亦稱為「第一表面」)及與該頂部表面101相對之底部表面102(亦稱為「第二表面」)。基板10限定穿透基板10之開口(或排氣孔)10h。基板10包括安置於基板10之底部表面102上之一或多個導電襯墊10c1，以提供半導體封裝器件1與其他電路或電路板之間的電連接。
電子組件11a及11b安置於基板10之頂部表面101上。電子組件11a及11b可為主動組件，諸如積體電路(IC)晶片或晶粒。電子組件11a及11b可為被動組件，諸如電容器、電阻器或電感器。在一些實施例中，電子組件11a及11b可包括發光晶粒或其他光學晶粒。舉例而言，第一電子組件11a及11b可包括發光二極體(LED)、雷射二極體或可包括一或多個半導體層之另一器件。電子組件11a及11b可電連接至另一電子組件或基板10中之 一或多者(例如，電連接至基板10之RDL)，且可藉助於倒裝晶片或導線接合技術實現電連接。殼體12安置於基板10之頂部表面101上以覆蓋電子組件11a及11b。
保護層13安置於基板10之底部表面102上。在一些實施例中，保護層13包括第一部分13a、第二部分13b及第三部分13c。第一部分13a覆蓋導電襯墊10c1之一部分。在一些實施例中，第一部分13a與導電襯墊10c1之部分共形。第二部分13b安置於基板10之底部表面102之第一部分上，且包圍開口10h，鄰近開口10h、安置在開口10h周圍或部分地限定開口10h。第一部分13a及/或第三部分13c可安置成比第二部分13b更遠離開口10h。第三部分13c安置於不由第二部分13b覆蓋之基板10之底部表面102的第二部分上。在一些實施例中，保護層13包括薄膜型感光材料。在一些實施例中，第一部分13a、第二部分13b及第三部分13c限定凹座。第三部分13c可限定凹座之底部。
在一些實施例中，保護層13之第二部分13b的厚度大於保護層13之第三部分13c的厚度。舉例而言，保護層13之第二部分13b的表面13b1與基板10之底部表面102之間的距離(沿與基板10之底部表面102正交的方向)大於保護層13之第三部分13c的表面13c1與基板10之底部表面102之間的距離(沿與基板10之底部表面102正交的方向)，例如大至少約1.1倍、大至少約1.2倍或大至少約1.3倍。在一些實施例中，保護層13之第二部分13b的厚度實質上等同於或大於保護層13之第一部分13a的厚度與導電襯墊10c1的厚度之總和。舉例而言，保護層13之第二部分13b的表面13b1與基板10之底部表面102之間的距離實質上等同於或大於保護層13之第一部分13a的表面13a1與基板10之底部表面102之間的距離(沿與基板10之底部表面 102正交的方向)。
藉由增加鄰近開口10h之保護層之一部分(例如保護層13之第二部分13b)的高度或厚度以實質上等於或大於覆蓋導電襯墊10c1之保護層之一部分(例如保護層13之第一部分13a)的高度或厚度，保護層13(包括鄰近開口10h之部分)可在製造程序期間緊密地或氣密地附接至膠帶，如此可防止污染物(例如水或其他顆粒或材料碎屑)進入開口10h而污染或損壞電子組件11a、11b。
圖2A說明根據本發明之第二態樣的半導體封裝器件2之一些實施例的橫截面視圖。半導體封裝器件2類似於圖1中所示之半導體封裝器件1，不同之處在於半導體封裝器件2進一步包括安置於基板10之底部表面102上之金屬結構10c2。
如圖2B中所示，其說明根據本發明之一些實施例之半導體封裝器件2的仰視圖，金屬結構10c2安置在開口10h周圍、鄰近於開口10h或包圍開口10h。金屬結構10c2可安置成比導電襯墊10c1更接近開口10h，且導電襯墊10c1可與金屬結構10c2間隔開。返回參考圖2A，金屬結構10c2由保護層13之第二部分13b'覆蓋(例如完全覆蓋)。舉例而言，保護層13之第二部分13b'與金屬結構10c2共形。在一些實施例中，金屬結構10c2包括虛設襯墊或接地襯墊。在一些實施例中，保護層13之第二部分13b'可覆蓋安置於基板10之底部表面102上的不同於金屬結構10c2的結構。
在一些實施例中，保護層13之第二部分13b'的表面13b1'與基板10之底部表面102之間的距離大於保護層13之第三部分13c的表面13c1與基板10之底部表面102之間的距離，例如大至少約1.1倍、大至少約1.2倍或大至少約1.3倍。在一些實施例中，保護層13之第二部分13b'的表面13b1'與 基板10之底部表面102之間的距離實質上等同於或大於保護層13之第一部分13a的表面13a1與基板10之底部表面102之間的距離。在一些實施例中，保護層13具有實質上均一的厚度。舉例而言，保護層13之第一部分13a、第二部分13b'及第三部分13c的厚度實質上相同。
藉由將金屬結構10c2安置在開口10h周圍來增加鄰近開口10h之保護層之一部分(例如保護層13之第二部分13b')的高度，保護層13(包括鄰近開口10h的部分)可在製造過程序間緊密地或氣密地附接至膠帶，如此可防止污染物(例如水或其他顆粒或材料碎屑)進入開口10h而污染或損壞電子組件11a、11b。另外，金屬結構10c2及導電層(例如導電襯墊10c1)可以相同程序形成(例如可形成為完整的單體結構)中，且因此可省略用於形成金屬結構10c2之額外程序。
圖3說明根據本發明之第三態樣的半導體封裝器件3之一些實施例的橫截面視圖。半導體封裝器件3類似於圖2a中所示之半導體封裝器件2，不同之處在於半導體封裝器件3之保護層13進一步沿基板10之底部表面102延伸且突出超過開口10h之邊緣以限定孔隙13h。在一些實施例中，孔隙13h之寬度小於開口10h之寬度。
在一些實施例中，基板10之開口10h係藉由機械鑽孔或雷射鑽孔形成，且開口10h之最小寬度(最小橫截面寬度)在約80微米(μm)至約100μm的範圍內。孔隙13h係藉由微影技術形成且可具有約20μm或更小(例如約18μm或更小、約16μm或更小、約14μm或更小或再小)之最小寬度。藉由使開口之大小減小至基板10之排氣孔，可增強阻斷污染物進入開口10h而污染或損壞電子組件11a、11b的能力。
圖4說明根據本發明之第四態樣的半導體封裝器件4之一些實施例的 橫截面視圖。半導體封裝器件4類似於圖2a中所示之半導體封裝器件2，不同之處在於半導體封裝器件4進一步包括安置於基板10與電子組件11a及11b之間的托架40。
電子組件11a及11b安置於托架40上。殼體12安置於托架40上以覆蓋電子組件11a及11b。托架40安置於基板10之頂部表面101上且經由導電接頭41電連接至基板10。在一些實施例中，導電接頭41包括由金屬襯墊41a及金屬襯墊41c包夾之焊錫膏41b。托架40限定穿透該托架40之開口40h。在一些實施例中，托架40之開口40h與基板10之開口10h實質上對準(例如托架40之開口40h的中心與開口10h的中心對準)。在一些實施例中，導電接頭41安置成鄰近開口10h或安置在開口10h周圍或包圍開口10h，且可充當密封元件以防止污染物進入開口40h而污染或損壞電子組件11a、11b。
圖5說明根據本發明之第五態樣的半導體封裝器件5之一些實施例的橫截面視圖。半導體封裝器件5類似於圖3中所示之半導體封裝器件3，不同之處在於，代替圖3中所示之殼體12或除圖3中所展示之殼體12之外，半導體器件5可使用支撐結構15a及透明板15b來實施。
支撐結構15a安置於基板10之頂部表面101上且透明圓15b安置於支撐結構15a上。在一些實施例中，透明板15b為玻璃板。在一些實施例中，透明板15b經組態以允許傳輸自電子組件11a及11b發射或由該等電子組件接收的光(例如電子組件11a及11b經組態以發射或接收的光)。
圖6A說明半導體封裝器件之比較製造程序之一或多個操作。限定排氣孔60h之基板60附接於膠帶65(或另一類型之黏著層)上。如圖6A中所示，鄰近排氣孔60h或安置在排氣孔60h周圍之保護層63a的厚度小於導電襯墊62的厚度與覆蓋導電襯墊62之保護層63b的厚度之總和，且因此在保 護層63a與膠帶65之間存在間隙。因此，污染物可經由保護層63a與膠帶65之間的間隙進入排氣孔60h而污染或損壞基板60上之晶片或晶粒。在一些實施例中，污染物可沿圖6A及圖6B中所示之箭頭的方向進入排氣孔60h，圖6A及圖6B說明根據比較程序之基板60之仰視圖。
圖7說明根據本發明之一些實施例的半導體封裝器件之製造程序的一或多個操作。圖7中所示之半導體封裝器件類似於圖6A中所示之半導體封裝器件，不同之處在於，圖7中所示之半導體封裝器件進一步包括金屬結構62a(例如虛設襯墊或接地襯墊)，其安置在排氣孔60h周圍或包圍排氣孔60h，或位於排氣孔60h之與安置有導電襯墊62之一側相對的一側上，以增加在排氣孔60h周圍之結構的總厚度。在此類實施中，在保護層63a與膠帶65之間實質上不存在間隙，或保護層63a可直接接觸膠帶65，且保護層63a可在製造程序期間緊密地或氣密地附接至膠帶65，如此可防止污染物進入排氣孔60h而污染或損傷基板60上之晶片或晶粒。
如本文中所使用，術語「近似地」、「實質上」、「實質」及「約」用以描述及解釋小變化。當與事件或情形結合使用時，術語可指代事件或情形明確發生之情況以及事件或情形極近似於發生之情況。舉例而言，當結合數值使用時，該等術語可指代小於或等於該數值之±10%的變化範圍，諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%，或小於或等於±0.05%。舉例而言，若兩個數值之間的差小於或等於該等值之平均值的±10%(諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%)，則可認為該兩個數值「實質上」相 同。舉例而言，「實質上」平行可指代相對於0°之小於或等於±10°之角度變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或小於或等於±0.05°。舉例而言，「實質上」垂直可指代相對於90°之±10°之角度變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或小於或等於±0.05°。
若兩個表面之間的移位不大於5μm、不大於2μm、不大於1μm或不大於0.5μm，則可認為該兩個表面共面或實質上共面。若兩個點或軸線之間的移位不大於5μm、不大於2μm、不大於1μm或不大於0.5μm，則可認為該兩個點或軸線對準或實質上對準。若表面之最高點與最低點之間的差不大於5μm、不大於2μm、不大於1μm或不大於0.5μm，則可認為該表面係平面或實質上平面的。
如本文所使用，術語「導電(conductive)」、「導電(electrically conductive)」及「電導率」係指傳送電流之能力。導電材料通常指示對電流流動呈現極小或零阻力之彼等材料。電導率之一個量度為西門子每米(S/m)。通常，導電材料為具有近似大於104S/m(諸如至少105S/m或至少106S/m)之電導率的一種材料。材料之電導率有時可隨溫度變化。除非另外規定，否則材料之電導率係在室溫下量測。
除非上下文另有明確規定，否則如本文所使用，單數術語「一(a/an)」及「該」可包括複數個指代物。在一些實施例之描述中，提供在另一組件「上」或「上方」之組件可涵蓋前一組件直接在後一組件上(例如，與後一組件實體接觸)的狀況以及一或多個介入組件位於前一組件與 後一組件之間的狀況。
儘管已參考本發明之具體實施例描述且說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者可清楚地理解，可進行各種改變，且可在實施例內取代等效組件而不脫離如由所附申請專利範圍所限定之本發明的真實精神及範疇。該等說明可不必按比例繪製。歸因於製造程序中的變數等等，本發明中之藝術再現與實際設備之間可存在區別。可存在並未具體說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可作出修改，以使特定情形、材料、物質組成、方法或程序適應於本發明之目標、精神及範疇。所有此類修改均意欲處於所附之申請專利範圍之範疇內。儘管已參考按特定次序執行之特定操作來描述本文中所揭示之方法，但可理解，在不脫離本發明之教示的情況下，可組合、細分，或重新定序此等操作以形成等效方法。因此，除非在本文中特定指示，否則操作之次序及分組並非本發明之限制。
1‧‧‧半導體封裝器件
10‧‧‧基板
10c1‧‧‧導電襯墊
10h‧‧‧排氣孔/開口
11a‧‧‧電子組件
11b‧‧‧電子組件
12‧‧‧殼體
13‧‧‧保護層
13a‧‧‧第一部分
13a1‧‧‧表面
13b‧‧‧第二部分
13b1‧‧‧表面
13c‧‧‧第三部分
13c1‧‧‧表面
101‧‧‧頂部表面
102‧‧‧底部表面

Claims (29)

  1. 一種半導體封裝器件，其包含：一基板，其具有一第一表面及與該第一表面相對之一第二表面，該基板限定穿透該基板之一第一開口；一電子組件，其安置於該基板之該第一表面上；一保護層，其安置於該基板之該第二表面上，該保護層包含鄰近該第一開口之一第一部分及安置成比該保護層之該第一部分更遠離該第一開口的一第二部分，該保護層之該第一部分具有背離該基板之該第二表面之一表面，該保護層之該第二部分具有背離該基板之該第二表面之一表面，其中該保護層之該第一部分的該表面與該基板之該第二表面之間的一距離大於該保護層之該第二部分的該表面與該基板之該第二表面之間的一距離。
  2. 如請求項1之半導體封裝器件，其進一步包含安置於該基板之該第二表面上之一導電襯墊，其中該保護層進一步包括一第三部分，該第三部分覆蓋該導電襯墊之一部分且具有背離該基板之該第二表面之一表面，且其中該保護層之該第一部分的該表面與該基板之該第二表面之間的該距離實質上等於或大於該保護層之該第三部分的該表面與該基板之該第二表面之間的一距離。
  3. 如請求項2之半導體封裝器件，其中該保護層與該導電襯墊共形。
  4. 如請求項1之半導體封裝器件，其進一步包含安置於該基板之該第二表面上且由該保護層之該第一部分覆蓋之一金屬結構。
  5. 如請求項4之半導體封裝器件，其中該金屬結構包含一虛設襯墊或一接地襯墊。
  6. 如請求項4之半導體封裝器件，其中該金屬結構包圍該第一開口。
  7. 如請求項1之半導體封裝器件，其進一步包含安置於該基板之該第一表面上且覆蓋該電子組件之一殼體。
  8. 如請求項1之半導體封裝器件，其中該保護層包括一感光材料。
  9. 如請求項1之半導體封裝器件，其中該保護層沿該基板之該第二表面延伸且突出超過該第一開口之一邊緣以限定一第二開口。
  10. 如請求項9之半導體封裝器件，其中該第一開口之一寬度大於該第二開口之一寬度。
  11. 如請求項1之半導體封裝器件，其進一步包含安置於該基板與該電子組件之間的一托架，其中該托架限定與該基板之該第一開口實質上對準之一排氣孔。
  12. 如請求項11之半導體封裝器件，其進一步包含包圍該第一開口及該排氣孔之一密封元件。
  13. 一種半導體封裝器件，其包含一基板，其具有一第一表面及與該第一表面相對之一第二表面，該基板限定穿透該基板之一第一開口；一電子組件，其安置於該基板之該第一表面上；一金屬結構，其安置於該基板之該第二表面上且鄰近該第一開口；及一保護層，其包含覆蓋該基板之該第二表面之一第一部分及覆蓋該金屬結構之一第二部分。
  14. 如請求項13之半導體封裝器件，其中該保護層之該第一部分的一厚度實質上等同於該保護層之該第二部分的一厚度。
  15. 如請求項13之半導體封裝器件，其中該保護層之該第二部分的一表面與該基板之該第二表面之間的一距離大於該保護層之該第一部分的一表面與該基板之該第二表面之間的一距離。
  16. 如請求項13之半導體封裝器件，其進一步包含安置於該基板之該第二表面上且比該金屬結構更遠離該第一開口之一導電襯墊，該導電襯墊與該金屬結構間隔開，其中該保護層包含覆蓋該導電襯墊之一部分的一第三部分。
  17. 如請求項16之半導體封裝器件，其中該保護層與該金屬結構及該導電襯墊共形。
  18. 如請求項13之半導體封裝器件，其中該金屬結構包圍該第一開口。
  19. 如請求項13之半導體封裝器件，其中該金屬結構包含一虛設襯墊或一接地襯墊。
  20. 如請求項13之半導體封裝器件，其進一步包含安置於該基板之該第一表面上且覆蓋該電子組件之一殼體。
  21. 如請求項13之半導體封裝器件，其中該保護層包括一感光材料。
  22. 如請求項13之半導體封裝器件，其中該保護層沿該基板之該第二表面延伸且突出超過該第一開口之一邊緣以限定一第二開口。
  23. 如請求項22之半導體封裝器件，其中該第一開口係藉由機械鑽孔形成且該第二開口係藉由一微影技術形成。
  24. 如請求項13之半導體封裝器件，其進一步包含安置於該基板與該電子組件之間的一托架，其中該托架限定與該基板之該第一開口實質上對準之一排氣孔。
  25. 如請求項24之半導體封裝器件，其進一步包含包圍該第一開口及該排氣孔之一密封元件。
  26. 一種半導體封裝器件，其包含一基板，其具有一第一表面及與該第一表面相對之一第二表面，該基板限定穿透該基板之一第一開口；一電子組件，其安置於該基板之該第一表面上；一金屬結構，其安置於該基板之該第二表面上；及一保護層，其覆蓋該金屬結構且沿該基板之該第二表面延伸以限定在該第一開口下方之一第二開口。
  27. 如請求項26之半導體封裝器件，其中該第一開口係藉由機械鑽孔形成且該第二開口係藉由一微影技術形成。
  28. 如請求項26之半導體封裝器件，其中該第一開口之一寬度大於該第二開口之一寬度。
  29. 如請求項26之半導體封裝器件，其中該保護層包括一感光材料。
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