CN109712942B - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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CN109712942B
CN109712942B CN201810191125.5A CN201810191125A CN109712942B CN 109712942 B CN109712942 B CN 109712942B CN 201810191125 A CN201810191125 A CN 201810191125A CN 109712942 B CN109712942 B CN 109712942B
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substrate
protective layer
opening
semiconductor package
disposed
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CN109712942A (zh
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房昱安
曾吉生
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

一种半导体封装装置包括衬底、电子组件及保护层。所述衬底具有第一表面及与所述第一表面相对的第二表面。所述衬底限定穿透所述衬底的第一开口。所述电子组件安置于所述衬底的所述第一表面上。所述保护层安置于所述衬底的所述第二表面上。所述保护层具有邻近所述第一开口的第一部分及安置成比所述保护层的所述第一部分更远离所述第一开口的第二部分。所述保护层的所述第一部分具有背离所述衬底的所述第二表面的表面。所述保护层的所述第二部分具有背离所述衬底的所述第二表面的表面。所述保护层的所述第一部分的所述表面与所述衬底的所述第二表面之间的距离大于所述保护层的所述第二部分的所述表面与所述衬底的所述第二表面之间的距离。

Description

半导体封装装置及其制造方法
技术领域
本发明通常涉及半导体封装装置及其制造方法。本发明涉及包含排气孔的半导体封装装置及其制造方法。
背景技术
在光学平面栅格阵列(OLGA)结构中，衬底限定穿透所述衬底的排气孔(或开口)。在单体化过程期间，OLGA结构附接于胶带上以避免污染物(例如水、其它颗粒或材料碎屑)进入排气孔进而污染或损坏芯片或裸片。然而，由于高度差(例如，覆盖衬底上的导电衬垫或迹线的保护层的高度大于直接位于衬底上的保护层的高度)，直接位于衬底上的不覆盖导电衬垫或迹线的保护层无法紧密地或气密地附接至胶带，这可能在保护层与胶带之间留下间隙。因此，污染物可经由保护层与胶带之间的间隙进入排气孔而污染或损坏芯片或裸片。
发明内容
在一个方面中，根据一些实施例，半导体封装装置包含衬底、电子组件及保护层。衬底具有第一表面及与所述第一表面相对的第二表面。衬底限定穿透所述衬底的第一开口。电子组件安置于衬底的第一表面上。保护层安置于衬底的第二表面上。保护层具有邻近第一开口的第一部分及比保护层的第一部分更远离第一开口的第二部分。保护层的第一部分具有背离衬底的第二表面的表面。保护层的第二部分具有背离衬底的第二表面的表面。保护层的第一部分的表面与所述衬底的第二表面之间的距离大于保护层的第二部分的表面与衬底的第二表面之间的距离。
在另一方面中，根据一些实施例，半导体封装装置包含衬底、电子组件、金属结构及保护层。衬底具有第一表面及与所述第一表面相对的第二表面。衬底限定穿透所述衬底的第一开口。电子组件安置于衬底的第一表面上。金属结构安置于衬底的第二表面上且邻近第一开口。保护层包含覆盖衬底的第二表面的第一部分及覆盖金属结构的第二部分。
在又一方面中，根据一些实施例，半导体封装装置包含衬底、电子组件、金属结构及保护层。衬底具有第一表面及与所述第一表面相对的第二表面。衬底限定穿透所述衬底的第一开口。电子组件安置于衬底的第一表面上。金属结构安置于衬底的第二表面上。保护层覆盖金属结构且沿衬底的第二表面延伸以限定在第一开口下方的第二开口。
附图说明
当结合随附图式阅读时，从以下实施方式最佳地理解本发明的方面。应注意，各种特征可不按比例绘制，且在图式中，为清晰论述起见，所描绘特征的尺寸可任意增大或减小。
图1说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图2A说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图2B说明根据本发明的一些实施例的半导体封装装置的仰视图。
图3说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图4说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图5说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图6A及图6B说明制造半导体封装装置的比较方法。
图7说明根据本发明的一些实施例的制造半导体封装装置的方法。
贯穿图式及实施方式使用共同参考编号以指示相同或类似元件。将易于从结合随附图式作出的以下实施方式来理解本发明。
具体实施方式
图1说明根据本发明的第一方面的半导体封装装置1的一些实施例的横截面视图。半导体封装装置1包含衬底10、电子组件11a、电子组件11b、壳体(或封盖)12及保护层13。
衬底10可包含(例如)印刷电路板，诸如纸基铜箔层合物、复合铜箔层合物或聚合物浸渍的基于玻璃纤维的铜箔层合物。衬底10可包含互连结构，诸如再分布层(RDL)或接地元件。衬底10具有顶部表面101(也称为“第一表面”)及与所述顶部表面101相对的底部表面102(也称为“第二表面”)。衬底10限定穿透衬底10的开口(或排气孔)10h。衬底10包含安置于衬底10的底部表面102上的一或多个导电衬垫10c1，以提供半导体封装装置1与其它电路或电路板之间的电连接。
电子组件11a及11b安置于衬底10的顶部表面101上。电子组件11a及11b可为有源组件，诸如积体电路(IC)芯片或裸片。电子组件11a及11b可为无源组件，诸如电容器、电阻器或电感器。在一些实施例中，电子组件11a及11b可包含发光裸片或其它光学裸片。举例来说，第一电子组件11a及11b可包含发光二极管(LED)、激光二极管或可包含一或多个半导体层的另一装置。电子组件11a及11b可电连接到另一电子组件或衬底10中的一或多者(例如，电连接到衬底10的RDL)，且可借助于倒装芯片或导线接合技术实现电连接。壳体12安置于衬底10的顶部表面101上以覆盖电子组件11a及11b。
保护层13安置于衬底10的底部表面102上。在一些实施例中，保护层13包含第一部分13a、第二部分13b及第三部分13c。第一部分13a覆盖导电衬垫10c1的一部分。在一些实施例中，第一部分13a与导电衬垫10c1的部分共形。第二部分13b安置于衬底10的底部表面102的第一部分上，且包围开口10h，邻近开口10h、安置在开口10h周围或部分地限定开口10h。第一部分13a及/或第三部分13c可安置成比第二部分13b更远离开口10h。第三部分13c安置于不由第二部分13b覆盖的衬底10的底部表面102的第二部分上。在一些实施例中，保护层13包含薄膜型感光材料。在一些实施例中，第一部分13a、第二部分13b及第三部分13c限定凹座。第三部分13c可限定凹座的底部。
在一些实施例中，保护层13的第二部分13b的厚度大于保护层13的第三部分13c的厚度。举例来说，保护层13的第二部分13b的表面13b1与衬底10的底部表面102之间的距离(沿与衬底10的底部表面102正交的方向)大于保护层13的第三部分13c的表面13c1与衬底10的底部表面102之间的距离(沿与衬底10的底部表面102正交的方向)，例如大至少约1.1倍、大至少约1.2倍或大至少约1.3倍。在一些实施例中，保护层13的第二部分13b的厚度基本上等同于或大于保护层13的第一部分13a的厚度与导电衬垫10c1的厚度的总和。举例来说，保护层13的第二部分13b的表面13b1与衬底10的底部表面102之间的距离基本上等同于或大于保护层13的第一部分13a的表面13a1与衬底10的底部表面102之间的距离(沿与衬底10的底部表面102正交的方向)。
通过增加邻近开口10h的保护层的一部分(例如保护层13的第二部分13b)的高度或厚度以基本上等于或大于覆盖导电衬垫10c1的保护层的一部分(例如保护层13的第一部分13a)的高度或厚度，保护层13(包含邻近开口10h的部分)可在制造过程期间紧密地或气密地附接至胶带，这可防止污染物(例如水或其它颗粒或材料碎屑)进入开口10h而污染或损坏电子组件11a、11b。
图2A说明根据本发明的第二方面的半导体封装装置2的一些实施例的横截面视图。半导体封装装置2类似于图1中所示的半导体封装装置1，不同之处在于半导体封装装置2进一步包含安置于衬底10的底部表面102上的金属结构10c2。
如图2B中所示，其说明根据本发明的一些实施例的半导体封装装置2的仰视图，金属结构10c2安置在开口10h周围、邻近于开口10h或包围开口10h。金属结构10c2可安置成比导电衬垫10c1更接近开口10h，且导电衬垫10c1可与金属结构10c2间隔开。返回参考图2A，金属结构10c2由保护层13的第二部分13b'覆盖(例如完全覆盖)。举例来说，保护层13的第二部分13b'与金属结构10c2共形。在一些实施例中，金属结构10c2包含虚设衬垫或接地衬垫。在一些实施例中，保护层13的第二部分13b'可覆盖安置于衬底10的底部表面102上的不同于金属结构10c2的结构。
在一些实施例中，保护层13的第二部分13b'的表面13b1'与衬底10的底部表面102之间的距离大于保护层13的第三部分13c的表面13c1与衬底10的底部表面102之间的距离，例如大至少约1.1倍、大至少约1.2倍或大至少约1.3倍。在一些实施例中，保护层13的第二部分13b'的表面13b1'与衬底10的底部表面102之间的距离基本上等同于或大于保护层13的第一部分13a的表面13a1与衬底10的底部表面102之间的距离。在一些实施例中，保护层13具有基本上均一的厚度。举例来说，保护层13的第一部分13a、第二部分13b'及第三部分13c的厚度基本上相同。
通过将金属结构10c2安置在开口10h周围来增加邻近开口10h的保护层的一部分(例如保护层13的第二部分13b')的高度，保护层13(包含邻近开口10h的部分)可在制造过过程间紧密地或气密地附接至胶带，如此可防止污染物(例如水或其它颗粒或材料碎屑)进入开口10h而污染或损坏电子组件11a、11b。另外，金属结构10c2及导电层(例如导电衬垫10c1)可以相同过程形成(例如可形成为完整的单体结构)中，且因此可省略用于形成金属结构10c2的额外过程。
图3说明根据本发明的第三方面的半导体封装装置3的一些实施例的横截面视图。半导体封装装置3类似于图2a中所示的半导体封装装置2，不同之处在于半导体封装装置3的保护层13进一步沿衬底10的底部表面102延伸且突出超过开口10h的边缘以限定孔隙13h。在一些实施例中，孔隙13h的宽度小于开口10h的宽度。
在一些实施例中，衬底10的开口10h通过机械钻孔或激光钻孔形成，且开口10h的最小宽度(最小横截面宽度)在约80微米(μm)至约100μm的范围内。孔隙13h通过微影技术形成且可具有约20μm或更小(例如约18μm或更小、约16μm或更小、约14μm或更小或再小)的最小宽度。通过使开口的大小减小至衬底10的排气孔，可增强阻断污染物进入开口10h而污染或损坏电子组件11a、11b的能力。
图4说明根据本发明的第四方面的半导体封装装置4的一些实施例的横截面视图。半导体封装装置4类似于图2a中所示的半导体封装装置2，不同之处在于半导体封装装置4进一步包含安置于衬底10与电子组件11a及11b之间的托架40。
电子组件11a及11b安置于托架40上。壳体12安置于托架40上以覆盖电子组件11a及11b。托架40安置于衬底10的顶部表面101上且经由导电接头41电连接到衬底10。在一些实施例中，导电接头41包含由金属衬垫41a及金属衬垫41c包夹的焊锡膏41b。托架40限定穿透所述托架40的开口40h。在一些实施例中，托架40的开口40h与衬底10的开口10h基本上对准(例如托架40的开口40h的中心与开口10h的中心对准)。在一些实施例中，导电接头41安置成邻近开口10h或安置在开口10h周围或包围开口10h，且可充当密封元件以防止污染物进入开口40h而污染或损坏电子组件11a、11b。
图5说明根据本发明的第五方面的半导体封装装置5的一些实施例的横截面视图。半导体封装装置5类似于图3中所示的半导体封装装置3，不同之处在于，代替图3中所示的壳体12或除图3中所展示的壳体12之外，半导体装置5可使用支撑结构15a及透明板15b来实施。
支撑结构15a安置于衬底10的顶部表面101上且透明圆15b安置于支撑结构15a上。在一些实施例中，透明板15b为玻璃板。在一些实施例中，透明板15b经配置以允许传输自电子组件11a及11b发射或由所述电子组件接收的光(例如电子组件11a及11b经配置以发射或接收的光)。
图6A说明半导体封装装置的比较制造过程的一或多个操作。限定排气孔60h的衬底60附接于胶带65(或另一类型的黏合层)上。如图6A中所示，邻近排气孔60h或安置在排气孔60h周围的保护层63a的厚度小于导电衬垫62的厚度与覆盖导电衬垫62的保护层63b的厚度的总和，且因此在保护层63a与胶带65之间存在间隙。因此，污染物可经由保护层63a与胶带65之间的间隙进入排气孔60h而污染或损坏衬底60上的芯片或裸片。在一些实施例中，污染物可沿图6A及图6B中所示的箭头的方向进入排气孔60h，图6A及图6B说明根据比较过程的衬底60的仰视图。
图7说明根据本发明的一些实施例的半导体封装装置的制造过程的一或多个操作。图7中所示的半导体封装装置类似于图6A中所示的半导体封装装置，不同之处在于，图7中所示的半导体封装装置进一步包含金属结构62a(例如虚设衬垫或接地衬垫)，其安置在排气孔60h周围或包围排气孔60h，或位于排气孔60h的与安置有导电衬垫62的一侧相对的一侧上，以增加在排气孔60h周围的结构的总厚度。在此类实施中，在保护层63a与胶带65之间基本上不存在间隙，或保护层63a可直接接触胶带65，且保护层63a可在制造过程期间紧密地或气密地附接至胶带65，如此可防止污染物进入排气孔60h而污染或损伤衬底60上的芯片或裸片。
如本文中所使用，术语“近似地”、“基本上”、“基本”及“约”用以描述及解释小变化。当与事件或情形结合使用时，术语可指代事件或情形明确发生的情况以及事件或情形极近似于发生的情况。举例来说，当结合数值使用时，所述术语可指代小于或等于所述数值的±10％的变化范围，诸如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(诸如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，则可认为所述两个数值“基本上”相同。举例来说，“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围，诸如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的±10°的角度变化范围，诸如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的移位不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则可认为所述两个表面共面或基本上共面。如果两个点或轴线之间的移位不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则可认为所述两个点或轴线对准或基本上对准。如果表面的最高点与最低点之间的差不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则可认为所述表面是平面或基本上平面的。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”及“电导率”是指传送电流的能力。导电材料通常指示对电流流动呈现极小或零阻力的那些材料。电导率的一个量度为西门子每米(S/m)。通常，导电材料为具有近似大于104S/m(诸如至少105S/m或至少106S/m)的电导率的一种材料。材料的电导率有时可随温度变化。除非另外规定，否则材料的电导率是在室温下测量。
除非上下文另有明确规定，否则如本文所使用，单数术语“一(a/an)”及“所述”可包含复数个指代物。在一些实施例的描述中，提供在另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的状况以及一或多个介入组件位于前一组件与后一组件之间的状况。
尽管已参考本发明的具体实施例描述且说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内取代等效组件而不脱离如由所附权利要求书所限定的本发明的真实精神及范围。所述说明可不必按比例绘制。归因于制造过程中的变化等等，本发明中的艺术再现与实际设备之间可存在区别。可存在并未具体说明的本发明的其它实施例。应将本说明书及图式视为说明性而非限制性的。可作出修改，以使特定情形、材料、物质组成、方法或过程适应于本发明的目标、精神及范围。所有此类修改均既定在所附权利要求书的范围内。尽管已参考按特定次序执行的特定操作来描述本文中所揭示的方法，但可理解，在不脱离本发明的教示的情况下，可组合、细分，或重新排序这些操作以形成等效方法。因此，除非在本文中特定指示，否则操作的次序及分组并非本发明的限制。

Claims (29)

1.一种半导体封装装置，其包括：
衬底，其具有第一表面及与所述第一表面相对的第二表面，所述衬底限定穿透所述衬底的第一开口；
电子组件，其安置于所述衬底的所述第一表面上；
保护层，其安置于所述衬底的所述第二表面上，所述保护层包括邻近所述第一开口的第一部分及安置成比所述保护层的所述第一部分更远离所述第一开口的第二部分，所述保护层的所述第一部分具有背离所述衬底的所述第二表面的表面，所述保护层的所述第二部分具有背离所述衬底的所述第二表面的表面，
其中所述保护层的所述第一部分的所述表面与所述衬底的所述第二表面之间的距离大于所述保护层的所述第二部分的所述表面与所述衬底的所述第二表面之间的距离。
2.根据权利要求1所述的半导体封装装置，其进一步包括安置于所述衬底的所述第二表面上的导电衬垫，其中所述保护层进一步包含第三部分，所述第三部分覆盖所述导电衬垫的一部分且具有背离所述衬底的所述第二表面的表面，且其中所述保护层的所述第一部分的所述表面与所述衬底的所述第二表面之间的所述距离实质上等于或大于所述保护层的所述第三部分的所述表面与所述衬底的所述第二表面之间的距离。
3.根据权利要求2所述的半导体封装装置，其中所述保护层与所述导电衬垫共形。
4.根据权利要求1所述的半导体封装装置，其进一步包括安置于所述衬底的所述第二表面上且由所述保护层的所述第一部分覆盖的金属结构。
5.根据权利要求4所述的半导体封装装置，其中所述金属结构包括虚设衬垫或接地衬垫。
6.根据权利要求4所述的半导体封装装置，其中所述金属结构包围所述第一开口。
7.根据权利要求1所述的半导体封装装置，其进一步包括安置于所述衬底的所述第一表面上且覆盖所述电子组件的壳体。
8.根据权利要求1所述的半导体封装装置，其中所述保护层包含感光材料。
9.根据权利要求1所述的半导体封装装置，其中所述保护层沿所述衬底的所述第二表面延伸且突出超过所述第一开口的边缘以限定第二开口。
10.根据权利要求9所述的半导体封装装置，其中所述第一开口的宽度大于所述第二开口的宽度。
11.根据权利要求1所述的半导体封装装置，其进一步包括安置于所述衬底与所述电子组件之间的托架，其中所述托架限定与所述衬底的所述第一开口实质上对准的排气孔。
12.根据权利要求11所述的半导体封装装置，其进一步包括包围所述第一开口及所述排气孔的密封元件。
13.一种半导体封装装置，其包括
衬底，其具有第一表面及与所述第一表面相对的第二表面，所述衬底限定穿透所述衬底的第一开口；
电子组件，其安置于所述衬底的所述第一表面上；
金属结构，其安置于所述衬底的所述第二表面上且邻近所述第一开口；及
保护层，其包括覆盖所述衬底的所述第二表面的第一部分及覆盖所述金属结构的第二部分。
14.根据权利要求13所述的半导体封装装置，其中所述保护层的所述第一部分的厚度实质上与所述保护层的所述第二部分的厚度相同。
15.根据权利要求13所述的半导体封装装置，其中所述保护层的所述第二部分的表面与所述衬底的所述第二表面之间的距离大于所述保护层的所述第一部分的表面与所述衬底的所述第二表面之间的距离。
16.根据权利要求13所述的半导体封装装置，其进一步包括安置于所述衬底的所述第二表面上且比所述金属结构更远离所述第一开口的导电衬垫，所述导电衬垫与所述金属结构间隔开，其中所述保护层包括覆盖所述导电衬垫的一部分的第三部分。
17.根据权利要求16所述的半导体封装装置，其中所述保护层与所述金属结构及所述导电衬垫共形。
18.根据权利要求13所述的半导体封装装置，其中所述金属结构包围所述第一开口。
19.根据权利要求13所述的半导体封装装置，其中所述金属结构包括虚设衬垫或接地衬垫。
20.根据权利要求13所述的半导体封装装置，其进一步包括安置于所述衬底的所述第一表面上且覆盖所述电子组件的壳体。
21.根据权利要求13所述的半导体封装装置，其中所述保护层包含感光材料。
22.根据权利要求13所述的半导体封装装置，其中所述保护层沿所述衬底的所述第二表面延伸且突出超过所述第一开口的边缘以限定第二开口。
23.根据权利要求22所述的半导体封装装置，其中所述第一开口通过机械钻孔形成且所述第二开口通过微影技术形成。
24.根据权利要求13所述的半导体封装装置，其进一步包括安置于所述衬底与所述电子组件之间的托架，其中所述托架限定与所述衬底的所述第一开口实质上对准的排气孔。
25.根据权利要求24所述的半导体封装装置，其进一步包括包围所述第一开口及所述排气孔的密封元件。
26.一种半导体封装装置，其包括
衬底，其具有第一表面及与所述第一表面相对的第二表面，所述衬底限定穿透所述衬底的第一开口；
电子组件，其安置于所述衬底的所述第一表面上；
金属结构，其安置于所述衬底的所述第二表面上；及
保护层，其覆盖所述金属结构且沿所述衬底的所述第二表面延伸以限定在所述第一开口下方的第二开口。
27.根据权利要求26所述的半导体封装装置，其中所述第一开口通过机械钻孔形成且所述第二开口通过微影技术形成。
28.根据权利要求26所述的半导体封装装置，其中所述第一开口的宽度大于所述第二开口的宽度。
29.根据权利要求26所述的半导体封装装置，其中所述保护层包含感光材料。
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