TWI698983B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI698983B
TWI698983B TW108107234A TW108107234A TWI698983B TW I698983 B TWI698983 B TW I698983B TW 108107234 A TW108107234 A TW 108107234A TW 108107234 A TW108107234 A TW 108107234A TW I698983 B TWI698983 B TW I698983B
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semiconductor wafer
terminal
semiconductor
adhesive resin
semiconductor device
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TW108107234A
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TW202013690A (zh
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赤田裕亮
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種能夠實現小型、薄型化之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置具備：基板，其於第1面具有第1端子；及第1半導體晶片，其設置於第1面，且具有第2端子。第1半導體晶片在相對於第1面平行之方向上離開接著性樹脂而設置。又，該半導體裝置具備將第1端子與第2端子電性連接之第1連接材。第1連接材之一部分埋入至接著性樹脂中。進而，該半導體裝置具備設置於基板之第1面之第2半導體晶片及設置於第2半導體晶片與第1面之間之接著性樹脂。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施形態係關於一種半導體裝置及半導體裝置之製造方法。
近年，隨著通信技術及資訊處理技術之發達，業界要求半導體裝置之小型、薄型化。例如，於NAND(Not AND，反及)型快閃記憶體等半導體裝置中，就小型、薄型化之觀點而言有於同一個配線基板積層控制器晶片與記憶體晶片之三維安裝結構。作為三維結構，例如已知利用晶粒接合膜(Die Attach Film：DAF)等接著性樹脂覆蓋控制器晶片並於接著性樹脂上積層記憶體晶片之結構(Film On Die：FOD)或使用矽間隔物積層記憶體晶片之結構等。
本說明書中記載之實施形態提供一種能夠實現小型、薄型化之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置具備：基板，其於第1面具有第1端子；及第1半導體晶片，其設置於第1面，且具有第2端子。第1半導體晶片在相對於第1面平行之方向上離開接著性樹脂而設置。又，該半導體裝置具備將第1端子與第2端子電性連接之第1連接材。第1連接材之一部分埋入至接著性樹脂中。進而，該半導體裝置具備設置於基板之第1面之第2半導體晶片及設置於第2半導體晶片與第1面之間之接著性樹脂。
100:半導體裝置
102:基板
104:第1面
106:第2面
108:第1端子
108a:第1端子
108b:第1端子
110:第1半導體晶片
110a:第1半導體晶片側邊
110b:第1半導體晶片側邊
112:第2端子
114:第1連接材
116、117:頂部
118:接著性樹脂
120:接著性樹脂
122、123:間隙
124:第2半導體晶片
124a:第2半導體晶片側邊
126:第2半導體晶片
126a:第2半導體晶片側邊
128:第2半導體晶片
128a:第2半導體晶片側邊
130:第2半導體晶片
130a:第2半導體晶片側邊
132:第2半導體晶片
132a:第2半導體晶片側邊
134:第2半導體晶片
134a:第2半導體晶片側邊
136:第2半導體晶片
136a:第2半導體晶片側邊
138:第2半導體晶片
138a:第2半導體晶片側邊
156:第3端子
158:第3端子
160:第4端子
162:第4端子
164:第4端子
166:第4端子
168:第4端子
170:第4端子
172:第4端子
174:第4端子
176:第2連接材
178:第2連接材
180:第2連接材
182:第2連接材
184:第2連接材
186:第2連接材
188:第2連接材
190:第2連接材
192:塑模樹脂
圖1係第1實施形態之半導體裝置之概略性俯視圖。
圖2係該半導體裝置之概略性側視圖。
圖3係表示該半導體裝置之製造方法之流程圖。
圖4係表示該半導體裝置之製造方法之概略性俯視圖。
圖5係表示該半導體裝置之製造方法之概略性俯視圖。
圖6係表示該半導體裝置之製造方法之概略性俯視圖。
圖7係表示該半導體裝置之製造方法之概略性俯視圖。
圖8係表示該半導體裝置之製造方法之概略性俯視圖。
圖9係表示該半導體裝置之製造方法之概略性俯視圖。
圖10係表示該半導體裝置之晶圓加工之過程之流程圖。
圖11係第2實施形態之半導體裝置之概略性俯視圖。
圖12係該半導體裝置之概略性側視圖。
以下，參照圖式對實施形態之半導體裝置進行說明。又，圖式係模式圖，存在例如厚度與平面尺寸之關係、各層厚度之比率等與實物不同之情形。又，於實施形態中，對實質上相同之構成要素附上相同之符號，並省略說明。
(第1實施形態)
參照圖1及圖2，對第1實施形態之半導體裝置100之構成進行說明。圖1係半導體裝置100之概略性俯視圖，圖2所示之側視圖係從圖1所示之 箭頭A之方向觀察半導體裝置100時之側視圖。將大致垂直於箭頭A之方向設為箭頭B。又，將箭頭A之方向設為第1方向，將箭頭B之方向設為第2方向。
第1實施形態之半導體裝置100具備：基板102、第1半導體晶片110、第1連接材114、接著性樹脂118、120、及第2半導體晶片124、126、128、130、132、134、136、138。又，該等構成由塑模樹脂192掩埋。再者，於圖1中，為了進行說明，省略塑模樹脂192進行圖示。
於基板102之內部形成有未圖示之配線層，將第1面104與第2面106之間電性連接。於基板102之第2面106，形成有未圖示之作為外部連接端子之凸塊，能夠將半導體裝置100與外部電性連接。
將從第2面106朝向第1面104之方向設為上方向，將其相反方向設為下方向。
基板102為大致四邊形之板狀。
於基板102之第1面104，設置與下述之第1半導體晶片110電性連接之第1端子108。
第1端子108以沿著第1半導體晶片110之外形之方式設置。
第1端子108具有沿著第1方向排列之第1端子108a與第1端子108b。
第1端子108a位於沿著第2方向為基板102之近前側，第1端子108b位於沿著第2方向為基板102之裡側。
第1端子108係使用銅、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
於基板102之第1面104，設置有與下述之第2半導體晶片 124、126、128、130電性連接之第3端子156、及與下述之第2半導體晶片132、134、136、138電性連接之第3端子158。
第3端子156沿著第1方向排列。
第3端子156位於沿著第2方向較第1端子108a更靠基板102之近前側。
第3端子156係使用銅、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第3端子158沿著第1方向排列。
第3端子158位於沿著第2方向較第1端子108b更靠基板102之裡側。
第3端子158係使用銅、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第1端子108、第3端子156、及第3端子158從基板102之第1面104通過內部之配線層電性連接至設置於第2面106之焊墊。
第1半導體晶片110例如係半導體記憶裝置之控制器晶片、介面晶片等。
第1半導體晶片110為大致四邊形之板狀，且以被基板102之第1面104之第1端子108包圍之方式設置。
未圖示之接著性樹脂設置於第1半導體晶片110與基板102之間。
第1半導體晶片110利用該接著性樹脂固定於基板102。
於第1半導體晶片110之表面之外周部，第2端子112設置於對應於第1端子108之位置上。
第2端子112係使用鋁、銅、鋁及銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第1連接材114係電氣導電性之弧狀接合線，將第2端子112與對應之第1端子108電性連接。
第1連接材114之弧狀之最高頂部116、117從上方觀察時，位於較第1半導體晶片110之外周更靠內側。
作為第1連接材114，使用線徑為25μm左右之金屬線(例如，金線(Au)或銅線(Cu))。
接著性樹脂118、120以下表面與基板102之第1面104直接接觸之方式設置。
接著性樹脂118、120具有：接著性樹脂118，設置於沿著第2方向較第1半導體晶片110更為近前側之第1位置上；及接著性樹脂120，設置於較第1半導體晶片110更為裡側之第2位置上。
接著性樹脂118為四邊形之板狀，以最靠近第1半導體晶片110之一邊118a與第1半導體晶片110之一邊110a大致平行之方式設置。
接著性樹脂120為四邊形之板狀，以最靠近第1半導體晶片110之一邊120a與第1半導體晶片110之一邊110b大致平行之方式設置。
接著性樹脂118、120以與第1半導體晶片110之間形成間隙122、123之方式設置。只要能夠由塑模樹脂192掩埋，間隙122、123之大小較佳為較小。由於存在未能由塑模樹脂192掩埋之可能性，因此間隙122、123之大小較佳為20μm以上。
接著性樹脂118、120例如係厚度60μm左右之DAF，與第1半導體晶片110大致相同或厚10~20μm左右，或者亦可較第1半導體晶片 110薄。
於第1實施形態中，表示了接著性樹脂118、120之厚度與至頂部116、117之高度相比較薄之情形。又，接著性樹脂118、120之厚度與至頂部116、117之高度相比可較厚亦可較薄。
接著性樹脂118覆蓋第1端子108a之全部，並掩埋第1連接材114之一部分。接著性樹脂118以與一邊118a對向之邊118b位於與第3端子156相比沿著第2方向更為裡側之方式設置。
接著性樹脂120覆蓋第1端子108b之全部，並掩埋第1連接材114之一部分。接著性樹脂120以與一邊120a對向之邊120b位於與第3端子158相比沿著第2方向更為近前側之方式設置。
於第1實施形態中，表示了頂部116、117未由接著性樹脂118、120掩埋之情形。又，頂部116、117可由接著性樹脂118、120掩埋，亦可不由接著性樹脂118、120掩埋。
第2半導體晶片124係具有例如NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片124為大致四邊形之板狀。
第2半導體晶片124以從上方觀察時之外形與接著性樹脂118大致相同之方式，且以接觸接著性樹脂118之上表面之方式設置。
第2半導體晶片124於一邊124a側之外周部設置沿著第1方向排列之第4端子160。
第4端子160係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片126係具有例如NAND型快閃記憶體等記憶 元件之記憶體晶片等。
第2半導體晶片126為大致四邊形之板狀。
第2半導體晶片126設置於第2半導體晶片124之上。
於第2半導體晶片126與第2半導體晶片124之間設置未圖示之接著性樹脂，第2半導體晶片126利用該接著性樹脂固定於第2半導體晶片124。
第2半導體晶片126以不覆蓋第4端子160之方式，相對於第2半導體晶片124向第2方向側錯開設置。
即，第2半導體晶片124與第2半導體晶片126呈階梯狀。
第2半導體晶片126於一邊126a側之外周部設置沿著第1方向排列之第4端子162。
第4端子162係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片128例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片128為大致四邊形之板狀。
第2半導體晶片128設置於第2半導體晶片126之上。
於第2半導體晶片128與第2半導體晶片126之間設置未圖示之接著性樹脂，第2半導體晶片128利用該接著性樹脂固定於第2半導體晶片126。
第2半導體晶片128以不覆蓋第4端子162之方式，相對於第2半導體晶片126向第2方向側錯開設置。
即，第2半導體晶片126與第2半導體晶片128呈階梯狀。
第2半導體晶片128於一邊128a側之外周部設置沿著第1方向排列之第4端子164。
第4端子164係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片130例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片130為大致四邊形之板狀。
第2半導體晶片130設置於第2半導體晶片128之上。
於第2半導體晶片130與第2半導體晶片128之間設置未圖示之接著性樹脂，第2半導體晶片130利用該接著性樹脂固定於第2半導體晶片128。
第2半導體晶片130以不覆蓋第4端子164之方式，相對於第2半導體晶片128向第2方向側錯開設置。此時，第2半導體晶片130以從上方觀察時與第2端子112重疊之方式設置。
即，第2半導體晶片128與第2半導體晶片130呈階梯狀。
第2半導體晶片130於一邊130a側之外周部設置沿著第1方向排列之第4端子166。
第4端子166係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片132例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片132為大致四邊形之板狀。
第2半導體晶片132以從上方觀察時之外形與接著性樹脂 120大致相同之方式，且以接觸接著性樹脂120之上表面之方式設置。
第2半導體晶片132於一邊132a側之外周部設置沿著第1方向排列之第4端子168。
第4端子168係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片134例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片134為大致四邊形之板狀。
第2半導體晶片134設置於第2半導體晶片132之上。
於第2半導體晶片134與第2半導體晶片132之間設置未圖示之接著性樹脂，第2半導體晶片134利用該接著性樹脂固定於第2半導體晶片132。
第2半導體晶片134以不覆蓋第4端子168之方式，相對於第2半導體晶片132向第2方向之相反側錯開設置。
即，第2半導體晶片132與第2半導體晶片134呈階梯狀。
第2半導體晶片134於一邊134a側之外周部設置沿著第1方向排列之第4端子170。
第4端子170係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片136例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片136為大致四邊形之板狀。
第2半導體晶片136設置於第2半導體晶片134之上。
於第2半導體晶片136與第2半導體晶片134之間設置未圖示之接著性樹脂，第2半導體晶片136利用該接著性樹脂固定於第2半導體晶片134。
第2半導體晶片136以不覆蓋第4端子170之方式，相對於第2半導體晶片134向第2方向之相反側錯開設置。
即，第2半導體晶片134與第2半導體晶片136呈階梯狀。
第2半導體晶片136於一邊136a側之外周部設置沿著第1方向排列之第4端子172。
第4端子172係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片138例如係具有NAND型快閃記憶體等記憶元件之記憶體晶片等。
第2半導體晶片138為大致四邊形之板狀。
第2半導體晶片138設置於第2半導體晶片136之上。
於第2半導體晶片138與第2半導體晶片136之間設置未圖示之接著性樹脂，第2半導體晶片138利用該接著性樹脂固定於第2半導體晶片136。
第2半導體晶片138以不覆蓋第4端子172之方式，相對於第2半導體晶片136向第2方向之相反側錯開設置。此時，第2半導體晶片138以從上方觀察時與第2端子112重疊之方式設置。
即，第2半導體晶片136與第2半導體晶片138呈階梯狀。
第2半導體晶片138於一邊138a側之外周部設置沿著第1方向排列之第4端子174。
第4端子174係使用鋁、銅、鋁與銅之合金、金等金屬並利用印刷、蒸鍍、濺鍍、鍍覆等方法形成。
第2半導體晶片124、126、128、130、132、134、136、138可具備記憶胞及解碼器等。於使用記憶體晶片作為第2半導體晶片124、126、128、130、132、134、136、138之情形時，可將控制器用於第1半導體晶片110以控制針對記憶體晶片之資料之寫入及讀出。
第2連接材176、178、180、182、184、186、188、190係電氣導電性之弧狀接合線，將第3端子156與第4端子160、162、164、166、及第3端子158與第4端子168、170、172、174電性連接。作為第2連接材176、178、180、182、184、186、188、190，使用線徑為25μm左右之金屬線(例如，金線(Au)或銅線(Cu))。
第2連接材176將第3端子156與第4端子160電性連接。
第2連接材178將第4端子160與第4端子162電性連接。
第2連接材180將第4端子162與第4端子164電性連接。
第2連接材182將第4端子164與第4端子166電性連接。
第2連接材184將第3端子158與第4端子168電性連接。
第2連接材186將第4端子168與第4端子170電性連接。
第2連接材188將第4端子170與第4端子172電性連接。
第2連接材190將第4端子172與第4端子174電性連接。
塑模樹脂192以密封基板102、第1半導體晶片110、接著性樹脂118、120、第2半導體晶片124、126、128、130、132、134、136、138之周圍之方式設置。
(第1實施形態之半導體裝置之效果)
作為第1比較例，對例如接著性樹脂之一部分以覆蓋第1半導體晶片110之方式設置之情形進行說明。於此種情形時，接著性樹脂膨脹出第1半導體晶片110之厚度。於其上積層第2半導體晶片124、132等之情形時，若為較薄之接著性樹脂，則會因膨脹過厚而無法順利地積層。因此，需要使用120~135μm左右且較第1半導體晶片110足夠厚之接著性樹脂，進而於接著性樹脂之上表面設置使用了矽(Si)等之間隔物以使其平坦化。於此種情形時，無法將半導體裝置薄型化，且間隔物之成本亦成為負擔。
作為第2比較例，對例如接著性樹脂以未覆蓋第1連接材114之一部分之方式設置於沿著第2方向更遠離第1端子108之位置上之情形進行說明。於此種情形時，雖能夠於厚度方向上小型化，但於沿著第2方向之方向上無法小型化。
於本實施形態中，接著性樹脂118、120之厚度可與第1半導體晶片110大致相同或厚10~20μm左右，或者較第1半導體晶片110薄，以於與第1半導體晶片110之間形成間隙122、123，且覆蓋第1連接材114之一部分之方式設置。
因此，根據本實施形態之半導體裝置100，與第1比較例相比，能夠將半導體裝置100薄型化相當於間隔物之厚度與因使用厚度較薄之接著性樹脂所相差之厚度之程度。進而，能夠抑制間隔物之相應費用。
因此，根據本實施形態之半導體裝置100，與第2比較例相比，使接著性樹脂118、120接近第1半導體晶片110，能夠於沿著第2方向之方向上小型化。
又，若接著性樹脂118、120不斷變厚，則能夠在第2半導 體晶片124、132之下表面依舊不接觸第1連接材114之情況下，而使第2半導體晶片124、132接近第1半導體晶片110。接著性樹脂118、120之厚度較合適為與第1半導體晶片110之厚度大致相同或厚10~20μm左右，但並不限定於此，亦可較第1半導體晶片110薄。於此情形時，更適合於薄型化。
[第1實施形態之半導體裝置之製造方法]
其次，參照圖3至圖10，對第1實施形態之半導體裝置100之製造方法進行說明。圖3係用以表示半導體裝置100之製造方法之流程圖。圖4至圖9係用以表示本實施形態之半導體裝置100之製造方法之概略性俯視圖。圖10係表示半導體裝置100之晶圓加工過程之流程圖。
(步驟S101：準備基板之步驟)
如圖3及圖4所示，準備於內部形成配線且具有第1端子108與第3端子156、158之基板102。
(步驟S102：將第1半導體晶片配置於基板之步驟)
如圖3及圖5所示，於基板102之第1面104配置第1半導體晶片110並利用未圖示之接著性樹脂貼附。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於基板102之第1面104。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第1半導體晶片110固定於基板102之第1面104。
(步驟S103：將基板與第1半導體晶片電性連接之步驟)
如圖3及圖6所示，利用第1連接材114將第1半導體晶片110之第2端子112與基板102之第1端子108之間電性連接。此時，以第1連接材114之弧狀之最高頂部116、117從上方觀察時位於較第1半導體晶片110之外周更為內側之方式連接。
(步驟S104：準備第2半導體晶片之步驟)
如圖3及圖10所示，貼附有接著性樹脂118、120之第2半導體晶片124、132利用以下之步驟來製作。首先，於晶圓正面貼附用以保護元件面之保護膠帶(S201)。其次，利用磨石研磨晶圓背面，使晶圓變薄(S202)。在此之後，將經薄化之晶圓貼附於帶有接著性樹脂118、120之切割膠帶(S203)。其後，剝離保護膠帶(S204)。進而，利用刀片切割帶有接著性樹脂118、120之晶圓(S205)。經過此種步驟，能夠準備複數個從上方觀察時之外形與接著性樹脂大致相同之第2半導體晶片(S206)。
(步驟S105：將接著性樹脂設置於基板之步驟)
如圖3及圖7所示，將設置有第2半導體晶片124之接著性樹脂118與設置有第2半導體晶片132之接著性樹脂120以掩埋第1連接材114之一部分之方式貼附於基板102之第1面104。此時，第2半導體晶片124、132與第1連接材114以不相互接觸之方式配置。於第1實施形態中，表示了頂部116、117未由接著性樹脂118、120掩埋之情形。
(步驟S106：積層第2半導體晶片之步驟)
如圖3及圖8所示，於貼附有接著性樹脂118之第2半導體晶片124之上 表面介隔未圖示之接著性樹脂積層第2半導體晶片126、128、130。又，於貼附有接著性樹脂120之第2半導體晶片132之上表面介隔未圖示之接著性樹脂積層第2半導體晶片134、136、138。
(步驟S106：積層第2半導體晶片126之步驟)
第2半導體晶片126設置於第2半導體晶片124之上。
如圖3及圖8所示，第2半導體晶片126以不覆蓋第4端子160之方式，相對於第2半導體晶片124向第2方向側錯開設置。
於第2半導體晶片126與第2半導體晶片124之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片124。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片126利用該接著性樹脂固定於第2半導體晶片124。
即，第2半導體晶片124與第2半導體晶片126呈階梯狀。
(步驟S106：積層第2半導體晶片128之步驟)
第2半導體晶片128設置於第2半導體晶片126之上。
第2半導體晶片128以不覆蓋第4端子162之方式，相對於第2半導體晶片126向第2方向側錯開設置。
於第2半導體晶片128與第2半導體晶片126之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片126。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片128利用該接著性樹脂固定於第2半導體晶片126。
即，第2半導體晶片126與第2半導體晶片128呈階梯狀。
(步驟S106：積層第2半導體晶片130之步驟)
第2半導體晶片130設置於第2半導體晶片128之上。
第2半導體晶片130以不覆蓋第4端子164之方式，相對於第2半導體晶片128向第2方向側錯開設置。此時，第2半導體晶片130以從上方觀察時與第2端子112重疊之方式設置。
於第2半導體晶片130與第2半導體晶片128之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片128。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片130利用該接著性樹脂固定於第2半導體晶片128。
即，第2半導體晶片128與第2半導體晶片130呈階梯狀。
(步驟S106：積層第2半導體晶片134之步驟)
第2半導體晶片134設置於第2半導體晶片132之上。
第2半導體晶片134以不覆蓋第4端子168之方式，相對於第2半導體晶片132向第2方向之相反側錯開設置。
於第2半導體晶片134與第2半導體晶片132之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片132。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片134利用該接著性樹脂固定於第2半導體晶片132。
即，第2半導體晶片132與第2半導體晶片134呈階梯狀。
(步驟S106：積層第2半導體晶片136之步驟)
第2半導體晶片136設置於第2半導體晶片134之上。
第2半導體晶片136以不覆蓋第4端子170之方式，相對於第2半導體晶片134向第2方向之相反側錯開設置。
於第2半導體晶片136與第2半導體晶片134之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片134。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片136利用該接著性樹脂固定於第2半導體晶片134。
即，第2半導體晶片134與第2半導體晶片136呈階梯狀。
(步驟S106：積層第2半導體晶片138之步驟)
第2半導體晶片138設置於第2半導體晶片136之上。
第2半導體晶片138以不覆蓋第4端子172之方式，相對於第2半導體晶片136向第2方向之相反側錯開設置。此時，第2半導體晶片138以從上觀察時與第2端子112重疊之方式設置。
於第2半導體晶片138與第2半導體晶片136之間設置未圖示之接著性樹脂。此時，該接著性樹脂於因加熱而黏度降低之狀態下貼附於第2半導體晶片136。其後，該接著性樹脂因冷卻而恢復原來之黏度，因此第2半導體晶片138利用該接著性樹脂固定於第2半導體晶片136。
即，第2半導體晶片136與第2半導體晶片138呈階梯狀。
(步驟S107：將基板與第2半導體晶片電性連接之步驟)
如圖3及圖9所示，使用第2連接材176、178、180、182、184、186、188、190將基板102與第2半導體晶片124、126、128、130、132、 134、136、138電性連接。
第2連接材176將第3端子156與第4端子160電性連接。
第2連接材178將第4端子160與第4端子162電性連接。
第2連接材180將第4端子162與第4端子164電性連接。
第2連接材182將第4端子164與第4端子166電性連接。
第2連接材184將第3端子158與第4端子168電性連接。
第2連接材186將第4端子168與第4端子170電性連接。
第2連接材188將第4端子170與第4端子172電性連接。
第2連接材190將第4端子172與第4端子174電性連接。
(步驟S108：利用塑模樹脂密封構成整體之步驟)
其次，使用因加熱而黏度降低之塑模樹脂192掩埋該構成整體。進而，藉由冷卻整個該構成，使被埋入之塑模樹脂192固化。塑模樹脂192係利用環氧樹脂等絕緣樹脂以傳遞模塑法、壓縮模塑法、注射模塑法等模塑法形成。利用以上之步驟，如圖1及圖2所示，製造本實施形態之半導體裝置100。
(第1實施形態之半導體裝置之製造方法之效果)
於本實施形態之製造方法中，由於並無貼附間隔物之步驟，故而與第1實施形態之半導體裝置之效果中之第1比較例相比能夠抑制費用。
又，由於能夠將接著性樹脂與半導體晶片加工為相同大小，故而操作較為容易。
進而，一面提高溫度，一面設為低黏度地，用接著性樹脂 及塑模樹脂來掩埋連接材，故而於製造過程中，能夠避免連接材脫落、彎曲等破損之情形。
(第2實施形態)
第2實施形態之半導體裝置200基本上與第1實施形態之半導體裝置100大致同樣地構成，但第1連接材214之弧狀之最高頂部216、217從上方觀察時位於較第1半導體晶片110之外周更為外側，且由接著性樹脂218、220掩埋，於此點上不同。
參照圖11及圖12，對第2實施形態之半導體裝置200之構成進行說明。圖11係第2實施形態之半導體裝置200之概略性俯視圖，圖12所示之側視圖係從圖11所示之箭頭A之方向觀察半導體裝置200時之側視圖。
第1連接材214之弧狀之最高頂部216、217從上方觀察時位於較第1半導體晶片110之外周更為外側，且由接著性樹脂218、220掩埋。
第1連接材214以不與第2半導體晶片124、132相互接觸之方式配置。
接著性樹脂218、220例如係厚度60μm左右之DAF，且較第1半導體晶片110厚10~20μm左右。
於第2實施形態中，表示了接著性樹脂218、220之厚度與至頂部216、217之高度相比較厚之情形。
接著性樹脂218、220以於與第1半導體晶片110之間形成間隙222、223之方式設置。只要能夠由塑模樹脂192掩埋，間隙222、223之 大小較佳為較小。由於存在未能由塑模樹脂192掩埋之可能性，因此間隙222、223之大小較佳為20μm以上。
第2實施形態之半導體裝置之製造方法與第1實施形態實質上相同。
(第2實施形態之半導體裝置之效果)
於本實施形態中，頂部216、217從上方觀察時位於較第1半導體晶片110之外周更為外側，且由接著性樹脂218、220掩埋。
因此，於將接著性樹脂218、220沿著第2方向更靠近第1半導體晶片110配置時，並無第1連接材214與第2半導體晶片124、132接觸之虞。即，能夠將間隙222、223之大小減小至極限。
又，與第1實施形態之半導體裝置之效果中之第2比較例相比，能夠沿著第2方向將第1連接材214埋入至接著性樹脂218、220，相應地將半導體裝置200小型、薄型化。
又，接著性樹脂218、220之厚度較適合為與包含至頂部216、217之厚度大致相同，或厚10~20μm左右。又，接著性樹脂218、220之厚度較第1半導體晶片110之厚度更厚。
(其他實施形態)
於第1實施形態及第2實施形態之圖1至圖12中，圖示了積層4個第2半導體晶片之例，但第2半導體晶片之積層數並不限定於此。
又，於第1實施形態及第2實施形態之圖1至圖12中，圖示了僅積層第2半導體晶片之例，但積層結構並不限定於此。例如，亦可於 積層之第2半導體晶片間介隔接著性樹脂或間隔物而積層。
進而，雖圖示了於沿著第2方向較第1半導體晶片更為近前側與裡側設置兩個接著性樹脂之例，但亦可僅設置於單側。
接著性樹脂之厚度與至第1連接材頂部之高度相比可較厚亦可較薄。又，頂部可由接著性樹脂掩埋，亦可不由接著性樹脂掩埋。
於第1實施形態及第2實施形態之圖1至圖12中，圖示了所有第2連接材連接於下一層之第2半導體晶片或基板之例，但第2連接材之連接方法並不限定於此，例如第2連接材從各層直接連接至基板，或跳過一層連接等。
雖然說明瞭本發明之若干實施形態，但該等實施形態係作為例而提出，並未意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，且能夠於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變化包含於發明之範圍及主旨內，並且包含於申請專利範圍中記載之發明及其均等之範圍內。
[相關申請案]
本申請案享有將日本專利申請案2018-184646號(申請日：2018年9月28日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
100:半導體裝置
102:基板
108:第1端子
108a:第1端子
108b:第1端子
110:第1半導體晶片
110a:第1半導體晶片側邊
110b:第1半導體晶片側邊
112:第2端子
114:第1連接材
124:第2半導體晶片
124a:第2半導體晶片側邊
126:第2半導體晶片
126a:第2半導體晶片側邊
128:第2半導體晶片
128a:第2半導體晶片側邊
130:第2半導體晶片
130a:第2半導體晶片側邊
132:第2半導體晶片
132a:第2半導體晶片側邊
134:第2半導體晶片
134a:第2半導體晶片側邊
136:第2半導體晶片
136a:第2半導體晶片側邊
138:第2半導體晶片
138a:第2半導體晶片側邊
156:第3端子
158:第3端子
160:第4端子
162:第4端子
164:第4端子
166:第4端子
168:第4端子
170:第4端子
172:第4端子
174:第4端子
176:第2連接材
178:第2連接材
180:第2連接材
182:第2連接材
184:第2連接材
186:第2連接材
188:第2連接材
190:第2連接材

Claims (10)

  1. 一種半導體裝置，其具備：基板，其於第1面具有第1端子；第1半導體晶片，其設置於上述第1面，且具有第2端子；第1連接材，其將上述第1端子與上述第2端子電性連接；第2半導體晶片，其設置於上述基板之上述第1面；及接著性樹脂，其設置於上述第2半導體晶片與上述第1面之間；上述第1連接材之一部分埋入上述接著性樹脂中，上述第1半導體晶片在相對於上述第1面平行之方向上離開上述接著性樹脂而設置。
  2. 一種半導體裝置，其具備：基板，其於第1面具有第1端子；第1半導體晶片，其設置於上述第1面，且具有第2端子；第1連接材，其將上述第1端子與上述第2端子電性連接；第2半導體晶片，其設置於上述基板之上述第1面；及接著性樹脂，其設置於上述第2半導體晶片與上述第1面之間；上述接著性樹脂係掩埋上述第1連接材之一部分，且從相對於上述第1面平行之方向觀察時，於較上述第1半導體晶片更為近前側之第1位置與較上述第1半導體晶片更為裡側之第2位置上離開上述第1半導體晶片而設置。
  3. 如請求項1或2之半導體裝置，其中於上述接著性樹脂之上呈階梯狀 地積層複數個上述第2半導體晶片。
  4. 如請求項1或2之半導體裝置，其中上述接著性樹脂直接接觸上述第1面。
  5. 如請求項1或2之半導體裝置，其中上述第2半導體晶片從上方觀察時之外形與上述接著性樹脂大致相同。
  6. 如請求項1或2之半導體裝置，其中上述複數個第2半導體晶片中最上方之第2半導體晶片從上方觀察時與上述第2端子重疊。
  7. 如請求項1或2之半導體裝置，其中上述基板為配線基板。
  8. 如請求項1或2之半導體裝置，其進而包含塑模樹脂，該塑模樹脂於上述第1面、上述第1半導體晶片、上述第2半導體晶片、上述接著性樹脂及上述第1連接材中，密封除埋入至上述接著性樹脂之部分以外之周圍。
  9. 一種半導體裝置之製造方法，於第1面具有第1端子之基板之上述第1面，配置具有第2端子之第1半導體晶片；使用第1連接材將上述基板之上述第1端子與上述第1半導體晶片之上述第2端子電性連接；並且將第2半導體晶片所貼附之接著性樹脂以掩埋上述第1連接材之一部 分之方式設置於上述基板之上述第1面。
  10. 如請求項9之半導體裝置之製造方法，其中以將貼附有上述接著性樹脂之晶圓分割為各個上述第2半導體晶片之方式，準備從上方觀察時之外形與上述接著性樹脂大致相同之上述第2半導體晶片。
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