CN111048468B - 电子元件的层叠件及其制造方法 - Google Patents

电子元件的层叠件及其制造方法 Download PDF

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Publication number
CN111048468B
CN111048468B CN201910962486.XA CN201910962486A CN111048468B CN 111048468 B CN111048468 B CN 111048468B CN 201910962486 A CN201910962486 A CN 201910962486A CN 111048468 B CN111048468 B CN 111048468B
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electronic component
laminate
layer
electronic components
electronic
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CN111048468A (zh
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广田洋平
山崎宽史
岩间齐
高桥祐介
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TDK Corp
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TDK Corp
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Abstract

一种电子元件的层叠件,包括:第一电子元件,其具有第一表面、与第一表面相对的第二表面以及位于第一表面和第二表面之间的侧面;第二电子元件,其具有第三表面,所述第一电子元件安装在所述第三表面上,所述第三表面面对所述第二表面,并且在所述第三表面和所述侧面之间形成角部;粘接层,用于将第一电子元件结合到第二电子元件,其中粘接层具有位于第二表面和第三表面之间的第一部分和填充角部的弯曲的第二部分;以及导电层,其在所述侧面的一侧上延伸,沿所述第二部分弯曲并延伸到所述第三表面。

Description

电子元件的层叠件及其制造方法
本申请基于2018年10月12日提交的JP申请号2018-193174,并要求其优先权,其公开内容通过引用整体并入本文。
技术领域
本发明涉及一种电子元件的层叠件(stack)及其制造方法,尤其涉及一种其中堆叠了ASIC(专用集成电路)和磁传感器的电子元件的层叠件。
背景技术
已知一种技术,其中通过将诸如集成电路、半导体元件、MEMS和磁传感器的电子元件安装在另一电子元件上来形成封装。美国专利9466580公开了一种半导体封装,其中半导体模具(die)(在下文中称为第一电子元件)安装在另一导体模具(die)(在下文中称为第二电子元件)上。形成在第一电子元件的上表面上的焊盘经由导电层(再分布层)连接到形成在第二电子元件的上表面(安装第一电子元件的表面)上的焊盘。在第一电子元件的侧面上设置绝缘层(钝化层),并且沿着绝缘层形成导电层。绝缘层的侧面形成为倾斜形状,并且导电层沿着如此形成的绝缘层的侧面设置。
发明内容
通常,为了使其中第一电子元件安装在第二电子元件上的电子元件的层叠件小型化,期望使第二电子元件小型化。为了减小第二电子元件的尺寸,可能需要将第二电子元件的焊盘靠近第一电子元件布置。如果导电层可以沿第一电子元件的侧面布置,则第二电子元件的焊盘与第一电子元件之间的所需距离被最小化,并且可以减轻对第二电子元件的尺寸减小的限制。然而,由于导电层必须在由第二电子元件的上表面和第一电子元件的侧面形成的角部(corner portion)处基本上以直角弯曲,所以导电层的电气可靠性可能劣化。
本发明旨在提供一种电子元件的层叠件及其制造方法,其中,导电层可以沿着第一电子元件的侧面布置,同时能够确保导电层的电气可靠性。
本发明的电子元件的层叠件包括:第一电子元件,其具有第一表面、与第一表面相对的第二表面以及位于第一表面和第二表面之间的侧面;第二电子元件,其具有第三表面,所述第一电子元件安装在所述第三表面上,所述第三表面面对所述第二表面,并且在所述第三表面和所述侧面之间形成角部;粘接层,用于将第一电子元件结合到第二电子元件,粘接层具有位于第二表面和第三表面之间的第一部分和填充角部的弯曲的第二部分;以及导电层,其在所述侧面的一侧上延伸,沿所述第二部分弯曲并延伸到所述第三表面。
本发明的一种制造电子元件层叠件的方法,包括:将第一电子元件安装在第二电子元件上,并通过粘接层将第一电子元件结合到第二电子元件,其中第一电子元件具有第一表面、与第一表面相对的第二表面以及位于第一表面和第二表面之间的侧面,第一电子元件的第二表面面对第二电子元件的第三表面,并且第三表面形成第三表面和侧面之间的角部,以及设置在侧面的一侧上延伸并进一步延伸到第三表面的导电层。设置粘接层,使得粘接层具有位于第二表面和第三表面之间的第一部分以及填充角部的弯曲的第二部分,并且导电层被设置为沿着第二部分弯曲。
根据本发明,用于将第一电子元件接合到第二电子元件的粘接层的一部分是填充形成在第三表面和侧面之间的角部的弯曲的第二部分,并且导电层沿着第二部分弯曲。因此,导电层不需要在角部处急转弯。因此,本发明可以提供一种电子元件的层叠件,其中,可以在确保导电层的电气可靠性的同时沿着第一电子元件的侧面布置导电层,本发明还提供一种制造该电子元件的层叠件的方法。
通过参考示出本发明的示例的附图的以下描述,本发明的以上和其它目的、特征和优点将变得显而易见。
附图说明
图1A和1B分别是示出根据第一实施方式的电子元件的层叠件的俯视图和截面图;
图2是更详细地示出图1A和1B中的层叠件的截面图;
图3A至3C是更详细地示出了图1A和1B中的层叠件的局部截面图;
图4A至4C是表示保持构件的各种变型的透视图;
图5A至5C是示意性地示出制造第一电子元件的方法的流程图;
图6A至6D是示意性地示出根据第一实施方式的制造层叠件的方法的流程图;
图7A和7B是示出根据第一实施方式的层叠件的优点的示意图;
图8是示出根据第二实施方式的电子元件的层叠件的俯视图;
图9A和9B是图8中的层叠件的截面图;
图10A和10B是更详细地示出图8中的层叠件的局部截面图;
图11A至11G是示意性地示出根据第二实施方式的制造层叠件的方法的流程图;
图12是根据另一变型的层叠件的截面图;以及
图13是根据又一变型的层叠件的截面图。
附图标记示例
1层叠件;2第一电子元件;3第二电子元件;4粘接层;5导电层;6保持构件;7第一绝缘层;9成型材料;11第三绝缘层;13第二绝缘层;21第一表面;22第二表面;23第一侧面;24第一电连接;31第三表面;33第二侧面;34第二电连接;41第一部分;42第二部分;K角部
具体实施方式
以下,将参照附图描述本发明的实施方式。本发明涉及一种电子元件的层叠件(封装),其中第一电子元件安装在第二电子元件上。在以下实施方式中,第一电子元件是磁传感器,第二电子元件是连接到磁传感器的ASIC(专用集成电路),但本发明不限于此。
(第一实施方式)
图1A是示出了电子元件的层叠件(下文中称为层叠件1)的俯视图,图1B是示出了沿着图1A中的线A-A截取的层叠件1的截面图。图2是更详细地示出层叠件1的截面图,图3A至3C分别是更详细地示出图2中的A部分、B部分和C部分的局部截面图。
第一电子元件2具有大致长方体形状。第一电子元件2具有第一表面21、与第一表面21相对的第二表面22以及位于第一表面21和第二表面22之间的第一侧面23。第一电子元件2在第一表面21上具有第一电连接24。第一电子元件2具有由硅制成的第一基底25以及设置在第一基底25上的第一钝化层26。在第一基底25中形成传感器元件,例如TMR元件(未示出)。第一钝化层26是保护第一基底25的绝缘层,并且第一表面21a由第一钝化层26的表面形成。在每个第一电连接24中,第一焊盘27形成在第一基底25的表面上,第一钝化层26包括暴露第一焊盘27的第一开口28。
第二电子元件3具有近似长方体形状。第二电子元件3具有第三表面31、与第三表面31相对的第四表面32以及位于第三表面31与第四表面32之间的第二侧面33。第二电子元件3的第三表面31面向第一电子元件2的第二表面22。第三表面31的一部分作为安装第一电子元件2的安装面,第一电子元件2通过该安装面上的粘接层4与第二电子元件3接合。第二电连接34设置在第三表面31上与安装面不同的位置处。第二电子元件3具有由硅制成的第二基底35以及设置在第二基底35上的第二钝化层36。在第二基底35中形成诸如IC(未示出)的元件。第二钝化层36是保护第二基底35的绝缘层,并且第三表面31由第二钝化层36的表面形成。在每个第二电连接34中,第二焊盘37形成在第二基底35的表面上,并且第二钝化层36具有暴露第二焊盘37的第二开口38。第二电子元件3比第一电子元件2大,第二电子元件3的第三表面31比第一电子元件2的第二面22大。具体地,第一电子元件2的第二表面22位于第二电子元件3的第三表面31的外周(circumference)内。因此,在第二电子元件3的第三表面31与第一电子元件2的第一侧面23之间形成了具有大致直角的角部K。如下文所述,第二电连接34经由导电层5连接到第一电连接24。用于与外部连接的外部连接用焊盘39设置在第二电子元件3的第三表面31的周围附近。如图1B所示,层叠件1经由连接到外部连接焊盘39的导线W连接到另一设备。
粘接层4由硅树脂制成。由于其高热性能,粘接层4能够在晶圆工艺中经受高温热处理。粘接层4具有位于第二表面22和第三表面31之间的第一部分41,以及填充角部K的弯曲形状的第二部分42。第一部分41主要作用是将第一电子元件2结合到第二电子元件3。第二部分42的一部分由预先设置在第一电子元件2外部的液态树脂形成,而其余部分由当第一电子元件2结合到第二电子元件3时从第二表面22和第三表面31之间的空间挤出的树脂形成。因此,第二部分42形成在第一部分41的侧面上,以及形成在第一侧面23的靠近第三表面31的区域(在下文中称为下部23b)中。由于树脂由于其表面张力而沿着第一侧面23上升,因此,虽然如此形成的树脂量有限,但是在第一侧面23的第二部分42和第一表面21之间的区域(下文中称为上部23a)中也形成粘接层4的一部分(未示出)。在本发明中,是否在上部23a中形成粘接层4的一部分23a不是必需的,并且形成于上部23a中的粘接层4的量不是必需的。上部23a和下部23b之间的边界在高度方向上比第一侧面23的中点更靠近第三表面31,但是该边界也可比中点更靠近第一表面21。
假设第二部分42的厚度t被定义为在第一侧面23的区域中沿着第一侧面23的法线测量的厚度,并且被定义为在第一电子元件2和第二电子元件3之间的区域中沿着第一侧面23的延伸的法线测量的厚度。如此限定的第二部分42的厚度t朝向第二电子元件3的第三表面31单调增加。另外,至少在比第一侧面23的厚度方向的中心(与第一表面21和第三表面31均等距离的中间位置)更靠近第三表面31的区域,厚度t的增加率朝向第三表面31单调增加。换言之,第二部分42具有弯曲形状,该弯曲形状在角部K附近朝向角部K凹入,并且基本上具有直角三角形的横截面,该直角三角形具有朝向角部K突出的弯曲斜边。
在第三表面31与粘接层4之间形成有保持粘接层4的保持构件6。更准确地说,保持构件6保持被固化以转变成粘接层4的液体粘合剂(树脂)。在本实施方式中,与第三表面31相比具有更高润湿性的润湿性控制层61被作为保持构件6。润湿性控制层61形成在粘接层4和第三表面31之间。润湿性是指液体在固体表面上可润湿的趋势。接触角(在固定液体表面和液体自由表面与固体壁接触的固体表面之间形成的角)越小,润湿性越高。润湿性控制层61是形成在第三表面31上并在该层和第三表面31之间形成台阶的金属层(金属焊盘)。具体而言,润湿性控制层61形成从第三表面31的周围向第一电子元件2突出的部分。润湿性控制层61例如由金属如Cu制成,但也可由能够保持将被转化为粘接层4的液体树脂的任何材料形成。在本实施方式中,通过电镀形成润湿控制层61,并且在第二钝化层36和润湿控制层61之间设置用于电镀润湿控制层61的第二种子层65。种子层第二种子层65由Cu制成,并且可以通过溅射形成。当润湿性控制层61通过溅射、CVD或类似方式形成时,第二种子层65不是必需的。从与第三表面31垂直的方向观察,润湿性控制层61的周围沿着第一电子元件2的整个周围形成在第一电子元件2的周围的外侧。
第二部分42的一部分由树脂形成,该树脂从第二表面22和第三表面31之间的空间被挤出。因此,为了以高精度和高形状再现性形成第二部分42,树脂优选具有尽可能低的粘度。然而,如果使用具有低粘度的树脂,则树脂可能广泛地分散在第三表面31上。由于润湿性控制层61具有比第三表面31更大的润湿性,所以所涂布的树脂扩散的区域被限制在润湿性控制层61的周边内。在润湿控制层61和第三表面31之间形成台阶,使得润湿控制层61在上侧,而第三表面31在下侧。因此,涂布的树脂扩散的区域也受到沿润湿性控制层61的周边产生的表面张力的限制。
保持构件6不限于上述布置,并且可以以各种方式修改。例如,如图4A所示,保持构件6可以是形成在第三表面31上并且具有比第三表面31的其它部分更大的润湿性的用于粘接层的保持表面62。可以通过对第三表面31进行粗糙表面精加工来形成具有比第三表面31更大的润湿性的保持表面62。在该变型中,保持表面62和第三表面31之间的台阶不是必需的。如图4B所示,保持构件6可以是从第三表面31沿远离第一电子元件2的方向凹进的凹部63。在该变型中,凹部63保持粘合剂,并且凹部63的底表面的润湿性不受限制。如图4C所示,保持构件6可以是设置在第三表面31上的框架构件64。在该变形例中,框架构件64保持粘合剂,并且框架构件64内部的底面的润湿性不受限制。此外,尽管未示出,但润湿控制层61可以嵌入在第二钝化层36中,使得润湿控制层61与第三表面31齐平。
如图1A、1B和2所示,第一电连接24(第一焊盘27)经由导电层5(再分布层)连接到第二电连接34(第二焊盘37)。导电层5是将第一电连接24连接到第二电连接34的条形金属层。在本实施方式中,提供了四个导电层5,但是导电层5的数量不限于此。每个导电层5从第一电连接24沿着第一表面21、然后沿着粘接层4的第二部分42(即,在第一侧面23的一侧上朝向第三表面31延伸)、然后沿着第二电子元件3的第三表面31延伸到第二电连接34。在本实施方式中,每个导电层5终止于第二电连接34。在第一侧面23的上部23a中,导电层5基本上沿着第一侧面23延伸。导电层5由Cu制成,但也可由其它导电材料制成,例如Au、Ag和Al。在本实施方式中,导电层5通过电镀形成,但也可以利用溅射法、CVD法等其他方法形成。导电层5沿着在角部K附近形成为弯曲形状的第二部分42弯曲,因此导电层5不会急剧改变方向。这使得容易确保导电层5的电气可靠性。
为了确保导电层5与第一基底25之间的电绝缘,在导电层5与第一侧面23之间以及导电层5与第一表面21之间都设置有第一绝缘层7。第一绝缘层7也设置在导电层5和第三表面31之间。第一绝缘层7由SiO2、SiN、AlO等制成,并且可以通过CVD形成。第一种子层51设置在第一绝缘层7的外表面,用于导电层5的电镀。第一种子层51由Cu制成并且可以通过溅射形成。当通过溅射、CVD等形成导电层5时,第一种子层51不是必需的。导电层5的外表面被第三钝化层8覆盖并保护。如图3A所示,在第一钝化层26和第一绝缘层7中围绕第一电连接24提供用于暴露第一焊盘27的第一开口28,并且在第一开口28的侧壁上以及在第一焊盘27上也形成第一种子层51。因此,可以建立导电层5和第一焊盘27之间的电连接。类似地,如图3C所示,在第二钝化层36中和第二电连接34周围的第一绝缘层7中都提供了用于暴露第二焊盘37的第二开口38,并且在第二开口38的侧壁上以及在第二焊盘37上也形成了第一种子层51。因此,可以建立导电层5和第二焊盘37之间的电连接。
接下来,将描述制造上述层叠件1的方法。在该制造方法中,在不同的晶圆工艺中形成第一电子元件2和第二电子元件3(形成在不同的晶圆上),并且将分离的第一电子元件2安装在设置在晶圆上的第二电子元件3上。首先,如图5A所示,将形成有多个第一电子元件2的晶圆W粘贴在粘合片S1上并固定。粘合片S1被附着到晶圆的与形成有第一电连接24的表面(第二表面22)相对的表面。从粘合片S1看,从第一电子元件2的背面,在晶圆W的厚度方向的一半(半切割)切割第一电子元件2。接着,如图5B所示,除去粘合片S1,将晶圆W翻转,并将其粘贴在另一个粘合片S2上,进行固定。即,第一电子元件2被附着到另一粘合片S2,使得第一电子元件2的被切割的表面接触粘合片S2。在该状态下,对第一电子元件2的未被切割的表面进行研磨,以使第一电子元件2变薄,直到没有未切割的部分残留为止。因此,第一电子元件2在粘合片S2上被分离。通过使用这种涉及半切割的切割方法,即使当第一电子元件2变薄时,也能够在切割过程期间防止碎裂。接着,如图5C所示,粘贴另一粘合片S3,将晶圆W翻转,并除去粘合片S2。因此,被分离的第一电子元件2能够被拾取并且能够容易地安装在相应的第二电子元件3上。当使用能够在图5B所示的状态下将第一电子元件2直接安装在第二电子元件3上的装置时,可以省略图5C所示的过程。
接下来,如图6A所示,将粘合剂43涂布到晶圆上的每个第二电子元件3的第三表面31。粘合剂43是液体树脂。具体地,第二种子层65形成在第二电子元件3的第二钝化层36上,并且润湿性控制层61通过电镀形成在第二种子层65上(图6A中未示出,参见图2和3B)。接下来,将液体粘合剂43涂布到润湿控制层61上。粘合剂43扩散以覆盖润湿控制层61的上表面。粘合剂43不覆盖润湿控制层61的整个上表面,而是优选地在润湿控制层61的上表面上在允许第一电子元件2的整个底表面接触粘合剂43的区域上散布。换句话说,第一电子元件2的第二表面22的面积小于粘合剂43散布的面积。这使得第二部分42能够沿着第一电子元件2的第二表面22的整个外周形成。粘合剂43可以覆盖润湿控制层61的整个上表面。因为润湿控制层61的面积大于第一电子元件2的第二表面22的面积,所以第二部分42沿着第一电子元件2的第二表面22的整个周边形成。应注意,虽然在图6A至6D中仅示出了一个第二电子元件3,但是在晶圆上形成了多个第二电子元件3。接着,如图6B所示,将第一电子元件2安装在覆盖有粘合剂43的润湿控制层61上。第一电子元件2的第二表面22面向第二电子元件3的第三表面31,并且角部K形成在第二电子元件3的第三表面31和第一电子元件2的第一侧面23之间。由于第一电子元件2的重量或通过控制压力,一部分粘合剂43被挤出第二表面22和第三表面31之间的空间,并沿着第一侧面23上升(见图2)。因此,形成第二部分42。通过调整粘合剂43的量、第一电子元件2的移动速度、按压力等,可以确保第二部分42的形状的再现性。当热固性树脂用作粘合剂43时,通过加热树脂将第一电子元件2结合到第二电子元件3以形成第二部分42。然后,使粘合剂43固化,形成粘接层4。
接下来,如图6C所示,形成将第一表面21上的第一电连接24连接到第三表面31上的第二电连接34的导电层5。具体而言,首先,在第一电子元件2的第一表面21和第一侧面23上,以及第二电子元件3的第三表面31上形成第一绝缘层7(参照图2、图3A~图3C)。第一绝缘层7例如可以通过CVD形成。在这种情况下,粘接层4的表面也被第一绝缘层7覆盖。接着,去除第一绝缘层7的在第一、第二焊盘27和37正上方的部分,以便暴露第一、第二焊盘27和37。然后,根据以下工艺形成导电层5。首先,在第一绝缘层7上以及在已经暴露的第一焊盘27和第二焊盘37上形成第一种子层51。接着,在第一种子层51上形成抗蚀剂,并且通过构图去除抗蚀剂的将要形成导电层5的部分,以便暴露第一种子层51。然后,将晶圆浸入电镀槽中,以便电镀第一种子层51的已暴露部分。由于镀层沿着第二部分42形成为弯曲形状,所以导电层5能够如上所述地从第一电子元件2的第一侧面23朝向第二电子元件3的第三表面31逐渐改变方向。然后,去除抗蚀剂,并且通过研磨等去除第一种子层51的未被镀覆的部分。随后,在导电层5上形成第三钝化层8。第三钝化层8例如可以通过CVD形成。如图6D所示,然后在第二电子元件3的第三表面31上形成外部连接用焊盘39。此后,尽管未示出,但是其上形成有第二电子元件3的晶圆被切割以分离层叠件1。
下面,将描述本实施方式的优点。由第一电子元件2和第二电子元件3形成的角部K是难以形成金属层并难以确保导电层5的电气可靠性的部分,而与导电层5如何形成无关(即,与导电层5是通过电镀形成还是通过除了电镀之外的方法(例如溅射)形成无关)。在本实施方式中,粘接层4的第二部分42形成在第一电子元件2的外侧。由于第二部分42形成为弯曲形状,所以可以通过沿着第二部分42形成导电层5来逐渐改变角部K附近的导电层5的方向。因此,在本实施方式中,能够容易地确保导电层5的电气可靠性。
实际上,如果可能,可以使用除粘合剂以外的构件以在角部K中形成弯曲部分。然而,使用这种构件可能使制造过程复杂化并影响成本。在本实施方式中,使用用于将第一电子元件2接合到第二电子元件3的液态树脂来在角部K中提供弯曲部分,并且不需要额外的构件。另外,在将第一电子元件2安装在第二电子元件3上时,树脂的变形同时发生,不需要用于使树脂变形的特殊步骤。即,本实施方式的粘接层4(粘合剂43)不仅用于将第一电子元件2与第二电子元件3粘接,而且还通过将粘接层4(粘合剂43)从第一电子元件2压出而用作导电层5的支承层。
此外,由于导电层5可以基本上沿着第一电子元件2的第一侧面23形成,所以第二电子元件3的第二电连接34可以布置在第一电子元件2附近。因此,减轻了对第二电连接34的位置的限制,并且可以使第二电子元件3以及层叠件1(封装)小型化。第二电子元件3的尺寸减小使得每个晶圆获得的第二电子元件3的数量增加。
第一绝缘层7是形成在第一电子元件2的第一表面21和第一侧面23上以及第二电子元件3的第三表面31上的薄膜。这在生产过程中带来了进一步的优势。图7A和7B是示意性地示出了美国专利号9466580中公开的层叠件的截面图。如图7A所示,在第一电子元件2的侧面形成倾斜的绝缘层101,沿着该倾斜的侧面形成导电层5。由于形成在第三表面31上的绝缘层101的厚度与第一电子元件2的高度基本相同,因此如图7B所示,在第一电子元件2的第一表面21上形成高度与第一电子元件2的高度基本相同的绝缘层101。因此,为了在第一表面21上形成导电层5,需要预先除去绝缘层101的虚线以上的部分。相反,在本实施方式中,在第一绝缘层7中不产生这种大的台阶。不需要使第一绝缘层7平坦的工序,能够简化工序。
此外,在除了形成导电膜5的部分之外的部分中也形成用于形成导电膜5的第一种子层51。因此,在完成电镀导电膜5的工艺之后(在去除抗蚀剂之后),需要去除前者中的第一种子层51。当角部K形成直角时,很难去除第一种子层51,但是在本实施方式中,第一电子元件2和第二电子元件3之间的边界通过粘接层4形成为弯曲形状,并且可以容易地去除第一种子层51。
(第二实施方式)
将参照图8至11G描述根据第二实施方式的层叠件101。以下,将主要描述与第一实施方式的不同之处。没有特别提及的结构和效果与第一实施方式的相同。图8是示出根据第二实施方式的层叠件101的俯视图,图9A和9B分别是沿图8的线A-A和线B-B截取的层叠件101的截面图。图10A和10B分别是更详细地示出图9A中的D部分和E部分的局部截面图。应注意,图9A中的A部分和B部分与第一实施方式中的相同。参见图3A至图3C及上述描述。
在本实施方式中,粘接层4的第二部分42和导电层5被由环氧树脂制成的成型材料(molding material)9覆盖。导电柱10与导电层5连接。导电柱10绕过第二电子元件3,以便直接取出第一电子元件2的输出。当柱10被布置在第一电子元件2的正上方时,柱10被连接到外部连接部分(焊球、导线等)时产生的应力可以通过柱10直接施加到第一电子元件2。当第一电子元件2是磁传感器或半导体元件时,输出可能由于应力的影响而变化。通过将柱10配置在第一电子元件2的外侧,能够避免该问题。柱10由与导电层5相同的材料(Cu)制成。第一电子元件2、导电层5和粘接层4的结构与第一实施方式相同。另一方面,如图9A和10B所示,没有提供第二电子元件34。在柱10和导电层5之间的连接部分,第二钝化层36设置在第二基底35上,并且第一绝缘层7、第一种子层51和导电层5依次设置在第二钝化层36上。如图9A和10A所示,用于外部连接的导电端子12设置在柱10的顶端。柱10沿其外周覆盖有第三钝化层8。
如图9B所示,第三绝缘层11设置在粘接层4的第二部分42和成型材料9之间。由于作为成型材料9的材料的环氧树脂与作为粘接层4的材料的硅树脂之间的粘合性差,所以环氧树脂容易从硅树脂上剥离。第三绝缘层11防止粘接层4直接接触成型材料9,从而降低成型材料9从粘接层4剥离的可能性。
在本实施方式中,环氧树脂用作成型材料9,但环氧树脂也可用作粘接层4的第二部分42的涂覆膜。在这种情况下,也优选地将第三绝缘层11设置在由环氧树脂制成的涂覆膜和粘接层4的第二部分42之间。此外,在本实施方式中,第三绝缘层11直接覆盖粘接层4的第二部分42,但也可以经由其他层间接地覆盖第二部分42。
接下来,将描述制造上述电子元件的层叠件101的方法。在该制造方法中,也在不同的晶圆工艺中形成第一电子元件2和第二电子元件3(形成在不同的晶圆上),并且将分离的第一电子元件2安装在设置在晶圆上的第二电子元件3上。第一电子元件2以与第一实施方式相同的方式制造。参见图5A至图5C及上述描述。
接下来,如图11A所示,将第一电子元件2接合到第二电子元件3上,然后形成导电层5。该过程可以以与第一实施方式相同的方式进行。参见图6A至图6D及上述描述。应注意,在本实施方式中未提供图6A到6D中所示的第二电连接34和外部连接焊盘39。在该阶段不形成第三钝化层8。接着,如图11B所示,通过电镀在导电层5上形成柱10。第一种子层51不是必需的,因为柱10形成在导电层5上。在形成柱10之后,在导电层5上和柱10周围形成第三钝化层8。
接着,如图11C所示,在第一电子元件2、第二电子元件3、导电层5和导电柱10上成型环氧树脂。如图11D所示,成型材料9的上部被研磨以露出柱10的顶部。如图11E所示,在柱10的顶部通过电镀形成用于外部连接的端子12。如图11F所示,晶圆从成型材料9侧切去一半。具体而言,成型材料9沿其厚度方向切去其的整个长度,第二基底35沿厚度方向切去其一半。如图11G所示,从相对面研磨第二基底35以减薄第二基底35,直到在厚度方向上没有未切割部分剩余。因此,层叠件1被分离。应注意,当层叠件101不需要薄化时,可省略图11F及11G中所示的工艺。
尽管已经通过实施方式描述了本发明,但是可以进行各种修改。例如,如图12所示,第二绝缘层13可以设置在第一电子部件2的第一侧面23上。导电层5通过第一绝缘层7与第一电子元件2绝缘。然而,由于导电层5靠近第一电子元件2,特别是第一电子元件2的第一侧面23的上方(第一表面21),因此,如果在第一绝缘层7中产生缺陷,则仅通过设置间隙来确保绝缘可能是困难的。第二绝缘层13提高了绝缘的可靠性。可以在晶圆工艺中提供第二绝缘层13,并且在该工艺中不会出现明显的缺点。
如图13所示,层叠件1还可以经由连接到外部连接焊盘39的焊球14连接到由虚线表示的另一装置15。
在本实施方式中,第一电子元件2具有长方体形状,并且第一表面21和第二表面22是平面且互相平行。然而,第一表面21和第二表面22可以是弯曲的或不平的。第一表面21和第二表面22可以彼此不平行。
此外,在本实施方式中,导电层5从第一电子元件2的第一电连接部24沿着第一电子元件2的第一侧面23侧朝向第三表面31延伸,但导电层5不需要连接至第一电连接部24。例如,导电层5可以从安装在第一电子元件2上的另一电子元件的电连接延伸到第一电子元件2的第一侧面23侧。换言之,导电层可以沿着任何路径,只要导电层在第一电子元件2的第一侧面23一侧上延伸、沿着粘接层4的第二部分42弯曲、并且延伸到第二电子元件3的第三表面31。
在本实施方式中,第一电子元件2是磁传感器,第二电子元件3是连接到该磁传感器的集成电路。然而,也可以配置成第一电子元件2是集成电路而第二电子元件3是磁传感器。即,第一电子元件2或第二电子元件3中的任一个可以是磁传感器,而其余元件可以是连接到磁传感器的集成电路。
在本实施方式中,第一电子元件2安装在第二电子元件3上。然而,第三电子元件可以安装在第二电子元件3上。在这种情况下,第三电子元件可以安装在第二电子元件3的安装有第一电子元件2的表面(第三表面31)上,但是也可以安装在与第三表面31相反的表面上,即,第四表面32上。
尽管已经详细示出和描述了本发明的某些优选实施方式,但是应当理解,在不脱离所附权利要求的精神或范围的情况下,可以进行各种改变和修改。

Claims (23)

1.一种电子元件的层叠件,包括:
第一电子元件,具有第一表面、与第一表面相对的第二表面以及位于第一表面和第二表面之间的侧面;
第二电子元件,具有第三表面,所述第一电子元件安装在所述第三表面上,所述第三表面面对所述第二表面,并且在所述第三表面和所述侧面之间形成角部;
粘接层,用于将所述第一电子元件结合到所述第二电子元件,其中,所述粘接层具有位于所述第二表面和所述第三表面之间的第一部分和填充所述角部的弯曲的第二部分;以及
导电层,其在所述侧面的一侧上延伸,沿着所述第二部分弯曲并延伸到所述第三表面,
在所述侧面的所述第一表面侧的部分中,所述导电层沿着所述侧面延伸。
2.根据权利要求1所述的电子元件的层叠件,其中,
所述导电层从所述第一表面延伸到所述第三表面。
3.根据权利要求2所述的电子元件的层叠件,其中,
所述第一电子元件在所述第一表面上具有第一电连接,
所述第二电子元件在所述第三表面上具有第二电连接,并且
所述导电层沿着所述粘接层的所述第二部分延伸,并且将所述第一电连接连接到所述第二电连接。
4.根据权利要求1至3中任一项所述的电子元件的层叠件,还包括:在所述第二电子元件和所述粘接层之间的用于所述粘接层的保持表面,其中,所述保持表面的润湿性大于所述第三表面的润湿性。
5.根据权利要求4所述的电子元件的层叠件,其中,
所述保持表面从所述第三表面朝所述第一电子元件突出。
6.根据权利要求4所述的电子元件的层叠件,其中,
当在垂直于所述第三表面的方向上观察时,沿着所述第一电子元件的整个外周,在所述第一电子元件的外周的外侧形成所述保持表面的外周。
7.根据权利要求1至3中任一项所述的电子元件的层叠件,还包括:用于保持所述粘接层的凹部,其中,所述凹部在远离所述第一电子元件的方向上从所述第三表面凹进。
8.根据权利要求7所述的电子元件的层叠件,其中,
当在垂直于所述第三表面的方向上观察时,沿着所述第一电子元件的整个外周,在所述第一电子元件的外周的外侧形成所述凹部的外周。
9.根据权利要求1至3中任一项所述的电子元件的层叠件,还包括:设置在所述第三表面上并保持所述粘接层的框架构件。
10.根据权利要求9所述的电子元件的层叠件,其中,
当在垂直于所述第三表面的方向上观察时,沿着所述第一电子元件的整个外周,在所述第一电子元件的外周的外侧形成所述框架构件的外周。
11.根据权利要求1所述的电子元件的层叠件,其中,
所述第二部分的厚度朝向所述第三表面单调增加。
12.根据权利要求1所述的电子元件的层叠件,其中,
所述第二部分具有在所述角部附近凹入的弯曲形状。
13.根据权利要求1所述的电子元件的层叠件,还包括:第一绝缘层,设置在所述导电层和所述第三表面之间以及所述导电层和所述侧面之间。
14.根据权利要求1所述的电子元件的层叠件,还包括:设置在所述侧面上的第二绝缘层。
15.根据权利要求1所述的电子元件的层叠件,其中,所述粘接层由有机硅树脂制成,还包括:
环氧树脂层,覆盖所述粘接层的所述第二部分和所述导电层,并且
在所述粘接层的第二部分和所述环氧树脂层之间设置第三绝缘层。
16.根据权利要求1所述的电子元件的层叠件,其中,
所述第一电子元件是磁传感器,所述第二电子元件是连接到所述磁传感器的集成电路,或者,所述第二电子元件是磁传感器,所述第一电子元件是连接到所述磁传感器的集成电路。
17.一种制造电子元件的层叠件的方法,包括以下步骤:
将第一电子元件安装在第二电子元件上,并通过粘接层将所述第一电子元件结合到所述第二电子元件,其中,所述第一电子元件具有第一表面、与第一表面相对的第二表面以及位于第一表面和第二表面之间的侧面,所述第一电子元件的所述第二表面面对所述第二电子元件的第三表面,并且所述第三表面在所述第三表面和所述侧面之间形成角部,以及
设置导电层,其在所述侧面的一侧延伸,并进一步延伸至所述第三表面,
其中,所述粘接层被设置成使得所述粘接层具有位于所述第二表面和所述第三表面之间的第一部分以及填充所述角部的弯曲的第二部分,并且所述导电层被设置成沿着所述第二部分弯曲并且在所述侧面的所述第一表面侧的部分中沿着所述侧面延伸。
18.根据权利要求17所述的制造电子元件的层叠件的方法,其中,
通过将液态树脂涂覆到所述第三表面,然后经由所涂覆的树脂将所述第一电子元件安装到所述第二电子元件上,并固化所述树脂,来形成所述粘接层,以及
在所述树脂固化之前,通过保持构件将所述树脂保持在预定区域中,其中,所述保持构件限制所述树脂扩散的区域。
19.根据权利要求18所述的制造电子元件的层叠件的方法,其中,
所述保持构件是保持所述树脂的表面,并且其润湿性大于所述第三表面的润湿性。
20.根据权利要求19所述的制造电子元件的层叠件的方法,其中,
保持表面从所述第三表面朝所述第一电子元件突出。
21.根据权利要求18所述的制造电子元件的层叠件的方法,其中,
所述保持构件是从所述第三表面沿着远离所述第一电子元件的方向凹进的凹部。
22.根据权利要求18所述的制造电子元件的层叠件的方法,其中,
所述保持构件是设置在所述第三表面上的框架构件。
23.根据权利要求17至22中任一项所述的制造电子元件的层叠件的方法,其中,
在晶圆工艺中在所述侧面上设置第二绝缘层。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154694A (ja) * 1997-07-31 1999-02-26 Sanyo Electric Co Ltd 半導体装置および混成集積回路装置
JPH11233531A (ja) * 1998-02-17 1999-08-27 Nec Corp 電子部品の実装構造および実装方法
JP2000049279A (ja) * 1998-07-30 2000-02-18 Sanyo Electric Co Ltd 半導体装置
JP2004039988A (ja) * 2002-07-05 2004-02-05 Shinko Electric Ind Co Ltd 素子搭載用回路基板及び電子装置
JP2004281538A (ja) * 2003-03-13 2004-10-07 Seiko Epson Corp 電子装置及びその製造方法、回路基板並びに電子機器
CN101320696A (zh) * 2007-06-04 2008-12-10 矽品精密工业股份有限公司 堆叠式封装结构及其制法
CN102934532A (zh) * 2010-06-15 2013-02-13 罗伯特·博世有限公司 用于制造电连接结构的方法及电连接结构
JP2018500538A (ja) * 2014-11-03 2018-01-11 メレクシス・テクノロジーズ・ナムローゼフェンノートシャップ 磁界センサおよびその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0951020A (ja) 1995-08-08 1997-02-18 Hitachi Ltd 半導体装置およびその製造方法ならびにicカード
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US7960830B2 (en) * 2003-11-14 2011-06-14 Industrial Technology Research Institute Electronic assembly having a multilayer adhesive structure
JP2005277356A (ja) * 2004-03-26 2005-10-06 Sanyo Electric Co Ltd 回路装置
JP2006270009A (ja) 2005-02-25 2006-10-05 Seiko Epson Corp 電子装置の製造方法
KR100912427B1 (ko) 2006-10-23 2009-08-14 삼성전자주식회사 적층 칩 패키지 및 그 제조 방법
JP5014853B2 (ja) * 2007-03-23 2012-08-29 株式会社日立製作所 半導体装置の製造方法
US9153517B2 (en) * 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
JP2011198779A (ja) * 2008-07-22 2011-10-06 Sharp Corp 電子回路装置、その製造方法及び表示装置
US11067643B2 (en) 2014-11-03 2021-07-20 Melexis Technologies Nv Magnetic field sensor and method for making same
KR101654433B1 (ko) 2014-12-03 2016-09-05 앰코 테크놀로지 코리아 주식회사 센서 패키지 및 그 제조 방법
US11230471B2 (en) 2016-02-05 2022-01-25 X-Celeprint Limited Micro-transfer-printed compound sensor device
JP6927179B2 (ja) * 2018-10-12 2021-08-25 Tdk株式会社 電気部品の積層体とその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154694A (ja) * 1997-07-31 1999-02-26 Sanyo Electric Co Ltd 半導体装置および混成集積回路装置
JPH11233531A (ja) * 1998-02-17 1999-08-27 Nec Corp 電子部品の実装構造および実装方法
JP2000049279A (ja) * 1998-07-30 2000-02-18 Sanyo Electric Co Ltd 半導体装置
JP2004039988A (ja) * 2002-07-05 2004-02-05 Shinko Electric Ind Co Ltd 素子搭載用回路基板及び電子装置
JP2004281538A (ja) * 2003-03-13 2004-10-07 Seiko Epson Corp 電子装置及びその製造方法、回路基板並びに電子機器
CN101320696A (zh) * 2007-06-04 2008-12-10 矽品精密工业股份有限公司 堆叠式封装结构及其制法
CN102934532A (zh) * 2010-06-15 2013-02-13 罗伯特·博世有限公司 用于制造电连接结构的方法及电连接结构
JP2018500538A (ja) * 2014-11-03 2018-01-11 メレクシス・テクノロジーズ・ナムローゼフェンノートシャップ 磁界センサおよびその製造方法

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DE102019127007A1 (de) 2020-04-16
US20200118963A1 (en) 2020-04-16
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US20210327846A1 (en) 2021-10-21

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