TW201409660A - 層疊封裝裝置的形成方法 - Google Patents

層疊封裝裝置的形成方法 Download PDF

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Publication number
TW201409660A
TW201409660A TW102128215A TW102128215A TW201409660A TW 201409660 A TW201409660 A TW 201409660A TW 102128215 A TW102128215 A TW 102128215A TW 102128215 A TW102128215 A TW 102128215A TW 201409660 A TW201409660 A TW 201409660A
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Taiwan
Prior art keywords
substrate
wafer
package
forming
wafers
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TW102128215A
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English (en)
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TWI523189B (zh
Inventor
Jing-Cheng Lin
Shih-Ting Lin
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201409660A publication Critical patent/TW201409660A/zh
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Abstract

一層疊封裝裝置的形成方法實施例，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊一第一晶片，至少第一晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；以及於第一晶片上堆疊一第二晶片。基板可形成自一有機基板、一陶瓷基板、一矽基板、一玻璃基板以及一層壓基板其中之一者。

Description

層疊封裝裝置的形成方法
本發明係有關一種半導體封裝技術，且特別有關一種層疊封裝(Package-on-Package,PoP)裝置的形成方法。
隨著對更微小的電子產品的需求日益增加，製造商及其他電子產業人士為此持續地尋找方法來縮小用於電子產品的積體電路的尺寸。就這方面而言，三維類型的積體電路封裝技術已開發並投入使用。
一種已開發的封裝技術為層疊封裝(Package-on-Package,PoP)。如其名稱所暗示，層疊封裝為半導體封裝的新技術，其涉及到將一封裝體堆疊至另一封裝體上。一層疊封裝裝置可能縱向地結合獨立的記憶體與邏輯封裝體。
不幸的是，用於製造層疊封裝裝置的傳統製程可能無法完全避免封裝體產生翹曲(warping)，特別在堆疊相對薄的晶片或積體電路時這種情況會更加嚴重。
本發明之實施例係揭示一種層疊封裝裝置的形成方法，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊一第一晶片，至少第一晶片與基板其中之一者具有一熱膨 脹係數，其與承載基板的熱膨脹係數不匹配；以及於第一晶片上堆疊一第二晶片。
本發明之另一實施例係揭示一種層疊封裝裝置的形成方法，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊複數個晶片，至少此些晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；以及在堆疊此些晶片之後，移除承載基板。
本發明之又一實施例係揭示一種層疊封裝裝置的形成方法，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊一第一晶片，至少第一晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；於第一晶片上堆疊一第二晶片，第二晶片相對於第一晶片橫向地偏移而使第二晶片具有一懸空部分；以及於第一晶片與基板之間及第一晶片與第二晶片之間流入一底膠材料。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
10‧‧‧層疊封裝裝置
12‧‧‧黏膠
14‧‧‧承載基板
16‧‧‧基板
18‧‧‧金屬內連線
20‧‧‧壓力退火蓋板
22‧‧‧第一晶片
24‧‧‧底膠材料
26‧‧‧第二晶片
28‧‧‧模封物材料
30‧‧‧焊球
32‧‧‧基板側壁
34‧‧‧懸空部分
36‧‧‧鈍化護層
38‧‧‧矽通孔電極
40‧‧‧鋁接觸墊
42‧‧‧焊料
第1A至1I圖共同為一層疊封裝裝置的形成方法實施例示意圖，其利用承載基板(carrier)以抑制或避免堆疊的晶片產生翹曲。
第2圖為利用第1A至1I圖所繪示之方法形成的一層疊封裝裝置實施例剖面示意圖。
第3圖為利用第1A至1I圖所繪示之方法形成的一層疊封裝裝置實施例剖面示意圖，其裝置中無任何底膠(underfill)。
第4圖為利用第1A至1I圖所繪示之方法形成的一層疊封裝裝置實施例剖面示意圖，其基板側壁上無任何模封物(molding)。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅為示例性而非用以侷限本發明的範圍。
本發明將說明關於特定背景中的實施例，即一層疊封裝(PoP)半導體裝置。然而，本發明所揭露的概念亦可應用於其他半導體結構或線路。
現請參照第1A至1I圖，一層疊封裝裝置10(見第2至4圖)的形成方法係共同繪示於此。如第1A圖所示，於一承載基板(carrier)14上沉積或形成一黏膠12或其他合適的接合材料。在一實施例中，承載基板14係形成自玻璃、矽、具有低熱膨脹係數(coefficient of thermal expansion)的材料或其他合適的承載基板材料。實際上，承載基板14一般為具有良好硬度(stiffness)的高模數材料。
現請參照第1B圖，利用黏膠12或其他合適的接合材料以將一基板16暫時地裝設於承載基板14上。在一實施例中，基板16為具有或支撐金屬內連線18或金屬化層的一有機基板、一陶瓷基板、一矽基板、一玻璃基板或一層壓基板。在一 實施例中，基板16係形成自環氧樹脂、樹脂或其他材料。
現請參照第1C圖，在一實施例中，在基板16暫時地裝設於承載基板14上(如第1B圖所示)之後，實施一壓力退火(pressure anneal)。壓力退火一般係使基板16偏向承載基板14，此可確保基板16穩固地(雖然是暫時地)裝設於承載基板14上。在一實施例中，利用伴隨熱量的壓力退火蓋板20來實施第1C圖的壓力退火。在一實施例中，可能在之後才於第1A至1I圖所繪示的方法實施例實施壓力退火。舉例來說，可於晶圓、面板、單一組件或多個組件上實施壓力退火。此外，在一實施例中，壓力退火僅包括壓力而無熱量的施加。
現請參照第1D圖，在移除第1C圖的壓力退火蓋板20之後，利用例如像焊球及對應的接觸墊將一第一晶片22貼附於基板16。第一晶片22可包括多個邏輯部件(一邏輯積體電路、類比電路等)及一記憶體部件等部件。基板16及/或晶片22一般為熱膨脹係數與承載基板14的熱膨脹係數不匹配的材料。如同後續詳述，此可抑制或避免例如像於基板16上堆疊的晶片或其他半導體結構產生任何翹曲。
在放置第一晶片22之後，可於第一晶片22與基板16之間流入一底膠(underfill)材料24。在一實施例中，可省略第一晶片22與基板16之間的底膠材料24。
現請參照第1E圖，在裝設第一晶片22之後，利用例如像焊球及對應的接觸墊將一第二晶片26貼附於第一晶片22上。第二晶片26可包括多個邏輯部件(一邏輯積體電路、類比電路等)及一記憶體部件等部件。需注意的是，將第二晶片 26堆疊至第一晶片22上一般即形成層疊封裝裝置10。
在放置第二晶片26(如第1E圖所示)之後，可於第二晶片26與第一晶片22之間流入一底膠(underfill)材料24。在一實施例中，可省略底膠材料24。如同後續詳述，在一實施例中，可相對於第一晶片22橫向地偏移第二晶片26而使第二晶片26具有一懸空部分(overhang)。
現請參照第1F圖，在裝設第二晶片26之後，於例如像基板16的暴露部分、第一晶片22及第二晶片26上形成一模封物(molding)材料。在一實施例中，模封物材料28亦形成於設置於承載基板14上且鄰近於基板16的黏膠12上。在一實施例中，模封物材料28一般會密封第一晶片22與第二晶片26。
現請參照第1G圖，在形成模封物材料28於第一晶片22與第二晶片26上之後，實施一研磨(grinding)製程以移除模封物材料28的上方部分。如第1G圖所示，研磨製程可顯露第二晶片26的上表面。然而，在一實施例中，研磨製程可留下設置於第二晶片26上的模封物材料的一部分或薄層。
現請參照第1H圖，在實施研磨製程之後，翻轉組件(assembly)且實施一剝離(de-bonding)製程以將承載基板14自基板16上移除。此外，實施一清洗製程以將黏膠12自基板16及模封物材料28上移除。一旦實施剝離與清洗製程，基板16中金屬內連線18的接觸墊便可顯露出來。
現請參照第1I圖，在實施剝離與清洗製程之後，實施一植球(ball mount)製程以於基板16中金屬內連線18的接觸墊上形成焊球30的陣列。此外，實施一晶圓切割(wafer saw)製 程以分離層疊封裝裝置10。如第1I圖所示，在晶圓切割製程之後，一部份的模封物材料28仍覆蓋基板16的側壁32。然而，在一實施例中，晶圓切割製程將模封物材料28自基板16的側壁32上移除。
現請參照第2圖，利用上述實施例方法所形成的一層疊封裝裝置10實施例係繪示於此。如第2圖所示，層疊封裝裝置10包括一第一晶片22，其堆疊於基板16上，及一第二晶片26，其堆疊於第一晶片22上。在一實施例中，第二晶片26係相對於第一晶片22橫向地偏移以使第二晶片26如上述般具有一懸空部分34。
在一實施例中，底膠材料24係設置於基板16與第一晶片22之間及第一晶片22與第二晶片26之間。在一實施例中，底膠材料24僅設置於基板16與第一晶片22之間。在一實施例中，底膠材料24僅設置於第一晶片22與第二晶片26之間。此外，層疊封裝裝置10的模封物材料28係形成於基板16的一部分、第一晶片22及第二晶片26周圍。在一實施例中，模封物材料28可省略。
繼續參照第2圖，層疊封裝裝置10的基板16支撐金屬內連線18及/或其他連線結構(例如，凸塊下方金屬(under bump metallization))，其用於電性耦接焊球30(即，球柵陣列(ball grid array))與第一晶片22。層疊封裝裝置10亦可包括其他結構、層或材料，例如像鈍化護層(passivation layer)36、矽通孔電極(through silicon vias,TSVs)38、鋁接觸墊40、焊料42等等。
現請參照第3圖，在一實施例中，層疊封裝裝置10省略第2圖的底膠材料24並將其置換為模封物材料28。換句話說，模封物材料28係作為第3圖的層疊封裝裝置10實施例之底膠。
現請參照第4圖，在一實施例中，模封物材料28可自基板16的側壁32上遠離或移除。作為範例，在第1F圖的模封製程沉積模封物材料28時，模封物材料28可不形成於側壁32上。換句話說，模封物材料28可避免於側壁32上形成。在其他實施例中，模封物材料28可藉由第1I圖的晶圓切割製程自基板16的側壁32上移除。換句話說，晶圓切割製程將模封物材料28自側壁32上移除。
可理解的是實施例方法與層疊封裝裝置10提供了許多優點。實際上，在堆疊晶片22、26時藉由利用承載基板14可抑制或避免翹曲產生，即使是堆疊相對薄的晶片。此外，可以有或沒有懸空部分的方式堆疊多個晶片。
一層疊封裝裝置的形成方法實施例，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊一第一晶片，至少晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；以及於第一晶片上堆疊一第二晶片。
一層疊封裝裝置的形成方法實施例，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊複數個晶片，至少此些晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；以及在堆疊此些晶片之後，移除承載基板。
一層疊封裝裝置的形成方法實施例，包括：將一基板暫時地裝設於一承載基板上；於基板上堆疊一第一晶片，至少第一晶片與基板其中之一者具有一熱膨脹係數，其與承載基板的熱膨脹係數不匹配；於第一晶片上堆疊一第二晶片，第二晶片相對於第一晶片橫向地偏移而使第二晶片具有一懸空部分；以及於第一晶片與基板之間及第一晶片與第二晶片之間流入一底膠材料。
儘管本發明揭露內容係就示例性實施例來說明，但這些說明並非意圖解釋為限定的含意。在所屬技術領域具有通常知識者參考說明時，示例性實施例的各種更動與結合以及本發明其他的實施例是相當明顯的。因此，所附的請求項亦應涵蓋任何更動或實施例。
10‧‧‧層疊封裝裝置
16‧‧‧基板
18‧‧‧金屬內連線
22‧‧‧第一晶片
24‧‧‧底膠材料
26‧‧‧第二晶片
28‧‧‧模封物材料
30‧‧‧焊球
32‧‧‧基板側壁
34‧‧‧懸空部分
36‧‧‧鈍化護層
38‧‧‧矽通孔電極
40‧‧‧鋁接觸墊
42‧‧‧焊料

Claims (10)

  1. 一種層疊封裝裝置的形成方法，包括：將一基板暫時地裝設於一承載基板上；於該基板上堆疊一第一晶片，至少該第一晶片與該基板其中之一者具有一熱膨脹係數，其與該承載基板的熱膨脹係數不匹配；以及於該第一晶片上堆疊一第二晶片。
  2. 如申請專利範圍第1項所述之層疊封裝裝置的形成方法，更包括相對於該第一晶片橫向地偏移該第二晶片而使該第二晶片具有一懸空部分。
  3. 如申請專利範圍第1項所述之層疊封裝裝置的形成方法，更包括在堆疊該第一與該第二晶片之前，利用一壓力退火蓋板以對該基板實施一壓力退火。
  4. 如申請專利範圍第1或2項所述之層疊封裝裝置的形成方法，更包括僅於該第一晶片與該基板之間，或僅於該第一晶片與該第二晶片之間流入一底膠材料。
  5. 如申請專利範圍第1項所述之層疊封裝裝置的形成方法，更包括於該基板的暴露部分、該第一晶片及該第二晶片上形成一模封物材料。
  6. 如申請專利範圍第5項所述之層疊封裝裝置的形成方法，更包括研磨去除該模封物材料的一部份。
  7. 一種層疊封裝裝置的形成方法，包括：將一基板暫時地裝設於一承載基板上；於該基板上堆疊複數個晶片，至少該些晶片與該基板其中 之一者具有一熱膨脹係數，其與該承載基板的熱膨脹係數不匹配；以及在堆疊該些晶片之後，移除該承載基板。
  8. 如申請專利範圍第7項所述之層疊封裝裝置的形成方法，更包括在堆疊該些晶片時，相對於其他該些晶片橫向地偏移該些晶片其中之一者。
  9. 如申請專利範圍第7項所述之層疊封裝裝置的形成方法，更包括在堆疊該些晶片之後，僅於該基板與該些晶片中最靠近該基板的一晶片之間，或僅於該些晶片之間流入一底膠材料。
  10. 如申請專利範圍第7項所述之層疊封裝裝置的形成方法，更包括於該基板的暴露部分上與該些晶片上形成一模封物材料。
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