TWI695421B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI695421B
TWI695421B TW104143856A TW104143856A TWI695421B TW I695421 B TWI695421 B TW I695421B TW 104143856 A TW104143856 A TW 104143856A TW 104143856 A TW104143856 A TW 104143856A TW I695421 B TWI695421 B TW I695421B
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TW
Taiwan
Prior art keywords
adhesive sheet
semiconductor
semiconductor wafer
adhesive
sheet
Prior art date
Application number
TW104143856A
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English (en)
Chinese (zh)
Other versions
TW201635361A (zh
Inventor
岡本直也
佐藤明徳
藤本泰史
毛受利彰
山田忠知
河崎仁彦
Original Assignee
日商琳得科股份有限公司
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Application filed by 日商琳得科股份有限公司 filed Critical 日商琳得科股份有限公司
Publication of TW201635361A publication Critical patent/TW201635361A/zh
Application granted granted Critical
Publication of TWI695421B publication Critical patent/TWI695421B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW104143856A 2014-12-26 2015-12-25 半導體裝置之製造方法 TWI695421B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-266140 2014-12-26
JP2014266140A JP6482866B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201635361A TW201635361A (zh) 2016-10-01
TWI695421B true TWI695421B (zh) 2020-06-01

Family

ID=56359712

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104143856A TWI695421B (zh) 2014-12-26 2015-12-25 半導體裝置之製造方法

Country Status (2)

Country Link
JP (1) JP6482866B2 (enrdf_load_stackoverflow)
TW (1) TWI695421B (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019026266A1 (ja) * 2017-08-04 2019-02-07 リンテック株式会社 半導体装置の製造方法
JP7093630B2 (ja) * 2017-12-27 2022-06-30 リンテック株式会社 離間装置および離間方法
KR102799377B1 (ko) * 2018-03-07 2025-04-22 린텍 가부시키가이샤 익스팬드 방법, 반도체 장치의 제조 방법, 및 점착 시트
JP7250468B6 (ja) * 2018-10-12 2023-04-25 三井化学株式会社 電子装置の製造方法および粘着性フィルム
JP2021034398A (ja) * 2019-08-14 2021-03-01 株式会社ジャパンディスプレイ 素子移載装置、素子移載方法
KR102351045B1 (ko) * 2019-12-19 2022-01-14 한국기계연구원 마이크로 소자의 간격 조절 전사방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243910A (ja) * 2004-02-26 2005-09-08 Lintec Corp 半導体チップの製造方法
JP2010199565A (ja) * 2009-01-27 2010-09-09 Citizen Electronics Co Ltd 発光ダイオードの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203079A (ja) * 2005-01-21 2006-08-03 Sharp Corp 半導体装置および半導体装置の製造方法
WO2014002535A1 (ja) * 2012-06-29 2014-01-03 シャープ株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243910A (ja) * 2004-02-26 2005-09-08 Lintec Corp 半導体チップの製造方法
JP2010199565A (ja) * 2009-01-27 2010-09-09 Citizen Electronics Co Ltd 発光ダイオードの製造方法

Also Published As

Publication number Publication date
JP6482866B2 (ja) 2019-03-13
TW201635361A (zh) 2016-10-01
JP2016127116A (ja) 2016-07-11

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