TWI689621B - 導電性基板、電子裝置及顯示裝置之製造方法 - Google Patents

導電性基板、電子裝置及顯示裝置之製造方法 Download PDF

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TWI689621B
TWI689621B TW107125663A TW107125663A TWI689621B TW I689621 B TWI689621 B TW I689621B TW 107125663 A TW107125663 A TW 107125663A TW 107125663 A TW107125663 A TW 107125663A TW I689621 B TWI689621 B TW I689621B
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layer
conductive pattern
forming
base
pattern layer
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TW107125663A
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TW201910554A (zh
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大德高志
谷口晋
関映子
佐藤淳
堀川雄平
折笠誠
阿部寿之
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日商 Tdk 股份有限公司
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
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Abstract

本發明揭示一種製造具有基材及設置於基材之一個主面側之導電圖案的導電性基板之方法。該方法具備如下步驟:藉由壓印法形成具有露出基底層之底面與包含溝槽形成層之表面之側面的溝槽;及使金屬鍍層自露出於溝槽之底面之基底層生長,藉此形成導電圖案層。

Description

導電性基板、電子裝置及顯示裝置之製造方法
本發明係關於一種導電性基板、電子裝置及顯示裝置之製造方法。
於觸控面板或者顯示器之表面上會有安裝搭載有具有透明性與導電性之導電性基板之透明天線的情況。近來,伴隨觸控面板及顯示器大型化、多樣化,對於導電性基板要求較高之透明性與導電性並且還要求可撓性。先前之導電性基板例如於透明基材上具有藉由含有ITO(indium tin oxide,銦錫氧化物)、金屬箔、或者導電性奈米線(nanowire)之樹脂形成之形成了微細圖案之導電圖案層。
但是,ITO或者導電性奈米線為昂貴之材料。又,作為將微細之導電圖案層形成於基材上之方法一般為蝕刻,藉由蝕刻進行之方法必需曝光步驟、顯影步驟、蝕刻步驟、及剝離步驟等步驟,步驟數較多。根據此種理由,對於以低成本製作導電性基板而言有限度。
作為以低成本製造導電性基板之方法,於日本專利特開2016-164694號公報中揭示有如下方法:於樹脂製之透明基材上形成溝槽(trench),藉由蒸鍍法或者濺鍍法使銅等導電性材料填充至透明基材整個面上,並利用蝕刻去除溝槽內部以外之導電性材料而形成導電層。另一方面,於國際公開第2014/153895號中揭示有如下方法:於樹脂製之透明基材上形成溝槽,並使導電性材料填充於溝槽內部。
然而,具有填充溝槽之導電圖案層之先前之導電性基板有於被反覆彎曲時存在發生導電層之剝離或導電性降低之情況的問題。
本發明之目的在於提供一種可製造具有填充溝槽之導電圖案層並且抑制由彎曲引起之導電圖案層之剝離及導電性之降低的導電性基板之方法、及製造使用有該導電性基板之電子裝置以及顯示裝置之方法。
本發明之一個側面提供一種製造導電性基板之方法,上述導電性基板具有基材及設置於基材之一個主面側之導電圖案層。
第1態樣之製造導電性基板之方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出基底層之底面與包含溝槽形成層之表面之側面的溝槽;及使金屬鍍層自露出於溝槽之底面之基底層生長,藉此形成包含金屬鍍層且填充溝槽之導電圖案層。
第2態樣之製造導電性基板之方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出基底層之底面與包含溝槽形成層之表面之側面的溝槽;使觸媒吸附至露出於溝槽之底面之基底層;及使金屬鍍層自觸媒所吸附之基底層生長,藉此形成包含金屬鍍層且填充溝槽之導電圖案層。
於第1態樣及第2態樣中,較佳為以於導電圖案層之側面中之至少一部分與上述溝槽之側面之間形成間隙之方式使金屬鍍層生長。
第1態樣及第2態樣之方法亦可進而具備使導電圖案層之包含與溝槽之底面為相反側之面之表面之至少一部分黑化的步驟。
第1態樣及第2態樣之方法亦可進而具備形成覆蓋溝槽形成層及導電圖案層之與基材為相反側之面之至少一部分之保護膜的步驟。
導電圖案層亦可具有網目狀圖案。
本發明之另一個側面提供一種製造電子裝置之方法,上述電子裝置具備:具有基材及設置於基材之一個主面側之導電圖案層之導電性基板、以及電子零件。
本發明之另一個側面提供一種製造顯示裝置之方法,上述顯示裝置具備:具有基材及設置於基材之一個主面側之導電圖案層之導電性基板、以及發光元件。
一態樣之製造電子裝置之方法及製造顯示裝置之方法具備將發光元件安裝於藉由上述方法所獲得之導電性基板之步驟。
以下適當參照圖式對本發明之實施形態進行說明。但是,本發明並不限定於以下之實施形態。
[第1實施形態] 圖1係示意性地表示第1實施形態之製造導電性基板1A之方法之剖視圖。於本實施形態之方法中,首先,如圖1A所示,將含有觸媒之基底層3形成於膜狀之基材2之一個主面2a上。圖1A之步驟亦可為準備具備基材2及形成於基材2上之基底層3之積層體之步驟。
基材2較佳為透明基材,尤佳為透明樹脂膜。透明樹脂膜例如可為聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚萘二甲酸乙二酯(PEN)、環烯烴聚合物(COP)、或者聚醯亞胺(PI)之膜。或者,基材2亦可為玻璃基板或者Si晶圓等。
基材2之厚度可為10 μm以上、20 μm以上、或者35 μm以上,且可為500 μm以下、200 μm以下、或者100 μm以下。
基底層3含有觸媒及樹脂。樹脂可為硬化性樹脂,作為其例,可列舉胺基樹脂、氰酸酯樹脂、異氰酸酯樹脂、聚醯亞胺樹脂、環氧樹脂、氧雜環丁烷樹脂、聚酯、烯丙基樹脂、酚樹脂、苯并㗁𠯤樹脂、二甲苯樹脂、酮樹脂、呋喃樹脂、COPNA(condensed polynuclear aromatic,縮合多環多核芳香族)樹脂、矽樹脂、二環戊二烯樹脂、苯并環丁烯樹脂、環硫樹脂、烯-硫醇樹脂、聚甲亞胺樹脂、聚乙烯基苄基醚化合物、苊(acenaphthylene)、及包含不飽和雙鍵或環狀醚、乙烯醚等藉由紫外線而引起聚合反應之官能基之紫外線硬化樹脂等。
包含於基底層3之觸媒較佳為無電解鍍覆觸媒。無電解鍍覆觸媒可為選自Pd、Cu、Ni、Co、Au、Ag、Pd、Rh、Pt、In、及Sn之金屬,較佳為Pd。觸媒可為單獨1種或者亦可為2種以上之組合。通常,觸媒作為觸媒粒子分散於樹脂中。
基底層3中之觸媒之含量可將基底層總量作為基準而為3質量%以上、4質量%以上、或者5質量%以上,並且可為50質量%以下、40質量%以下、或者25質量%以下。
基底層3之厚度可為10 nm以上、20 nm以上、或者30 nm以上,並且可為500 nm以下、300 nm以下、或者150 nm以下。
將基底層3形成於基材2上之方法並無特別之限制,例如可為將含有觸媒、樹脂及視需要之溶劑之基底層形成用之硬化性樹脂組合物塗佈於基材2之主面2a上並使塗膜乾燥及/或硬化之方法。塗佈例如係使用棒式塗佈機進行。
接著,如圖1B所示,將溝槽形成層4形成於基底層3之與基材2為相反側之面3a上。圖1B之步驟亦可為準備依序具備基材2、基底層3、及溝槽形成層4之積層體5A之步驟。
溝槽形成層4較佳為透明之樹脂層。又,溝槽形成層4亦可為包含未硬化之光硬化性或者熱硬化性樹脂之層。作為構成溝槽形成層4之光硬化性樹脂及熱硬化性樹脂之例,可列舉丙烯酸系樹脂、胺基樹脂、氰酸酯樹脂、異氰酸酯樹脂、聚醯亞胺樹脂、環氧樹脂、氧雜環丁烷樹脂、聚酯、烯丙基樹脂、酚樹脂、苯并㗁𠯤樹脂、二甲苯樹脂、酮樹脂、呋喃樹脂、COPNA樹脂、矽樹脂、二環戊二烯樹脂、苯并環丁烯樹脂、環硫樹脂、烯-硫醇樹脂、聚甲亞胺樹脂、聚乙烯基苄基醚化合物、苊、及包含不飽和雙鍵或環狀醚、乙烯醚等利用紫外線引起聚合反應之官能基之紫外線硬化樹脂等。
溝槽形成層4之折射率(nd25)就提高導電性基板之透明性之觀點而言,較佳為小於基底層3之折射率,例如可為1.0以上,並且可為1.7以下、1.6以下、或者1.5以下。折射率能夠藉由反射分光膜厚計進行測定。
接著,如圖1C、圖1D所示,藉由使用具有凸部7a之模具7之壓印法形成溝槽(槽部)6。於該步驟中,使具有特定形狀之凸部7a之模具7藉由在箭頭A所示之方向上移動,從而壓入至溝槽形成層4(圖1C)。模具7亦可壓入直至凸部7a之前端到達基底層3。在此狀態下,於溝槽形成層4為包含未硬化之光硬化性或者熱硬化性樹脂之層之情形時使之硬化。於溝槽形成層4為包含光硬化性樹脂之層之情形時,藉由照射紫外線等光而使溝槽形成層4硬化。之後,取下模具7,藉此形成具有將模具7之凸部7a之形狀反轉之形狀的溝槽6(圖1D)。
如圖1D所示,溝槽6係由露出基底層3之底面6a、及包含圍繞底面6a之溝槽形成層4之表面的對向之側面6b、6c形成。溝槽6係以形成對應於後續步驟中形成之導電圖案層之圖案之方式在基底層3上延伸。亦可為了使基底層3露出於溝槽6之底面6a而於取下模具7之後藉由乾式蝕刻等蝕刻去除溝槽6內之殘存於基底層3上之溝槽形成層4。
模具7可由石英、Ni、紫外線硬化性液狀聚矽氧橡膠(PDMS)等形成。模具7之凸部7a之形狀即由模具7形成之溝槽6之形狀並無特別之限定,可如圖1D所示,以溝槽6之寬度自溝槽形成層4之與基底層3為相反側之表面4a向底面6a變窄之方式使側面6b、6c相對於底面6a傾斜,亦可使側面6b、6c相對於底面6a垂直。側面6b、6c亦可形成階差。
溝槽6之寬度及深度通常係設定為對應於在後續步驟中形成之導電圖案層之寬度及厚度。於本說明書中,所謂溝槽之寬度係指與溝槽延伸之方向垂直之方向上之最大寬度。溝槽之深度相對於溝槽之寬度之比可與後述之導電圖案層之縱橫比相同。
接著,如圖1E所示,形成填充溝槽6之導電圖案層8。導電圖案層8可藉由使金屬鍍層自基底層3生長之無電解鍍覆法形成。導電圖案層8既可為由單一之金屬鍍層構成之層,亦可由金屬種類不同之複數金屬鍍層構成。例如,導電圖案層8亦可具有作為形成於基底層3上之金屬鍍層之晶種層、及作為形成於晶種層之與基底層3為相反側之面上之金屬鍍層的1層以上之上部金屬鍍層。藉由使導電圖案層8為將基底層作為起點形成之金屬鍍層,可獲得導電圖案層8與基底層3之較高之密接性。藉此,於導電性基板反覆彎曲時,能夠抑制導電圖案層8自基底層3剝離,且維持良好之導電性。
作為導電圖案層8之金屬鍍層例如包含選自銅、鎳、鈷、鈀、銀、金、鉑及錫之至少1種金屬,較佳為包含銅。導電圖案層8於維持適當之導電性之範圍內亦可進而包含磷等非金屬元素。
於導電圖案層8具有晶種層及上部金屬鍍層之情形時,構成晶種層之金屬與構成上部金屬鍍層之金屬既可相同亦可不同,例如,可晶種層包含鎳且上部金屬鍍層包含銅。上部金屬鍍層亦可由形成於晶種層上之銅鍍層與形成於銅鍍層上之包含金或者鈀之最上層構成。
藉由將形成有溝槽6之積層體5A浸漬於含有金屬離子之無電解鍍覆液中,從而能夠以包含於基底層3中之觸媒作為起點形成作為導電圖案層8之金屬鍍層。藉由形成填充溝槽6之導電圖案層8,從而能夠獲得導電性基板1A。
無電解鍍覆液包含構成導電圖案層8之金屬之離子。無電解鍍覆液亦可進而含有磷、硼、鐵等。
使積層體5A浸漬於無電解鍍覆液時之無電解鍍覆液之溫度例如可為40~90℃。又,無電解鍍覆液之浸漬時間視導電圖案層8之厚度等而有所不同,例如為10~30分鐘。
導電圖案層8係以形成對應於溝槽6之圖案之方式於基底層3上延伸。導電圖案層8之厚度既可實質上與溝槽形成層4之厚度一致,亦可導電圖案層8之厚度相對於溝槽形成層4之厚度之比落於0.8~1.2之範圍內。
導電圖案層8之寬度可為1 μm以上、10 μm以上、或者20 μm以上,且可為90 μm以下、70 μm以下、或者30 μm以下。於本說明書中,所謂導電圖案層之寬度係指垂直於導電圖案層之延伸方向之方向上之最大寬度。
導電圖案層8之寬度就提高導電性基板之透明性之觀點而言,可為0.3 μm以上、0.5 μm以上、或者1.0 μm以上,且可為5.0 μm以下、4.0 μm以下、或者3.0 μm以下。
導電圖案層8之厚度可為0.1 μm以上、1.0 μm以上、或者2.0 μm以上,且可為10.0 μm以下、5.0 μm以下、或者3.0 μm以下。導電圖案層8之寬度及厚度可藉由變更模具7之設計且變更溝槽6之寬度及厚度而進行調整。
導電圖案層8之縱橫比可為0.1以上、0.5以上、或者1.0以上,且可為10.0以下、7.0以下、或者4.0以下。藉由將導電圖案層8之縱橫比設為上述範圍,從而能夠進一步提高導電圖案8對基底層3之密接性,並且能夠亦進一步提高導電性。所謂導電圖案層之縱橫比係指導電圖案層之厚度相對於導電圖案層之寬度之比(厚度/寬度)。
具有晶種層及上部金屬鍍層之導電圖案層能夠藉由包括使晶種層形成於基底層上及使上部金屬鍍層形成於晶種層上的方法形成。藉由將形成有溝槽6之積層體5A浸漬於晶種層形成用之無電解鍍覆液,從而以包含於基底層3中之觸媒作為起點將金屬鍍層作為晶種層形成。之後,藉由將具有晶種層之積層體浸漬於導電層形成用之無電解鍍覆液中,從而能夠形成上部金屬鍍層。亦可在形成上部金屬鍍層之前使觸媒吸附於晶種層,以吸附於晶種層之觸媒作為起點形成上部金屬鍍層。
晶種層之厚度可為10 nm以上、30 nm以上、或者50 nm以上,且可為500 nm以下、300 nm以下、或者100 nm以下。
導電圖案層8較佳為以在其側面8b、8c之至少一部分與溝槽6之側面6b及/或6c之間形成間隙方式形成。藉此,能夠更加有效地抑制導電性基板1A彎曲時之導電圖案層8之損傷。間隙較佳為形成於導電圖案層8之側面8b及8c與溝槽6之對向之側面6b及6c兩者之間。間隙之寬度可為1 nm以上、5 nm以上、或者10 nm以上,且可為150 nm以下、125 nm以下、或者100 nm以下。所謂間隙之寬度係指垂直於電圖案層8之延伸方向之方向上之導電圖案層8與溝槽6之距離之最大值。藉由使金屬鍍層自基底層3或者基底層3上之晶種層生長,從而能夠容易地使間隙形成於導電圖案層8與溝槽6之側面6b、6c之間。
導電圖案層8例如可包含沿著一定方向延伸之複數個線狀部,亦可形成網目狀之圖案。
本實施形態中之製造導電性基板之方法亦可視需要進而具備使導電圖案層8之表面之至少一部分黑化之步驟。例如,亦可使導電圖案層8之與溝槽6之底面6a為相反側之面8a(以下有時稱作導電圖案層之上表面8a)、導電圖案層8之溝槽6之底面6a側之面、或者該等兩者黑化。又,亦可使導電圖案層8之側面8b、8c黑化。此處,所謂「使表面黑化」意指以對入射至該表面之光之正反射率降低之方式加工表面。
使導電圖案層8之表面黑化之方法並無特別之限制,例如可列舉使表面粗化之方法、及利用較原先表面吸收更多光之層、換言之較原先表面黑之層(以下稱為「黑化層」)覆蓋原先表面之方法。黑化層既可為使用黑色金屬鍍覆用之鍍覆液形成之黑色金屬鍍層,亦可為藉由RAYDENT處理(註冊商標)形成之黑色金屬鍍層。黑化層通常係作為構成導電圖案層8之一部分之導電層設置。
作為利用黑色金屬鍍覆用之鍍覆液形成之黑色金屬鍍層,可列舉黑色鎳鍍層、黑色鉻鍍層、鋅鍍層之黑色鉻酸鹽、黑色銠鍍層、黑色釕鍍層、錫-鎳-銅之合金鍍層、錫-鎳之合金鍍層、置換鈀鍍層。
導電圖案層8之底面6a側之表面例如可藉由在形成溝槽6之後將黑色金屬鍍層(例如黑色鎳鍍層)作為晶種層形成於基底層3上,並且於晶種層上形成上部金屬鍍層而黑化。導電圖案層8之與底面6a為相反側之面8a可藉由在形成導電圖案層8之後形成覆蓋面8a之黑色金屬鍍層而黑化。於在導電圖案層8之側面8b、8c與溝槽6之側面6b、6c之間形成有間隙之情形時,多數情況下藉由浸漬於黑色金屬鍍覆用之鍍覆液而形成覆蓋導電圖案層8之與溝槽6之底面6a為相反側之面8a並且覆蓋導電圖案層8之側面8b、8c的黑色金屬鍍層。
黑化層(黑色金屬鍍層之膜)之厚度可為10 nm以上、30 nm以上、或50 nm以上,且可為150 nm以下、125 nm以下、或者100 nm以下。
在藉由使表面粗化之方法使表面黑化之情形時,以表面粗糙度Ra較佳成為15 nm以上之方式使表面粗化。Ra更佳為60 nm以下。Ra可藉由掃描探針顯微鏡(SPM)進行測定。粗化可藉由利用酸處理等粗化導電圖案層8表面之方法或者以導電圖案層8之表面變粗之方式形成導電圖案層8之方法等進行。
本實施形態中之製造導電性基板之方法亦可視需要進而具備形成覆蓋溝槽形成層4及導電圖案層8之與基材2為相反側之面之至少一部分之保護膜的步驟。保護膜例如可包含樹脂及填料。作為保護膜之樹脂之例,可列舉胺基樹脂、異氰酸酯樹脂、矽樹脂、丙烯酸系樹脂、聚碳酸酯樹脂、氟樹脂、及包含不飽和雙鍵或環狀醚及乙烯醚等利用紫外線引起聚合反應之官能基之紫外線硬化樹脂等。作為保護膜之填料之例,可列舉氧化矽、氧化鋯、氧化鈦、氧化鋁、氟化鎂氧化鋅、氧化銻、摻磷氧化錫、摻銻氧化錫、摻錫氧化銦、Ag奈米膠體等。保護膜例如可藉由將保護膜形成用之樹脂組合物塗佈於溝槽形成層4及導電圖案層8之與基材2為相反側之面並且視需要使塗膜乾燥及/或硬化而形成。於在導電圖案層8與溝槽6之側面6b、6c之間形成有間隙之情形時,保護膜亦可填充該間隙。
保護膜之厚度可為10 nm以上、50 nm以上、或者100m以上,且可為5000 nm以下、3000 nm以下、或者1000 nm以下。
保護膜之折射率就導電性基板之透明性之觀點而言可為1.0以上、或者1.3以上,且可為1.6以下、或者1.5以下。保護膜之折射率較佳為小於溝槽形成層4之折射率。保護膜之折射率例如可藉由增減填料之含量而進行調整。
本實施形態之方法在能夠容易地形成一定寬度之導電圖案層之方面亦優異。圖2係表示具有形成有網目狀圖案之導電圖案層之導電性基板之例的局部放大圖。於藉由本實施形態之方法形成之導電性基板之情形時,如圖2A所例示,導電圖案層8之寬度即使於2根導電圖案層8之交點附近之區域P亦不會大幅變化,容易維持一定寬度。與此相對,若於藉由蝕刻形成導電圖案層之先前方法之情形時,則會有如圖2B所例示,導電圖案層8'之寬度於2根導電圖案層8'之交點附近之區域Q變大之情況。導電圖案層8之寬度於交點附近之區域不會變大就全光線透過率變高之方面而言有利。導電圖案層8之寬度偏差較小就全光線透過率之偏差較小之方面而言有利。
進而,本實施形態之方法因無需藉由蝕刻去除多餘之導電材料,故而可削減步驟數。
[第2實施形態] 圖3係示意性地表示第2實施形態之製造導電性基板1B之方法之剖視圖。有時對於與圖1之第1實施形態之方法對應之構成及部分標註相同之符號,並省略重複之說明。
本實施形態之方法於形成溝槽6之步驟之後,包含使觸媒10吸附至露出於溝槽6之底面6a之基底層9之步驟(圖3E),使作為導電圖案層8之金屬鍍層自觸媒10所吸附之基底層9生長,於該方面與第1實施形態之方法不同。
如圖3A所示,形成於基材2之主面2a上之基底層9通常為不含觸媒但能夠使觸媒吸附之層。基底層9可由聚乙炔、聚并苯、聚對苯、聚對苯乙炔、聚吡咯、聚苯胺、聚噻吩、及該等之各種衍生物等樹脂形成。吸附至基底層9之觸媒可為與第1實施形態相同之無電解鍍覆觸媒。例如,藉由使形成有具有露出基底層9之底面6a之溝槽6的積層體浸漬於含有觸媒之水溶液中,從而能夠使觸媒吸附至基底層9。其他步驟與第1實施形態相同。
[顯示裝置] 藉由將發光元件安裝於利用以上之方法所製造之導電性基板,從而能夠製造具備該導電性基板及發光元件之顯示裝置。上述之導電性基板因抑制導電圖案層自基底層之剝離,故而具備該導電性基板之顯示裝置能夠被製造成薄如布或紙,可用作能夠彎折或折圓之可撓性之顯示裝置(display)。此種可撓性之顯示裝置能夠進行小型化、輕量化,能夠提高收納性、設計性。
圖4係示意性地表示製造顯示裝置之方法之一實施形態之剖視圖。於該方法中,首先,如圖4A所示,準備發光元件40與導電性基板1A。發光元件40具備發光部41、設置於發光部41之一個主面41a上之正極42、及與正極42空開間隔地設置於主面41a上之負極43。以下,有時將正極42及負極43統稱為電極42、43。發光元件40可為能夠發出紅色、綠色或者藍色光之元件。發光元件40例如可為發光二極體(LED)。於本實施形態之情形,導電性基板1A中之導電圖案層8包含沿著一定方向延伸之複數個線狀部81、82。
發光元件40之形狀(發光部41之形狀)並無特別限制,例如可為大致矩形狀(長方形狀、正方形狀等)。發光元件40之尺寸可適當設定,但是於發光元件40為矩形狀之情形時,發光元件40之寬度就進一步提高顯示裝置之解像度之觀點而言,較佳為100 μm以下、80 μm以下、60 μm以下、30 μm以下、或者20 μm以下。此情形時之發光元件40之長度較佳為50 μm以下、40 μm以下、30 μm以下、20 μm以下、或者10 μm以下。發光元件40之寬度可為5 μm以上、10 μm以上、或者20 μm以上。此情形時之發光元件40之長度可為5 μm以上、或者10 μm以上。於後述之步驟中將發光元件40安裝於導電性基板1A時,發光元件40之寬度設定為對應於導電圖案層8之寬度之方向。發光元件40之長度設定為沿著導電圖案層8之延伸方向之方向。
接著,如圖4B所示,將發光元件40安裝於導電性基板1A。該步驟包括將發光元件40之電極42、43連接於導電性基板1A之導電圖案層8。此時,藉由分別使發光元件40之正極42及負極43接觸於導電圖案層8之相鄰之2個線狀部81、82,從而使發光元件40與導電圖案層8電性連接。藉此,能夠獲得發光元件40安裝於導電性基板1A之顯示裝置50A。
圖5係示意性地表示製造顯示裝置之方法之其他實施形態之剖視圖。於該方法中,將發光元件40安裝於導電性基板1A之步驟包括將連接部形成於導電性基板1A中之導電圖案層8上、及經由連接部將發光元件40連接於導電圖案層8,就該方面而言與上述之實施形態不同。
於該方法中,首先,如圖5A、圖5B所示,將連接部44形成於導電性基板1A中之導電圖案層8上。連接部44可以與導電圖案層8之上表面8a上之至少一部分接觸之方式形成。
連接部44可藉由使用包含焊料合金之微小球而形成於導電圖案層8之上表面8a上,亦可印刷包含焊料合金之膏來形成。連接部44亦可藉由使金屬鍍層自導電圖案層8生長之無電解鍍覆法來形成。於連接部44藉由無電解鍍覆法形成之情形時,連接部44既可包含錫、銀、銅、鉍、銦等作為構成材料,亦可包含由該等之任意2種以上之材料構成之合金。於本實施形態中,連接部44較佳為藉由包含焊料合金之微小球或者膏來形成。
關於連接部44之尺寸,只要為能夠使發光元件40中之電極42、43接觸之大小,則可適當設定。例如,如圖5B所示,連接部44之寬度亦可與導電圖案層8之寬度相同地形成。連接部44亦可形成為小於導電圖案層8之寬度而使導電圖案層8之上表面8a之一部分露出。
接著,如圖5C所示,藉由使發光元件40之電極42、43接觸於連接部44之與導電圖案層8接觸之面之相反側之面44a,從而經由連接部44使發光元件40連接於導電性基板1A。此時,藉由使發光元件40中之正極42及負極43接觸於相鄰之2個連接部44,從而電性連接發光元件40。藉此,能夠獲得發光元件40安裝於導電性基板1A之顯示裝置50B。
圖6係示意性地表示包括經由連接部44使發光元件40連接於導電性基板1A的製造顯示裝置之方法之一個變化例之剖視圖。根據本變化例,因能夠對於導電性基板1A更良好且容易地安裝發光元件40,故而於將更小之發光元件40安裝於導電性基板1A之情形時可尤佳地使用。
於該方法中,首先,如圖6A、圖6B所示,將密接層45形成於導電性基板1A之導電圖案層8上。密接層45亦可形成於導電圖案層8之上表面8a上之至少一部分。藉由形成密接層45,從而於將後述之絕緣層形成於溝槽形成層4上及導電圖案層8上時,能夠抑制絕緣層之剝離。
密接層45較佳為藉由使金屬鍍層自導電圖案層8生長之無電解鍍覆法形成。密接層45就提高與後述之UBM(under barrier metal,底部阻擋金屬層)層、進而與設置於UBM層上之連接部44及發光元件40之密接性之觀點而言,較佳為包含選自鎳及鎳合金所組成群中之至少1種作為構成材料。密接層45更佳為除了選自鎳及鎳合金所組成之群中之至少1種之外亦含有選自鋅及磷所組成之群中之至少1種。
於密接層45中,較佳為與接觸於導電圖案層8之面為相反側之面45a(以下亦稱為密接層45之上表面45a)被粗化。藉由使密接層45之上表面45a粗化,從而利用投錨效應使後述之絕緣層更容易地密接。
使密接層45之上表面45a粗化之方法係藉由利用酸處理等使鍍覆後之密接層45之上表面45a粗化之方法或者在以密接層45之表面變粗糙之方式調整鍍覆液之後形成密接層45之方法等進行。
密接層45之表面粗糙度Ra就進一步提高與後述之絕緣層之密接性之觀點而言,較佳為0.1 μm以上,更佳為0.3 μm以上,進而較佳為0.5 μm以上。Ra就確保顯示裝置之強度之觀點而言,較佳為1 μm以下,更佳為0.8 μm以下,進而較佳為0.7 μm以下。Ra能夠藉由與上述之黑化層中說明之方法相同之測定方法進行測定。
密接層45之厚度就獲得適宜之表面粗糙度Ra之觀點而言,較佳為0.1 μm以上,更佳為0.5 μm以上,進而較佳為1.0 μm以上。密接層45之厚度可為2.0 μm以下、1.8 μm以下、或者1.5 μm以下。
接著,如圖6C所示,形成覆蓋溝槽形成層4之與基底層3為相反側之表面4a,且具有使密接層45之上表面45a露出之開口部的絕緣層46。絕緣層46較佳為以覆蓋溝槽形成層4之表面4a與密接層45之一部分(例如密接層45之上表面45a之端部)之方式形成。
絕緣層46係由具有絕緣性之素材形成。具有絕緣性之素材可為無機材料或者樹脂。作為無機材料,例如可列舉SiO2 、SiN等含有矽之化合物。作為樹脂,可列舉環氧樹脂、聚醯亞胺等。
如圖6D所示,將UBM層(底部阻擋金屬層)47形成於絕緣層46之開口部內露出之密接層45之上表面45a上。UBM層47較佳為藉由使金屬鍍層自密接層45生長之無電解鍍覆法形成。UBM層47可包含選自鎳、鈷、鐵及銅當所組成之群中之至少1種金屬。UBM層47亦可進而包含磷等非金屬元素。UBM層47較佳為含有鎳,或者含有鎳及磷。
如圖6E所示,將連接部44形成於UBM層47之與導電性基板1A為相反側之面47a上。連接部44之構成材料及形成方法亦可與上述之實施形態中之構成材料及形成方法相同,但是於本變化例中,就安裝更小之發光元件40之觀點而言,連接部44較佳為藉由使金屬鍍層自UBM層47生長之無電解鍍覆法形成。連接部44較佳為包含錫或者其合金作為構成材料。形成於UBM層47上之連接部44亦可其一部分接觸於絕緣層46之表面。
如圖6F所示,將發光元件40連接於形成之連接部44。藉此,能夠獲得發光元件40經由連接部44、UBM層47、及密接層45而連接於導電性基板1A之導電圖案層8的顯示裝置50C。即,藉由包括形成密接層45、絕緣層46、UBM層47及連接部44、及將發光元件40連接於連接部44的步驟而將發光元件40安裝於導電性基板1A。
圖7係示意性地表示藉由圖4~圖6所示之方法而獲得之顯示裝置50(50A~50C)之主要部分之俯視圖。於圖7所示之顯示裝置5中,複數個發光元件40(40a、40b、及40c)跨及導電性基板1A上之導電圖案層8之相鄰之2個線狀部81、82並且沿著該等線狀部之延伸方向L排列。發光元件40可包含具有紅色之發光部之發光元件40a、具有綠色之發光部之發光元件40b、及具有藍色之發光部之發光元件40c,該等發光元件40a、40b、及40c可以任意之順序配置。作為鄰接之發光元件40(40a、40b、及40c)彼此之間隔,例如導電圖案層8之寬度方向上之間隔D1 可為400 μm以下,導電圖案層8之延伸方向L上之間隔D2 可為200 μm以下。
於上述之製造顯示裝置50之方法中,亦可進而具備設置覆蓋發光元件40之露出部分之密封部之步驟。密封部例如可由聚矽氧樹脂、環氧樹脂、烯烴樹脂等樹脂形成。
對於藉由第2實施形態之方法製造之導電性基板1B,亦能夠藉由與第1實施形態相同之方法安裝發光元件,能夠製造顯示裝置。
[電子裝置] 於其他之實施形態中,亦可於藉由上述之方法製造之導電性基板上安裝發光元件以外之電子零件。作為發光元件以外之電子零件,可列舉例如電容器、電感器、熱敏電阻等無源零件、半導體元件、連接器等。藉此,除顯示裝置以外,亦能夠製造於藉由上述方法製造之導電性基板上具備電子零件之電子裝置。
[實施例] 以下,藉由實施例具體地說明本發明,但是本發明並不限定於該等實施例。
[實施例1] 準備含有20質量%之Pd粒子與異氰酸酯樹脂之基底層形成用之含觸媒之樹脂。利用棒式塗佈機將該含觸媒之樹脂塗佈於作為透明基材之PET膜(厚度100 μm)上。將塗膜加熱至80℃使之硬化,藉此形成基底層(厚度100 nm)。之後,使用棒式塗佈機將紫外線硬化性之透明丙烯酸系低聚物塗佈於基底層上而形成溝槽形成層(厚度2 μm)。
準備具有形成網目狀圖案之寬度1 μm之凸部之Ni製模具。將該模具按壓至溝槽形成層,使模具之凸部之前端到達基底層。於該狀態下,藉由紫外線照射使溝槽形成層硬化。藉此,形成具有露出基底層之底面之溝槽。溝槽之寬度為1 μm,深度為2 μm,相鄰之溝槽之間隔為100 μm。
將具有形成了溝槽之溝槽形成層之積層體浸漬於含有界面活性劑之鹼性之脫脂液中5分鐘。之後,利用純水洗淨自脫脂液中取出之積層體。將洗淨後之積層體浸漬於含有硫酸鎳及次磷酸鈉之無電解鍍覆液中3分鐘,使包含Ni與P之作為晶種層(厚度100 nm)之金屬鍍層自露出於溝槽之底面之基底層生長。利用純水洗淨自無電解鍍覆液中取出之積層體。接著,於將形成有晶種層之積層體浸漬於含有Pd之水溶液中5分鐘之後利用純水洗淨,而使作為觸媒之Pd粒子吸附於晶種層。之後,藉由將積層體浸漬於含有硫酸銅及福馬林之無電解鍍覆液中15分鐘,從而使填充溝槽之Cu鍍層(上部金屬鍍層)於晶種層上生長。利用純水洗淨自無電解鍍覆液取出之積層體,以80℃乾燥3分鐘,從而獲得具有形成網目狀之圖案,包含晶種層及Cu鍍層之導電圖案層的導電性基板。於該導電性基板中,導電圖案層之寬度W為1 μm,厚度為2 μm,縱橫比(厚度/寬度)為2。相鄰之導電圖案層彼此之間隔S為200 μm。對於獲得之導電性基板使用截面拋光機,切割出導電圖案層之截面,藉由使用掃描電子顯微鏡進行觀察而確認到在溝槽之側面與導電圖案層之側面之間形成有間隙。
[實施例2~5] 除了將導電圖案層之寬度W(溝槽之寬度)及導電圖案層之厚度(溝槽之深度)變更為表1所記載之值之外,以與實施例1相同之方法製作導電性基板。
[實施例6~9] 除了將導電圖案層之厚度(溝槽之深度)變更為表1所記載之值之外,以與實施例1相同之方法製作導電性基板。
[比較例1] 按照圖8所示之先前之製造方法製作不具備基底層之導電性基板。首先,將紫外線硬化性之透明丙烯酸系低聚物塗佈於與實施例相同之PET膜(基材2),形成溝槽形成層4(厚度2 μm)。將具有形成網目狀圖案之寬度1 μm凸部之模具按壓至溝槽形成層4,使凸部之前端到達基材2。於此狀態下,藉由利用紫外線照射使溝槽形成層4硬化,從而獲得形成有具有露出基材2之底面之溝槽6的積層體5C(圖8A)。接著,藉由濺鍍法形成覆蓋溝槽形成層4之表面4a及底面6a整體之包含Cu之晶種層11(圖8B)。之後,藉由將積層體5C浸漬於含有硫酸銅及福馬林之無電解鍍覆液中,從而使Cu鍍層自晶種層11生長,形成填充溝槽6並且覆蓋溝槽形成層4整體之Cu鍍層8A(圖8C)。之後,藉由蝕刻去除Cu鍍層8A中之填充溝槽6內部之部分以外之部分(圖8D),從而製作具有導電圖案層8之比較例1之導電性基板1C。對於獲得之導電性基板使用截面拋光機,切割出導電圖案層之截面,藉由使用掃描電子顯微鏡進行觀察而確認到導電圖案層8與溝槽6之側面6b、6c密接,於該等之間未形成間隙。
<彎曲試驗> 準備長150 mm、寬50 mm之各導電性基板之試樣。將該試樣供於使用圖9所示之耐彎曲性試驗機之遵照JISC5016之彎曲試驗。即,藉由將導電性基板1之端部12固定於固定部13,並且使導電性基板1沿著彎曲部14之圓形之周面(曲率半徑d:5 mm),從而將導電性基板1以彎曲之方式配置。之後,使與端部12為相反側之端部15沿著箭頭B所示之方向往返。將往返之移動距離設為30 mm,將往返之週期設為150次/分鐘,反覆使端部15往返1分鐘。
<導電性之評價(表面電阻之測定)> 使用非接觸式電阻測定器EC-80P[NAPSON股份有限公司製造],分別對於彎曲試驗前後之導電性基板測定表面電阻。測定係對於導電性基板之表面
Figure 02_image001
20 mm之區域進行。基於測定結果,按以下之4階之等級來評價導電性。於等級A之情形時,可謂導電性最優異。 等級A:表面電阻未達5 Ω/□ 等級B:表面電阻為5 Ω/□以上且未達10 Ω/□ 等級C:表面電阻為10 Ω/□以上且未達15 Ω/□ 等級D:表面電阻為15 Ω/□以上
<密接性之評價> 利用掃描電子顯微鏡觀察彎曲試驗後之導電性基板之截面,確認導電圖案層有無自基底層或者基材剝離。
<透明性之評價> 使用霧度計NDH5000(日本電色工業股份有限公司製造)並遵照JISK7136來測定導電性基板之全光線透過率。對測定結果,基於以下之3階之等級來評價透明導電性基板之透明性。於等級A之情形時,可謂透明性最優異。 等級A:導電性基板之全光線透過率/基材之全光線透過率×100%=98%以上 等級B:導電性基板之全光線透過率/基材之全光線透過率×100%=96%以上且未達98% 等級C:導電性基板之全光線透過率/基材之全光線透過率×100%=未達96%
[表1]
Figure 107125663-A0304-0001
如表1所示,可知於實施例1~9之導電性基板中,於彎曲試驗後,導電圖案層之剝離得到抑制,並且維持了良好之導電性。
[實施例10~12] 以與實施例1相同之方式製作複數個導電性基板。將該等浸漬於含有Pd之水溶液中5分鐘之後利用純水洗淨,使作為觸媒之Pd粒子吸附於導電圖案層之表面。之後,將導電性基板浸漬於黑色Ni鍍覆用之無電解鍍覆液中3分鐘,作為導電圖案層之與溝槽之底面為相反側及溝槽之側面側之最表層,形成了黑色Ni鍍膜。利用純水洗淨自無電解鍍覆液中取出之各導電性基板。進一步對黑色Ni鍍膜進行酸處理,藉由調整酸處理之時間而將黑Ni鍍膜之表面粗糙度Ra調整為15 nm(實施例10)、58 nm(實施例11)或者65 nm(實施例12)。Ra係使用掃描探針顯微鏡於1 μm之視野中測得。實施例1之導電圖案層之Ra為8 nm。
<導電性之評價、透過率之測定> 藉由與上述之方法相同之方法對於實施例10~12及實施例1之導電性基板評價透明性及導電性。如表2所示,可知於Ra為15~60 nm時,透明性及導電性特別優異。
[表2]
Figure 107125663-A0304-0002
[實施例13~15] 以與實施例1相同之方式製作複數個導電性基板。利用刮刀將保護膜形成用之硬化性樹脂組合物塗佈於該等導電性基板之溝槽形成層及導電圖案層之表面。於使塗膜乾燥之後藉由紫外線照射而使之硬化,從而形成覆蓋溝槽形成層及導電圖案之保護膜(厚度100 nm)。此處所使用之保護膜形成用之硬化性樹脂組合物含有填料(氧化矽)及氟樹脂。藉由變更填料之含量,從而以保護膜之折射率成為表3所記載之值之方式進行調整。
<透明性之評價> 藉由與上述之方法相同之方法對於實施例13~15及實施例1之導電性基板測定導電性基板之透明性。將結果表示於表3中。如表3所示,可知於保護膜之折射率大於空氣之折射率1.0且小於溝槽形成層之折射率之情形時,透明性特別優異。
[表3]
Figure 107125663-A0304-0003
根據本發明,能夠製造一種具有填充溝槽之導電圖案層並且抑制由彎曲引起之導電圖案層之剝離及導電性之降低的導電性基板。與包括利用蝕刻去除導電層之方法相比,容易對導電圖案層賦予適度大之厚度,因此容易獲得良好之導電性,本發明於該方面亦優異。
進而,本發明亦能夠提供一種製造於導電性基板中導電圖案層之剝離得到抑制之電子裝置或顯示裝置之方法。尤其是於顯示裝置中,近年來,正進行具備發光二極體(LED)等發光元件之顯示裝置(例如LED顯示器)之開發。於液晶顯示器(LCD)中,係藉由透過型液晶控制背光之光,與此相對,於LED顯示器中,係使用作為自然發光元件之發光二極體構成像素。藉此,LED顯示器具有高亮度、高壽命、高視角之特徵。
於具備發光元件之顯示裝置中,為了提高其解像度,只要減小發光元件自身即可。但是,若發光元件較小,則必須形成微細之導電圖案層,因此有導電圖案層容易發生剝離,且難以確保導電性之傾向。根據本發明,即使於發光元件較小之情形時,亦能夠容易地製造導電性基板中之導電圖案層不易發生剝離,進而發光元件與導電性基板之密接性亦優異的顯示裝置。
1‧‧‧導電性基板1A‧‧‧導電性基板1B‧‧‧導電性基板1C‧‧‧導電性基板2‧‧‧基材2a‧‧‧基材之主面3‧‧‧基底層3a‧‧‧基底層之與基材為相反側之面4‧‧‧溝槽形成層4a‧‧‧溝槽形成層之與基底層為相反側之表面5A‧‧‧積層體5C‧‧‧積層體6‧‧‧溝槽6a‧‧‧溝槽之底面6b‧‧‧溝槽之側面6c‧‧‧溝槽之側面7‧‧‧模具7a‧‧‧凸部8‧‧‧導電圖案層8'‧‧‧導電圖案層8a‧‧‧導電圖案層之上表面8A‧‧‧Cu鍍層8b‧‧‧導電圖案層之側面8c‧‧‧導電圖案層之側面9‧‧‧基底層11‧‧‧晶種層12‧‧‧導電性基板之端部13‧‧‧固定部14‧‧‧彎曲部15‧‧‧導電性基板之另一端部40‧‧‧發光元件40a‧‧‧發光元件40b‧‧‧發光元件40c‧‧‧發光元件41‧‧‧發光部41a‧‧‧發光部之一個主面42‧‧‧正極43‧‧‧負極44‧‧‧連接部44a‧‧‧連接部之與導電圖案層接觸之面之相反側之面45‧‧‧密接層45a‧‧‧密接層之與接觸於導電圖案層之面為相反側之面46‧‧‧絕緣層47‧‧‧UBM層47a‧‧‧UBM層之與導電性基板為相反側之面50‧‧‧顯示裝置50A‧‧‧顯示裝置50B‧‧‧顯示裝置50C‧‧‧顯示裝置81‧‧‧線狀部82‧‧‧線狀部A‧‧‧箭頭B‧‧‧箭頭d‧‧‧曲率半徑D1‧‧‧發光元件於導電圖案層之寬度方向上之間隔D2‧‧‧發光元件於導電圖案層之延伸方向L上之間隔L‧‧‧線狀部之延伸方向P‧‧‧2根導電圖案層之交點附近之區域Q‧‧‧2根導電圖案層之交點附近之區域
圖1A~E係示意性地表示製造第1實施形態之導電性基板之方法之剖視圖。 圖2A係表示一實施形態之導電性基板之局部放大圖,B係表示先前之導電性基板之一例之局部放大圖。 圖3A~F係示意性地表示第2實施形態之製造導電性基板之方法之剖視圖。 圖4A、B係示意性地表示製造顯示裝置之方法之一實施形態之剖視圖。 圖5A~C係示意性地表示製造顯示裝置之方法之其他實施形態之剖視圖。 圖6A~F係示意性地表示圖5所示之方法之變化例之剖視圖。 圖7係示意性地表示藉由圖4~圖6所示之方法獲得之顯示裝置之主要部分之俯視圖。 圖8A~D係表示先前之導電性基板之製造方法之步驟圖。 圖9係耐彎曲性試驗機之概略圖。
1‧‧‧導電性基板
1A‧‧‧導電性基板
2‧‧‧基材
2a‧‧‧基材之主面
3‧‧‧基底層
3a‧‧‧基底層之與基材為相反側之面
4‧‧‧溝槽形成層
4a‧‧‧溝槽形成層之與基底層為相反側之表面
5A‧‧‧積層體
6‧‧‧溝槽
6a‧‧‧溝槽之底面
6b‧‧‧溝槽之側面
6c‧‧‧溝槽之側面
7‧‧‧模具
7a‧‧‧凸部
8‧‧‧導電圖案層
8a‧‧‧導電圖案層之上表面
8b‧‧‧導電圖案層之側面
8c‧‧‧導電圖案層之側面
A‧‧‧箭頭

Claims (16)

  1. 一種製造導電性基板之方法,上述導電性基板具有基材及設置於上述基材之一個主面側之導電圖案層,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽,其中上述基底層包含分散於樹脂中之觸媒;及使金屬鍍層自露出於上述溝槽之底面之上述基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層。
  2. 一種製造導電性基板之方法,上述導電性基板具有基材及設置於上述基材之一個主面側之導電圖案層,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽;使觸媒吸附至露出於上述溝槽之底面之上述基底層;及使金屬鍍層自上述觸媒所吸附之基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層,其中上述基底層係由聚乙炔、聚并苯、聚對苯、聚對苯乙炔、聚吡咯、聚苯胺、聚噻吩、及該等之各種衍生物之樹脂形成,且上述溝槽形成層包含光硬化性或熱硬化性樹脂。
  3. 如請求項1或2之方法,其中以於上述導電圖案層之側面中之至少一部分與上述溝槽之側面之間形成間隙之方式使上述金屬鍍層生長。
  4. 如請求項1或2之方法,其進而具備使上述導電圖案層之包含與上述溝槽之底面為相反側之面之表面黑化的步驟。
  5. 如請求項1或2之方法,其進而具備形成覆蓋上述溝槽形成層及上述導電圖案層之與上述基材為相反側之面之至少一部分之保護膜的步驟。
  6. 如請求項1或2之方法,其中上述導電圖案層形成網目狀之圖案。
  7. 一種製造電子裝置之方法,上述電子裝置具備:具有基材及設置於上述基材之一個主面側之導電圖案層之導電性基板、以及電子零件,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽,其中上述基底層包含分散於樹脂中之觸媒;使金屬鍍層自露出於上述溝槽之底面之上述基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層;及將上述電子零件安裝於具有上述基材及上述導電圖案層之上述導電性基板。
  8. 一種製造電子裝置之方法,上述電子裝置具備:具有基材及設置於上述基材之一個主面側之導電圖案層之導電性基板、以及電子零件,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽;使觸媒吸附至露出於上述溝槽之底面之上述基底層;使金屬鍍層自上述觸媒所吸附之基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層;及將上述電子零件安裝於具有上述基材及上述導電圖案層之上述導電性基板,其中上述基底層係由聚乙炔、聚并苯、聚對苯、聚對苯乙炔、聚吡咯、聚苯胺、聚噻吩、及該等之各種衍生物之樹脂形成,且上述溝槽形成層包含光硬化性或熱硬化性樹脂。
  9. 如請求項7或8之方法,其中將上述電子零件安裝於上述導電性基板之步驟包括:將連接部形成於上述導電圖案層上;及經由上述連接部將上述電子零件與上述導電圖案層連接。
  10. 如請求項7或8之方法,其中將上述電子零件安裝於上述導電性基板之步驟包括:將密接層形成於上述導電圖案層上; 形成覆蓋上述溝槽形成層之與上述基底層為相反側之表面且具有使上述密接層之一部分露出之開口部的絕緣層;將UBM層形成於上述密接層之開口部內露出之上述密接層之面上;將連接部形成於上述UBM層上;及經由上述連接部、上述UBM層及上述密接層將上述電子零件與上述導電圖案層連接。
  11. 一種製造顯示裝置之方法,上述顯示裝置具備:具有基材及設置於上述基材之一個主面側之導電圖案層之導電性基板、以及發光元件,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽,其中上述基底層包含分散於樹脂中之觸媒;使金屬鍍層自露出於上述溝槽之底面之上述基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層;及將上述發光元件安裝於具有上述基材及上述導電圖案層之上述導電性基板。
  12. 一種製造顯示裝置之方法,上述顯示裝置具備:具有基材及設置於上述基材之一個主面側之導電圖案層之導電性基板、以及發光元件,上述方法包括如下步驟:藉由包括將具有凸部之模具壓入至形成於上述基材上之基底層上形 成之溝槽形成層的壓印法,形成具有露出上述基底層之底面與包含上述溝槽形成層之表面之側面的溝槽;使觸媒吸附至露出於上述溝槽之底面之上述基底層;使金屬鍍層自上述觸媒所吸附之基底層生長,藉此形成包含上述金屬鍍層且填充上述溝槽之上述導電圖案層;及將上述發光元件安裝於具有上述基材及上述導電圖案層之上述導電性基板,其中上述基底層係由聚乙炔、聚并苯、聚對苯、聚對苯乙炔、聚吡咯、聚苯胺、聚噻吩、及該等之各種衍生物之樹脂形成,且上述溝槽形成層包含光硬化性或熱硬化性樹脂。
  13. 如請求項11或12之方法,其中將上述發光元件安裝於上述導電性基板之步驟包括:將連接部形成於上述導電圖案層上;及經由上述連接部將上述發光元件與上述導電圖案層連接。
  14. 如請求項11或12之方法,其中將上述發光元件安裝於上述導電性基板之步驟包括:將密接層形成於上述導電圖案層上;形成覆蓋上述溝槽形成層之與上述基底層為相反側之表面且具有使上述密接層之一部分露出之開口部的絕緣層;將UBM層形成於上述密接層之開口部內露出之上述密接層之面上;將連接部形成於上述UBM層上;及 經由上述連接部、上述UBM層及上述密接層將上述發光元件與上述導電圖案層連接。
  15. 如請求項7或8之製造電子裝置之方法,其中以於上述導電圖案層之側面中之至少一部分與上述溝槽之側面之間形成間隙之方式使上述金屬鍍層生長。
  16. 如請求項11或12之製造顯示裝置之方法,其中以於上述導電圖案層之側面中之至少一部分與上述溝槽之側面之間形成間隙之方式使上述金屬鍍層生長。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
WO2020232150A2 (en) * 2019-05-13 2020-11-19 Board Of Regents, The University Of Texas System Roll-to-roll nanoimprint lithography tools processes
CN113391733B (zh) * 2021-07-09 2022-06-17 江苏软讯科技有限公司 一种金属网格柔性导电膜及其制作方法
WO2023090335A1 (ja) * 2021-11-19 2023-05-25 Agc株式会社 透明電子デバイス、合わせガラス、及び透明電子デバイスの製造方法
WO2023189256A1 (ja) * 2022-03-29 2023-10-05 Tdk株式会社 導電性フィルム及び表示装置
WO2023189250A1 (ja) * 2022-03-29 2023-10-05 Tdk株式会社 導電性フィルム及び表示装置
WO2023210488A1 (ja) * 2022-04-28 2023-11-02 富士フイルム株式会社 導電性基板の製造方法
WO2024106228A1 (ja) * 2022-11-18 2024-05-23 Tdk株式会社 導電性フィルム及び表示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201203064A (en) * 2010-03-03 2012-01-16 Miraenanotech Co Ltd A capacitive touch panel and a method for manufacturing the same
KR20140023512A (ko) * 2012-08-16 2014-02-27 엘지이노텍 주식회사 질화물 발광장치
TW201437895A (zh) * 2013-02-27 2014-10-01 Miraenanotech Co Ltd 採用虛擬圖案的靜電電容式觸控螢幕之觸控板結構
TW201505493A (zh) * 2013-07-17 2015-02-01 Ichia Tech Inc 前驅基板、軟性印刷電路板的製造方法及前驅基板

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4417245A1 (de) * 1994-04-23 1995-10-26 Lpkf Cad Cam Systeme Gmbh Verfahren zur strukturierten Metallisierung der Oberfläche von Substraten
KR100280880B1 (ko) 1998-04-10 2001-05-02 구자홍 다이아몬드박막 패턴 제조방법
JP2005008909A (ja) * 2003-06-16 2005-01-13 Canon Inc 構造体の製造方法
JP2006339365A (ja) 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd 配線基板およびその製造方法、多層積層配線基板の製造方法並びにビアホールの形成方法
JPWO2007074567A1 (ja) 2005-12-27 2009-06-04 イビデン株式会社 光・電気複合配線板及びその製造方法
KR100797716B1 (ko) 2006-03-21 2008-01-23 삼성전기주식회사 회로기판이 없는 led-백라이트유닛 및 그 제조방법
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US20080264672A1 (en) * 2007-04-26 2008-10-30 Air Products And Chemicals, Inc. Photoimprintable Low Dielectric Constant Material and Method for Making and Using Same
KR101532716B1 (ko) 2008-12-31 2015-07-02 미래나노텍(주) 광학 필터 및 그 제조 방법
CN103247366B (zh) 2013-03-28 2015-04-08 南昌欧菲光科技有限公司 电容式透明导电膜及其制造方法
KR101553439B1 (ko) 2013-04-30 2015-10-01 주식회사 잉크테크 흑화 전도성 패턴의 형성방법
JP2015164030A (ja) 2014-01-31 2015-09-10 住友金属鉱山株式会社 導電性基板、積層導電性基板、導電性基板の製造方法、及び積層導電性基板の製造方法
JP2016164694A (ja) 2015-03-06 2016-09-08 パナソニックIpマネジメント株式会社 タッチセンサおよびタッチセンサの製造方法
JP2018085358A (ja) * 2016-11-21 2018-05-31 日立化成株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201203064A (en) * 2010-03-03 2012-01-16 Miraenanotech Co Ltd A capacitive touch panel and a method for manufacturing the same
KR20140023512A (ko) * 2012-08-16 2014-02-27 엘지이노텍 주식회사 질화물 발광장치
TW201437895A (zh) * 2013-02-27 2014-10-01 Miraenanotech Co Ltd 採用虛擬圖案的靜電電容式觸控螢幕之觸控板結構
TW201505493A (zh) * 2013-07-17 2015-02-01 Ichia Tech Inc 前驅基板、軟性印刷電路板的製造方法及前驅基板

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