TWI685943B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI685943B TWI685943B TW106146164A TW106146164A TWI685943B TW I685943 B TWI685943 B TW I685943B TW 106146164 A TW106146164 A TW 106146164A TW 106146164 A TW106146164 A TW 106146164A TW I685943 B TWI685943 B TW I685943B
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Abstract
實施形態提供一種可小型化之半導體裝置。 實施形態之半導體裝置具備:基板;金屬板,其具有第1方向之第1寬度及與第1方向正交之第2方向之第2寬度;第1半導體晶片,其設置於金屬板與基板之間,且具有第1方向之第3寬度與第2方向之第4寬度;及第2半導體晶片,其設置於第1半導體晶片與基板之間;且第1寬度小於第3寬度,第2寬度小於第4寬度。
Description
本發明之實施形態係關於一種半導體裝置。
存在將複數個半導體晶片積層並樹脂密封而成之半導體封裝。藉由將複數個半導體晶片積層並收納於一個半導體封裝中而實現半導體裝置之大容量化、高速化、低耗電化。為了使搭載半導體封裝之電子機器小型化,要求使半導體封裝小型化。
本發明提供一種可小型化之半導體裝置。 實施形態之半導體裝置具備:基板;金屬板,其具有第1方向之第1寬度及與上述第1方向正交之第2方向之第2寬度;第1半導體晶片,其設置於上述金屬板與上述基板之間,且具有上述第1方向之第3寬度與上述第2方向之第4寬度;及第2半導體晶片,其設置於上述第1半導體晶片與上述基板之間;且上述第1寬度小於上述第3寬度,上述第2寬度小於上述第4寬度。
[相關申請案] 本申請案享有以日本專利申請案2017-179329號(申請日:2017年9月19日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。 以下,一面參照圖式,一面對本發明之實施形態進行說明。再者,於以下之說明中,對於相同或類似之構件標註相同之符號,針對已經說明過一次之構件等適當省略其說明。 又,於本說明書中,存在為便於說明而使用「上」或「下」之用語之情形。「上」或「下」只不過是表示附圖內之相對位置關係之用語,而並非規定相對於重力之位置關係之用語。 以下,參照附圖對實施形態之半導體裝置進行說明。 (第1實施形態) 第1實施形態之半導體裝置具備:基板;金屬板,其具有第1方向之第1寬度及與第1方向正交之第2方向之第2寬度;第1半導體晶片,其設置於金屬板與基板之間,且具有第1方向之第3寬度與第2方向之第4寬度;及第2半導體晶片,其設置於第1半導體晶片與基板之間;且第1寬度小於第3寬度,第2寬度小於第4寬度。 圖1係第1實施形態之半導體裝置之模式剖視圖。圖2係第1實施形態之半導體裝置之模式俯視圖。圖3係第1實施形態之半導體裝置之模式側視圖。圖1(a)係圖2之A-A'剖視圖。圖1(b)係圖2之B-B'剖視圖。圖2係對模製樹脂進行透視觀察之圖。 第1實施形態之半導體裝置係半導體記憶體100。於半導體記憶體100中,複數個記憶體晶片與邏輯晶片安裝於一個封裝中。 半導體記憶體100具備金屬底座10(金屬板)、樹脂層20、第1記憶體晶片21(第1半導體晶片)、第2記憶體晶片22(第2半導體晶片)、第3記憶體晶片23、邏輯晶片24、連接部26、連接端子28、電路基板30(基板)、模製樹脂32(樹脂材)、外部端子34。 金屬底座10為平板狀。金屬底座10具有第1邊101、第2邊102、第3邊103、第4邊104。第1邊101及第2邊102於第1方向上平行且相互對向。第3邊103及第4邊104於第2方向上平行且相互對向。第1方向與第2方向正交。 金屬底座10之第1方向之寬度為第1寬度(圖2中之W1)。金屬底座10之第2方向之寬度為第2寬度(圖2中之W2)。第1記憶體晶片21之第1方向之寬度為第3寬度(圖2中之W3)。第1記憶體晶片21之第2方向之寬度為第4寬度(圖2中之W4)。第1寬度W1小於第3寬度W3,第2寬度W2小於第4寬度W4。 金屬底座10之尺寸小於第1記憶體晶片21之尺寸。金屬底座10之面積小於第1記憶體晶片21之面積。金屬底座10之端部與第1記憶體晶片21之端部之距離(圖2中之d1)例如為50 μm以上且500 μm以下。 金屬底座10具有第1突出部11、第2突出部12、第3突出部13、及第4突出部14。第1突出部11及第2突出部12設置於金屬底座10之第1邊101。第3突出部13及第4突出部14設置於金屬底座10之第2邊102。第1突出部11、第2突出部12、第3突出部13、及第4突出部14於第2方向上延伸。 第1突出部11、第2突出部12、第3突出部13、及第4突出部14之長度(圖2中之d2)例如為0.5 mm以上且1.5 mm以下。第1突出部11、第2突出部12、第3突出部13、及第4突出部14之前端與第1記憶體晶片21之端部之距離(圖2中之d3)例如為0.4 mm以上且1.0 mm以下。 第1突出部11、第2突出部12、第3突出部13、及第4突出部14之寬度大致固定。第1突出部11、第2突出部12、第3突出部13、及第4突出部14之寬度例如為0.2 mm以上且0.4 mm以下。 如圖3所示,第1突出部11及第2突出部12於模製樹脂32之側面露出。第1突出部11及第2突出部12之前端於模製樹脂32之側面露出。第3突出部13及第4突出部14亦同樣地於模製樹脂32之側面露出。第3突出部13及第4突出部14之前端於模製樹脂32之側面露出。 金屬底座10之膜厚例如為100 μm以上且200以下。金屬底座10例如為鐵與鎳之合金。金屬底座例如為42合金。 金屬底座10係進行半導體記憶體100之封裝時所使用之引線框架之一部分。金屬底座10具有於進行半導體記憶體100之封裝時,支持所積層之第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24之功能。 第1突出部11、第2突出部12、第3突出部13、及第4突出部14係設置於進行半導體記憶體100之封裝時所使用之引線框架之懸吊銷之一部分。第1突出部11、第2突出部12、第3突出部13、及第4突出部14係切割時被切斷之懸吊銷。 再者,亦可於金屬底座10之一面或兩面設置用以提高金屬底座10與樹脂層20之密接性或金屬底座10與模製樹脂32之密接性之凹凸。凹凸例如為複數個袋狀孔。又,凹凸例如為複數個貫通孔。 樹脂層20設置於金屬底座10與第1記憶體晶片21之間。樹脂層20例如為熱硬化性樹脂。樹脂層20例如為晶片接合膜(DAF,die attach film)。樹脂層20具有將金屬底座10與第1記憶體晶片21接著之功能。 第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24設置於金屬底座10與電路基板30之間。於邏輯晶片24之上積層有第3記憶體晶片23、第2記憶體晶片22、第1記憶體晶片21。 於邏輯晶片24、第3記憶體晶片23、第2記憶體晶片22、第1記憶體晶片21之各者之間設置有連接部26。邏輯晶片24、第3記憶體晶片23、第2記憶體晶片22、第1記憶體晶片21使用連接部26電性連接。連接部26例如為微凸塊。 第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23之厚度例如為30 μm以上且50 μm以下。第1記憶體晶片21與第2記憶體晶片22之間隔、第2記憶體晶片22與第3記憶體晶片23之間隔例如為10 μm以上且30 μm以下。 第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23具有記憶資料之功能。第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23例如為NAND(Not AND,反及)型快閃記憶體。第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23例如係使用單晶矽而製造。 邏輯晶片24具備運算功能。邏輯晶片24例如係第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23之控制器晶片。 電路基板30設置於第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24之下。電路基板30係玻璃環氧化物基板。電路基板30具有連接第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24與外部之電路之功能。 連接端子28設置於第3記憶體晶片23與電路基板30之間。藉由連接端子28而將第3記憶體晶片23與電路基板30電性連接。連接端子28例如為微凸塊。 外部端子34設置於電路基板30之下。外部端子34例如為焊料球。 模製樹脂32覆蓋金屬底座10、第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24。模製樹脂32亦設置於第1記憶體晶片21與第2記憶體晶片22之間、第2記憶體晶片22與第3記憶體晶片23之間、第3記憶體晶片23與邏輯晶片24之間。 模製樹脂32具有保護第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24之功能。模製樹脂32例如將環氧樹脂作為主成分。 繼而,對第1實施形態之半導體裝置之製造方法進行說明。對半導體記憶體100之封裝方法進行說明。 圖4、圖5係表示第1實施形態之半導體裝置之製造方法之模式圖。圖4(a)、圖5(a)係俯視圖。圖4(b)係圖4(a)之C-C'剖視圖。圖5(b)係圖5(a)之C-C'剖視圖。 首先,準備引線框架40(圖4)。於引線框架40設置複數個金屬底座10。金屬底座10係由懸吊銷42支持。 繼而,於金屬底座10之上積層複數個半導體晶片而形成積層體44(圖5)。積層體44具備金屬底座10、樹脂層20、第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24、連接部26。 積層體44之複數個半導體晶片藉由樹脂層20接著於金屬底座10。又,積層體44之複數個半導體晶片彼此例如使用微凸塊連接。 圖6係第1實施形態之半導體裝置之製造方法之說明圖。圖6係懸吊銷42之切斷步驟之說明圖。圖6表示使用切斷模具50將懸吊銷42切斷之方法。圖6(a)係表示切斷前之圖,圖6(b)係表示切斷後之圖。圖6係包含懸吊銷42部分之剖視圖。 切斷模具50具有支持台51、導引體52、衝頭53。如圖6(a)所示,形成於引線框架之積層體44被載置於切斷模具50之支持台51之上。懸吊銷42之上表面被導引體52壓住。於導引體52之間設置有用以將懸吊銷42切斷之衝頭53。 如圖6(b)所示,衝頭53進行加工而將懸吊銷42切斷。藉由將懸吊銷42切斷而使積層體44單片化。 作為第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23與導引體52之間之對準餘裕,需要固定距離。又,為了防止懸吊銷42之破損,導引體52之前端需要特定之寬度。因此,作為第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23與懸吊銷42之切斷位置之間之距離(圖6(a)、圖6(b)中之dx),需要特定之距離。距離dx例如為0.4 mm以上且1.0 mm以下。 於將懸吊銷42切斷後,自第1記憶體晶片21之端部突出之第1突出部11與第3突出部13作為懸吊銷42之一部分殘留於金屬底座10。第1突出部11及第3突出部13之前端與第1記憶體晶片21之端部之距離相當於距離dx,例如為0.4 mm以上且1.0 mm以下。 圖7、圖8、圖9係表示第1實施形態之半導體裝置之製造方法之模式圖。圖7(a)、圖8(a)、圖9(a)係俯視圖。圖7(b)係圖7(a)之D-D'剖視圖。圖8(b)係圖8(a)之D-D'剖視圖。圖9(b)係圖9(a)之D-D'剖視圖。 將單片化之複數個積層體44固定於電路基板30上(圖7)。電路基板30與積層體44例如使用連接端子28連接。連接端子28例如為微凸塊。積層體44例如固定有9個。固定於電路基板30之積層體44之數量並不限定於9個。 相鄰之積層體44之與金屬底座10之突出部對應之懸吊銷42係對向。例如,如圖7所示,與第1突出部11和第3突出部13對應之懸吊銷42係對向。又,與第2突出部12和第4突出部14對應之懸吊銷42係對向。 圖7中之虛線表示將電路基板30切斷時之切斷預定線。於相鄰之2個積層體44之間之電路基板30存在特定寬度(圖7中之d4)之無效區域。 繼而,利用模製樹脂32將積層體44密封(圖8)。模製樹脂32覆蓋金屬底座10、第1記憶體晶片21、第2記憶體晶片22、第3記憶體晶片23、邏輯晶片24。模製樹脂32亦將半導體晶片之間、即第1記憶體晶片21與第2記憶體晶片22之間、第2記憶體晶片22與第3記憶體晶片23之間、第3記憶體晶片23與邏輯晶片24之間掩埋。 模製樹脂32例如係於圖8所示之空心箭頭之方向對積層體44進行填充。即自金屬底座10之不存在突出部之邊之側流入模製樹脂32。藉由自不存在突出部之邊之側流入模製樹脂32,半導體晶片之間之模製樹脂32之填充性提高。即,不易於半導體晶片之間產生模製樹脂32之空腔(孔隙)。 繼而,於電路基板30之與積層體44相反側之面形成外部端子34。外部端子34例如為焊料球。 繼而,例如使用接著層72將模製樹脂32側接著於切割裝置之載置台70(圖9)。繼而,沿著圖9中之虛線所示之切斷預定線,將電路基板30、模製樹脂32切斷而使積層體44單片化。此時,金屬底座10之突出部之一部分亦被切斷。電路基板30、模製樹脂32、及金屬底座10之突出部例如係使用刀片切割裝置切斷。 藉由以上之製造方法製造經封裝之半導體記憶體100。 繼而,對第1實施形態之半導體裝置之作用及效果進行說明。 圖10係比較例之半導體裝置之模式剖視圖。圖11係比較例之半導體裝置之模式俯視圖。圖12係比較例之半導體裝置之模式側視圖。圖10係圖11之E-E'剖視圖。圖11係對模製樹脂進行透視觀察之圖。 比較例之半導體裝置係半導體記憶體900。於半導體記憶體900,複數個記憶體晶片與邏輯晶片安裝於一個封裝中。 比較例之半導體記憶體900與第1實施形態之半導體記憶體100不同之處在於,金屬底座10之尺寸大於第1記憶體晶片21之尺寸。 於半導體記憶體900之金屬底座10並未設置突出部。原因在於在懸吊銷42之切斷步驟中,由於金屬底座10充分大於第1記憶體晶片21,故而可將引線框架之切斷位置設置於懸吊銷42與金屬底座10之連接部或者較連接部更靠內側。因此,亦不存在如半導體記憶體100般金屬底座10之突出部於模製樹脂32之側面露出之情形。 圖13係表示第1實施形態之半導體裝置之作用及效果之圖。圖13(a)係比較例之半導體裝置之模式剖視圖。圖13(a)表示與圖10相同之剖面。圖13(b)係第1實施形態之半導體裝置之模式剖視圖。圖13(b)表示與圖1(a)相同之剖面。 於第1實施形態之半導體記憶體100中,金屬底座10之尺寸小於第1記憶體晶片21之尺寸。例如,半導體記憶體100之寬度(圖13(b)中之Wq)小於半導體記憶體900之寬度(圖13(a)中之Wp)。因此,與比較例之半導體記憶體900相比,可實現半導體記憶體100之小型化。 又,於比較例之半導體記憶體900之情形時,於利用模製樹脂32進行密封時,有半導體晶片之間之模製樹脂32之填充性變差之虞。尤其有第1記憶體晶片21與第2記憶體晶片22之間之模製樹脂32之填充性變差之虞。因此,有如圖13(a)所示般於半導體晶片之間產生空腔58(孔隙)之虞。 於半導體記憶體900之情形時,金屬底座10之尺寸大於第1記憶體晶片21之尺寸。因此,於流入模製樹脂32進行樹脂密封時,金屬底座10會成為障礙而阻礙模製樹脂32流入至半導體晶片之間。因此,於半導體晶片之間產生空腔58。若於模製樹脂32產生空腔58,則會產生例如半導體記憶體900之可靠性不良而成為問題。 於第1實施形態之半導體記憶體100中,金屬底座10之尺寸小於第1記憶體晶片21之尺寸。因此,於流入模製樹脂32進行樹脂密封時,金屬底座10不會成為障礙,從而不會阻礙模製樹脂32流入至半導體晶片之間。 因此,於第1實施形態之半導體記憶體100中,半導體晶片之間之模製樹脂32之填充性提高。因此,半導體記憶體100之可靠性提高。 於第1實施形態之半導體記憶體100中,金屬底座10之端部與第1記憶體晶片21之端部之距離(圖2中之d1)較佳為50 μm以上且500 μm以下,更佳為100 μm以上且300 μm以下。若低於上述範圍,則會有因對準偏移而導致金屬底座10自第1記憶體晶片21之端部露出之虞。又,若高於上述範圍,則會有未支持於金屬底座10之第1記憶體晶片21之面積增大,而第1記憶體晶片21產生缺陷等之虞。 例如,亦可設為將第1突出部11及第2突出部12設置於金屬底座10之第3邊103且將第3突出部13及第4突出部14設置於金屬底座10之第4邊104之構成。又,例如,亦可設為第1突出部11、第2突出部12、第3突出部13、及第4突出部14於金屬底座10之四個角各設置1個且分別相對於第1方向及第2方向斜交延伸之構成。 以上,根據第1實施形態之半導體記憶體100,可實現半導體記憶體100之小型化。又,可提高半導體記憶體100之可靠性。 (第2實施形態) 第2實施形態之半導體裝置與第1實施形態不同之處在於,將第1突出部與第3突出部假想性地連結之線段、將第1突出部與第4突出部假想性地連結之線段、將第2突出部與第3突出部假想性地連結之線段、及將第2突出部與第4突出部假想性地連結之線段與第2方向斜交。以下,針對與第1實施形態重複之內容,省略一部分記述。 圖14係第2實施形態之半導體裝置之模式俯視圖。圖14係對模製樹脂進行透視觀察之圖。 第2實施形態之半導體裝置係半導體記憶體200。於半導體記憶體200,複數個記憶體晶片與邏輯晶片安裝於一個封裝中。 金屬底座10具有第1突出部11、第2突出部12、第3突出部13、及第4突出部14。第1突出部11及第2突出部12設置於金屬底座10之第1邊101。第3突出部13及第4突出部14設置於金屬底座10之第2邊102。 將第1突出部11與第3突出部13假想性地連結之線段A、將第1突出部11與第4突出部14假想性地連結之線段B、將第2突出部12與第3突出部13假想性地連結之線段C、及將第2突出部12與第4突出部14假想性地連結之線段D與第2方向斜交。線段A、線段B、線段C、及線段D例如係將突出部之前端彼此假想性地連結而成之線段。 設置於金屬底座10之右側之第1突出部11及第2突出部12與設置於金屬底座10之左側之第3突出部13及第4突出部14使第1方向之位置(圖14中之上下方向之位置)錯開而配置。換言之,設置於金屬底座10之右側之第1突出部11及第2突出部12與設置於金屬底座10之左側之第3突出部13及第4突出部14係以成為互不相同之關係之方式配置。 於第1實施形態之半導體記憶體100中,如圖7所示,於將積層體44配置於電路基板30上時,相鄰之積層體44之金屬底座10之突出部對向而發生干涉。例如,如圖7所示,第1突出部11與第3突出部13對向。又,第2突出部12與第4突出部14對向。 圖7中之虛線表示將電路基板30切斷時之切斷預定線。於相鄰之2個積層體44之間之電路基板30存在特定寬度(圖7中之d4)之無效區域。於第1實施形態之半導體記憶體100中,因金屬底座10之突出部對應而發生干涉導致無效區域之寬度d4變寬。 圖15係表示第2實施形態之半導體裝置之製造方法之模式圖。圖15(a)係俯視圖。圖15(b)係圖15(a)之F-F'剖視圖。圖15係與第1實施形態之圖7對應之圖。 於第2實施形態之半導體記憶體200中,如圖15所示,由於金屬底座10之突出部成為互不相同之關係,故而與相鄰之積層體44之金屬底座10之突出部對應之懸吊銷42並不對向而不會發生干涉。因此,可使相鄰之積層體44之金屬底座10之距離比半導體記憶體100之情形更靠近。因此,與半導體記憶體100相比,電路基板30之無效區域之寬度(圖15中之d5)變窄。 電路基板30之無效區域之寬度d5變窄,藉此,例如可縮小電路基板30之尺寸。又,例如可於相同尺寸之電路基板30載置多於第1實施形態之積層體44。因此,可降低半導體記憶體200之製造成本。 金屬底座10之突出部之配置並不限定於圖14所示之配置。只要金屬底座10之突出部成為互不相同之關係,則亦可設為圖14以外之配置。 於第1實施形態之半導體記憶體100中,藉由使金屬底座10之尺寸小於第1記憶體晶片21之尺寸而於金屬底座10設置突出部。於第2實施形態之半導體記憶體200中,解決了起因於金屬底座10之突出部之問題之一。 以上,根據第2實施形態之半導體記憶體200,與第1實施形態相同地可實現半導體記憶體200之小型化及可靠性之提高。進而,可降低半導體記憶體200之製造成本。 (第3實施形態) 第3實施形態之半導體裝置與第1實施形態不同之處在於,第1突出部具有第1部分及位於較第1部分更靠前端側且厚度薄於第1部分之第2部分。以下,針對與第1實施形態重複之內容,省略一部分記述。 圖16係第3實施形態之半導體裝置之模式俯視圖。圖17係第3實施形態之半導體裝置之模式剖視圖。圖17係圖16之G-G'剖視圖。圖16係對模製樹脂進行透視觀察之圖。 第3實施形態之半導體裝置係半導體記憶體300。於半導體記憶體300中,複數個記憶體晶片與邏輯晶片安裝於一個封裝中。 金屬底座10具有第1突出部11、第2突出部12、第3突出部13、及第4突出部14。第1突出部11及第2突出部12設置於金屬底座10之第1邊101。第3突出部13及第4突出部14設置於金屬底座10之第2邊102。 第1突出部11具有第1部分11a與第2部分11b。第2部分11b位於較第1部分11a更靠第1突出部11之前端側。第2部分11b之厚度(圖17中之t2)薄於第1部分11a之厚度(圖17中之t1)。 第1部分11a與第2部分11b之交界11c位於第1記憶體晶片21之端部與模製樹脂32之端部之間。第1部分11a與第2部分11b之交界11c之階差設置於金屬底座10之與第1記憶體晶片21為相反側之面。 第2部分11b之厚度t2例如為第1部分11a之厚度t1之三分之一以上且三分之二以下。 第2部分11b係設置於引線框架之懸吊銷之凹部之一部分。第2部分11b係將電路基板30與模製樹脂32切斷時被切斷之懸吊銷之凹部。 第2突出部12、第3突出部13、及第4突出部14亦分別具備與第1部分11a及第2部分11b相同構成之第1部分12a及第2部分12b、第1部分13a及第2部分13b、第1部分14a及第2部分14b。 圖18係第3實施形態之半導體裝置之作用及效果之說明圖。圖18(a)係第1實施形態之情形時之剖視圖,圖18(b)係第3實施形態之情形時之剖視圖。 圖18表示使用刀片切割裝置將電路基板30與模製樹脂32切斷時之剖面。表示將引線框架之懸吊銷42切斷之過程中之剖面。 使用接著層72將積層體44之模製樹脂32側接著於切割裝置之載置台70。電路基板30與模製樹脂32、及懸吊銷42係利用旋轉切割刀片60切斷。積層體44之左側係切斷已經結束之狀態。積層體44之右側係切斷中之狀態。 例如,於圖18(a)之第1實施形態之情形時,於利用切割刀片60將懸吊銷42切斷時,將懸吊銷42向空心箭頭之方向拉伸。藉由拉伸懸吊銷42,而使懸吊銷42相對於模製樹脂32向空心箭頭之方向相對地移動。因此,有懸吊銷42與模製樹脂32之間剝離之虞。 當於懸吊銷42與模製樹脂32之間產生剝離時,剝離部位成為來自外部之水分之滲入路徑。當滲入水分時,有產生半導體記憶體100之電路短路之虞。因此,有半導體記憶體100之可靠性降低之虞。 利用切割刀片60切斷之懸吊銷42之厚度越厚,切斷時間越長。因此,拉伸懸吊銷42之時間變長,而容易產生懸吊銷42與模製樹脂32之間之剝離。 又,若懸吊銷42之切斷部分與接著層72之間之部分模製樹脂32之厚度變薄,則模製樹脂32容易缺損。若模製樹脂32缺損,則半導體記憶體100變得外觀不良。 於圖18(b)之第3實施形態之情形時,於懸吊銷42設置有切斷後成為第1突出部11之第2部分11b之凹部42a。於利用切割刀片60將懸吊銷42切斷時,即便將懸吊銷42向空心箭頭之方向拉伸,第1部分11a與第2部分11b之交界11c之階差亦會被模製樹脂32卡住。因此,抑制懸吊銷42相對於模製樹脂32之相對移動。 因此,抑制懸吊銷42與模製樹脂32之間之剝離。因此,與第1實施形態之情況相比,半導體記憶體300之可靠性提高。 又,於懸吊銷42之凹部42a,懸吊銷42之厚度變薄。因此,懸吊銷42之切斷時間變短。因此,進而抑制懸吊銷42與模製樹脂32之間之剝離。 又,懸吊銷42之切斷部分與接著層72之間之部分之模製樹脂32之厚度因設置有懸吊銷42之凹部44a而變厚。因此,抑制模製樹脂32之缺損。因此,抑制半導體記憶體300產生外觀不良。 第2部分11b之厚度t2較佳為第1部分11a之厚度t1之三分之一以上且三分之二以下。若低於上述範圍,則有作為懸吊銷42之強度變得不充分之虞。若高於上述範圍,則有懸吊銷42與模製樹脂32之間之剝離之抑制變得不充分之虞。又,若高於上述範圍,則有模製樹脂32之缺損之抑制效果變得不充分之虞。 於第1實施形態之半導體記憶體100中,藉由使金屬底座10之尺寸小於第1記憶體晶片21之尺寸而將突出部設置於金屬底座10。並且,該突出部自模製樹脂32露出。於第3實施形態之半導體記憶體300中,解決了起因於金屬底座10之突出部之問題之一。 再者,亦可設為將第2實施形態之構成與第3實施形態之構成組合而成之半導體記憶體。 以上,根據第3實施形態之半導體記憶體300,與第1實施形態同樣地可實現半導體記憶體300之小型化及可靠性之提高。進而,可提高半導體記憶體300之可靠性及抑制外觀不良之產生。 (第4實施形態) 第4實施形態之半導體裝置與第1實施形態不同之處在於,第1突出部具有:第1區域,其具有朝向前端而寬度變細之圓錐形狀;及第2區域,其位於較第1區域更靠前端側,且具有大致固定之寬度。以下,針對與第1實施形態重複之內容,省略一部分記述。 圖19係第4實施形態之半導體裝置之模式俯視圖。圖19係對模製樹脂進行透視觀察之圖。 第4實施形態之半導體裝置係半導體記憶體400。於半導體記憶體400中,複數個記憶體晶片與邏輯晶片安裝於一個封裝中。 金屬底座10具有第1突出部11、第2突出部12、第3突出部13、及第4突出部14。第1突出部11及第2突出部12設置於金屬底座10之第1邊101。第3突出部13及第4突出部14設置於金屬底座10之第2邊102。 第1突出部11具有第1區域11x與第2區域11y。第2區域11y位於較第1區域11x更靠第1突出部11之前端側。第1區域11x具有朝向第1突出部11之前端而寬度變細之圓錐形狀。第2區域11y具有大致固定之寬度。 第1區域11x與第2區域11y之交界11z例如位於第1記憶體晶片21之端部與模製樹脂32之端部之間。 第2突出部12、第3突出部13、及第4突出部14亦分別具備與第1區域11x和第2區域11y相同構成之第1區域12x與第2區域12y、第1區域13x與第2區域13y、第1區域14x與第2區域14y。 於利用切割刀片60將懸吊銷42切斷時,即便將懸吊銷42向空心箭頭之方向拉伸,圓錐形狀之第1區域11x亦會被模製樹脂32卡住。因此,抑制懸吊銷42相對於模製樹脂32之相對移動。 因此,抑制懸吊銷42與模製樹脂32之間之剝離。因此,與第1實施形態之情況相比,半導體記憶體400之可靠性提高。 再者,亦可設為第1突出部11不具備第2區域11y而整體具有圓錐形狀之構成。 於第1實施形態之半導體記憶體100中,藉由使金屬底座10之尺寸小於第1記憶體晶片21之尺寸而將突出部設置於金屬底座10。並且,該突出部自模製樹脂32露出。於第4實施形態之半導體記憶體400中,解決了起因於金屬底座10之突出部之問題之一。 再者,亦可設為將第2實施形態之構成與第4實施形態之構成組合而成之半導體記憶體。又,亦可設為將第2實施形態之構成、第3實施形態之構成、及第4實施形態之構成組合而成之半導體記憶體。 以上,根據第4實施形態之半導體記憶體400,與第1實施形態同樣地可實現半導體記憶體400之小型化及可靠性之提高。進而,可實現半導體記憶體400之可靠性之提高。 於第1至第4實施形態中,作為半導體裝置,以將記憶體晶片與邏輯晶片積層而成之半導體記憶體為例進行了說明。然而,半導體裝置並不限定於上述構成。例如,亦可為僅將記憶體晶片積層而成之半導體記憶體。又,例如亦可為僅將邏輯晶片積層而成之邏輯裝置。 於第1至第4實施形態中,以積層有3個記憶體晶片之情形為例進行了說明,但經積層之記憶體晶片之數量亦可為2個或4個以上。 以上,已對本發明之若干實施形態進行了說明,但該等實施形態係作為例子而提出,並無意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態加以實施,且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。例如,亦可將一實施形態之構成要素替換或變更為其他實施形態之構成要素。該等實施形態或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明與其均等之範圍內。
10‧‧‧金屬底座(金屬板)11‧‧‧第1突出部11a‧‧‧第1部分11b‧‧‧第2部分11c‧‧‧交界11x‧‧‧第1區域11y‧‧‧第2區域11z‧‧‧交界12‧‧‧第2突出部12a‧‧‧第1部分12b‧‧‧第2部分12x‧‧‧第1區域12y‧‧‧第2區域13‧‧‧第3突出部13a‧‧‧第1部分13b‧‧‧第2部分13x‧‧‧第1區域13y‧‧‧第2區域14‧‧‧第4突出部14a‧‧‧第1部分14b‧‧‧第2部分14x‧‧‧第1區域14y‧‧‧第2區域20‧‧‧樹脂層21‧‧‧第1記憶體晶片(第1半導體晶片)22‧‧‧第2記憶體晶片(第2半導體晶片)23‧‧‧第3記憶體晶片24‧‧‧邏輯晶片26‧‧‧連接部28‧‧‧連接端子30‧‧‧電路基板(基板)32‧‧‧模製樹脂(樹脂材)34‧‧‧外部端子40‧‧‧引線框架42‧‧‧懸吊銷42a‧‧‧凹部44‧‧‧積層體50‧‧‧切斷模具51‧‧‧支持台52‧‧‧導引體53‧‧‧衝頭58‧‧‧空腔60‧‧‧切割刀片70‧‧‧載置台72‧‧‧接著層100‧‧‧半導體記憶體(半導體裝置)101‧‧‧第1邊102‧‧‧第2邊103‧‧‧第3邊104‧‧‧第4邊200‧‧‧半導體記憶體(半導體裝置)300‧‧‧半導體記憶體(半導體裝置)400‧‧‧半導體記憶體(半導體裝置)900‧‧‧半導體記憶體d1‧‧‧距離d2‧‧‧距離d3‧‧‧距離d4‧‧‧寬度d4‧‧‧寬度dx‧‧‧距離t1‧‧‧厚度t2‧‧‧厚度W1‧‧‧第1寬度W2‧‧‧第2寬度W3‧‧‧第3寬度W4‧‧‧第4寬度Wp‧‧‧寬度Wq‧‧‧寬度
圖1(a)及(b)係第1實施形態之半導體裝置之模式剖視圖。 圖2係第1實施形態之半導體裝置之模式俯視圖。 圖3係第1實施形態之半導體裝置之模式側視圖。 圖4(a)及(b)係表示第1實施形態之半導體裝置之製造方法之模式圖。 圖5(a)及(b)係表示第1實施形態之半導體裝置之製造方法之模式圖。 圖6(a)及(b)係第1實施形態之半導體裝置之製造方法之說明圖。 圖7(a)及(b)係表示第1實施形態之半導體裝置之製造方法之模式圖。 圖8(a)及(b)係表示第1實施形態之半導體裝置之製造方法之模式圖。 圖9(a)及(b)係表示第1實施形態之半導體裝置之製造方法之模式圖。 圖10係比較例之半導體裝置之模式剖視圖。 圖11係比較例之半導體裝置之模式俯視圖。 圖12係比較例之半導體裝置之模式側視圖。 圖13(a)及(b)係表示第1實施形態之半導體裝置之作用及效果之圖。 圖14係第2實施形態之半導體裝置之模式俯視圖。 圖15(a)及(b)係表示第2實施形態之半導體裝置之製造方法之模式圖。 圖16係第3實施形態之半導體裝置之模式俯視圖。 圖17係第3實施形態之半導體裝置之模式剖視圖。 圖18(a)及(b)係第3實施形態之半導體裝置之作用及效果之說明圖。 圖19係第4實施形態之半導體裝置之模式俯視圖。
10‧‧‧金屬底座(金屬板)
11‧‧‧第1突出部
13‧‧‧第3突出部
20‧‧‧樹脂層
21‧‧‧第1記憶體晶片(第1半導體晶片)
22‧‧‧第2記憶體晶片(第2半導體晶片)
23‧‧‧第3記憶體晶片
24‧‧‧邏輯晶片
26‧‧‧連接部
28‧‧‧連接端子
30‧‧‧電路基板(基板)
32‧‧‧模製樹脂(樹脂材)
34‧‧‧外部端子
100‧‧‧半導體記憶體(半導體裝置)
Claims (10)
- 一種半導體裝置,其具備:基板;金屬板,其具有第1方向之第1寬度及與上述第1方向正交之第2方向之第2寬度、於上述第1方向上平行且相互對向之第1邊及第2邊、於上述第2方向上平行且相互對向之第3邊及第4邊、設置於上述第1邊之第1突出部及第2突出部、設置於上述第2邊之第3突出部及第4突出部;第1半導體晶片,其設置於上述金屬板與上述基板之間,且具有上述第1方向之第3寬度與上述第2方向之第4寬度;第2半導體晶片,其設置於上述第1半導體晶片與上述基板之間;及樹脂材,其覆蓋上述金屬板、上述第1半導體晶片、及上述第2半導體晶片;且上述第1寬度小於上述第3寬度,上述第2寬度小於上述第4寬度;上述第1突出部、上述第2突出部、上述第3突出部、及上述第4突出部於上述樹脂材之側面露出。
- 如請求項1之半導體裝置,其中將上述第1突出部與上述第3突出部假想性地連結之線段、將上述第1突出部與上述第4突出部假想性地連結之線段、將上述第2突出部與上述第3突出部假想性地連結之線段、及將上述第2突出部與上述第4突出部假想性地連結之線段與上述第2方向斜交。
- 如請求項1之半導體裝置,其中上述第1突出部具有第1部分、及位於 較上述第1部分更靠前端側且厚度薄於上述第1部分之第2部分。
- 如請求項1之半導體裝置,其中上述第1突出部具有第1區域,上述第1區域具有朝向前端而寬度變細之圓錐形狀。
- 如請求項4之半導體裝置,其中上述第1突出部具有第2區域,上述第2區域位於較上述第1區域更靠前端側且具有大致固定之寬度。
- 如請求項1至5中任一項之半導體裝置,其進而具備樹脂層,上述樹脂層設置於上述金屬板與上述第1半導體晶片之間。
- 如請求項1至5中任一項之半導體裝置,其中上述基板為電路基板。
- 一種半導體裝置,其具備:基板;金屬板,其具有第1方向之第1寬度及與上述第1方向正交之第2方向之第2寬度;第1半導體晶片,其設置於上述金屬板與上述基板之間,且具有上述第1方向之第3寬度與上述第2方向之第4寬度;第2半導體晶片,其設置於上述第1半導體晶片與上述基板之間;及樹脂材,其覆蓋上述金屬板、上述第1半導體晶片、及上述第2半導體晶片;且上述第1寬度小於上述第3寬度,上述第2寬度小於上述第4寬度; 上述樹脂材覆蓋整個上述金屬板。
- 如請求項8之半導體裝置,其中上述金屬板具有第1突出部、第2突出部、第3突出部、及第4突出部,上述第1突出部、上述第2突出部、上述第3突出部、及上述第4突出部於上述樹脂材之側面露出。
- 如請求項9之半導體裝置,其中上述金屬板具有於上述第1方向上平行且相互對向之第1邊及第2邊、及於上述第2方向上平行且相互對向之第3邊及第4邊,上述第1突出部及上述第2突出部設置於上述第1邊,上述第3突出部及上述第4突出部設置於上述第2邊。
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