TWI663664B - Method for forming metal wiring - Google Patents
Method for forming metal wiring Download PDFInfo
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- TWI663664B TWI663664B TW107103572A TW107103572A TWI663664B TW I663664 B TWI663664 B TW I663664B TW 107103572 A TW107103572 A TW 107103572A TW 107103572 A TW107103572 A TW 107103572A TW I663664 B TWI663664 B TW I663664B
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- insulating layer
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1605—Process or apparatus coating on selected surface areas by masking
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
- C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
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- C23C18/161—Process or apparatus coating on selected surface areas by direct patterning from plating step, e.g. inkjet
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- C23C18/30—Activating or accelerating or sensitising with palladium or other noble metal
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- C23C18/31—Coating with metals
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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Abstract
實施形態係提供一種可以低成本形成金屬配線之金屬配線之形成方法。 實施形態之金屬配線之形成方法,係:在基板上形成第1絕緣層;使第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸後形成觸媒吸附層;在觸媒吸附層上形成與第1絕緣層不同之第2絕緣層;將第2絕緣層圖案化後形成遮罩圖案;將遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻第1絕緣層;在已蝕刻第1絕緣層之領域選擇性地形成觸媒層;在觸媒層上利用無電解電鍍法形成金屬層。
Description
本發明之實施形態係有關金屬配線之形成方法。
在半導體裝置,例如,為了得到電晶體、二極體等元件之間的電性接續而使用金屬配線。此外,為了半導體裝置之多功能化或高積體化,有使用基板貼合之場合。基板貼合,係藉由將形成在不同基板之半導體裝置、層積並貼合而一體化。例如,藉由貼合具有不同功能之半導體裝置,可以實現半導體裝置之多功能化。此外,例如,藉由貼合具有同種功能之半導體裝置,可以實現半導體裝置之高積體化。於基板貼合,例如,藉由直接接合被形成在各基板表面之金屬配線彼此,而層積之半導體裝置間得以電性接續。 為了半導體裝置之低成本化,期待以低成本形成金屬配線。此外,期待能以低成本實現基板貼合之金屬配線之形成方法。
本發明之實施形態,係提供一種可以低成本形成金屬配線之金屬配線之形成方法。 實施形態之金屬配線之形成方法,其特徵係:在基板上形成第1絕緣層;使前述第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸後形成觸媒吸附層;在前述觸媒吸附層上形成與前述第1絕緣層不同之第2絕緣層;將前述第2絕緣層圖案化後形成遮罩圖案;將前述遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻前述第1絕緣層;在已蝕刻前述第1絕緣層之領域選擇性地形成觸媒層;在前述觸媒層上利用無電解電鍍法形成金屬層。
以下,參照圖式詳細說明本發明之實施形態。又,於以下之說明,在相同或類似的構件等附上相同的符號,針對說明一遍過的構件等酌情省略其說明。 (第1實施形態) 第1實施形態之金屬配線之形成方法,係:在基板上形成第1絕緣層;使第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸後形成觸媒吸附層;在觸媒吸附層上形成與第1絕緣層不同之第2絕緣層;將第2絕緣層圖案化後形成遮罩圖案;將遮罩圖案作為遮罩,並利用濕式蝕刻法去除第1絕緣層;在已去除第1絕緣層之領域選擇性地形成觸媒層;在觸媒層上利用無電解電鍍法形成金屬層。 圖1係第1實施形態之金屬配線之形成方法之說明圖。圖1係形成金屬配線之製程之剖面圖。 最初,準備基板10。基板10,例如,為單晶矽基板。 其次,在基板10上形成第1絕緣層11。第1絕緣層11,例如,係氧化物、氮化物、或氧氮化物。氧化物,例如,係氧化矽、氧化鋁。氮化物,例如,係氮化矽、氮化鋁。氧氮化物,例如,係氧氮化矽、氧氮化鋁。第1絕緣層11,例如,係氧化矽。 其次,在第1絕緣層11上形成觸媒吸附層20。觸媒吸附層20之膜厚,例如,為2nm以下。 觸媒吸附層20,係藉由使第1絕緣層11之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之三氮雜苯化合物之溶液接觸而形成。三氮雜苯化合物,係具有三氮雜苯骨格、第1官能基、及第2官能基。 第1實施形態之三氮雜苯化合物,係以下述化學式(1)表示。
化學式(1)中,A、B、C內,至少一個為矽烷醇基及烷氧矽基之任一方,至少一個是由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一個,R
1、R
2、R
3為任意存在之連結基。 烷氧矽基,例如,三甲基矽基、二甲氧基甲基矽基、單甲氧基二甲基矽基、三乙氧基矽基、二乙氧基甲基矽基、單乙氧基二甲基矽基。例如,R
1、R
2、R
3係包含第二級胺或烷基鏈。例如,R
1、R
2、R
3不存在,而胺基、氫硫基、羧基或疊氮基直接在三氮雜苯環結合也無妨。 例如,A、B、C內,一個為矽烷醇基及烷氧矽基之任一方,其餘2個是由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一個也無妨。 包含三氮雜苯化合物之溶液之溶媒,例如,為水。包含三氮雜苯化合物之溶液之溶媒,例如,為甲醇、乙醇、丙醇、乙二醇、甘油、丙二醇單乙基醚等之醇系溶媒。 第1絕緣層11至表面、與包含三氮雜苯化合物的溶液之接觸,例如,係藉由將基板10浸漬在包含三氮雜苯化合物之溶液中來進行。或者,藉由在第1絕緣層11上塗布包含三氮雜苯化合物之溶液來進行。 第1絕緣層11之表面、與包含三氮雜苯化合物的溶液之接觸時間,例如,為1分鐘以下。 其次,在觸媒吸附層20上形成與第1絕緣層11不同之第2絕緣層12(圖1(a))。第2絕緣層12,例如,係樹脂層。第2絕緣層12,例如,係光阻劑。 其次,將第2絕緣層12圖案化後形成遮罩圖案32(圖1(b))。例如,第2絕緣層12為光阻劑之場合,利用公知的微影法形成遮罩圖案32。 遮罩圖案32,例如,為線條&空間圖案。在無第2絕緣層12的領域之第1絕緣層11上,殘存觸媒吸附層20。 其次,將遮罩圖案32作為遮罩,蝕刻第1絕緣層11(圖1(c))。藉由蝕刻第1絕緣層11,在第1絕緣層11形成溝。第1絕緣層11之蝕刻,係利用濕式蝕刻法進行。 在濕式蝕刻法使用之藥液,係包含氟化氫、氟化銨、或者磷酸。在濕式蝕刻法使用之藥液,例如,係氫氟酸、氟化銨溶液、或者磷酸溶液。 第1絕緣層11為氧化矽之場合,在藥液使用氫氟酸、或者氟化銨溶液。 如圖1(c)所示,第1絕緣層11被蝕刻之後,在第1絕緣層11上,選擇性地殘存觸媒吸附層20。 其次,在第1絕緣層11被蝕刻之領域選擇性地形成觸媒層30(圖1(d))。在第1絕緣層11上殘存之觸媒吸附層20上,藉由吸附電鍍觸媒而形成觸媒層30。 電鍍觸媒,只要會成為無電解電鍍之觸媒,則並未特別限定。例如,可以使用鈀(Pd)、銀(Ag)、銅(Cu)、金(Au)、鉑(Pt)。 觸媒層30之形成,係藉由使包含電鍍觸媒的溶液、接觸到觸媒吸附層20之表面而進行。觸媒吸附層20之表面、與包含電鍍觸媒的溶液之接觸時間,例如,為1分鐘以下。 其次,在觸媒層30上利用無電解電鍍法形成金屬層40(圖1(e))。金屬層40,係在觸媒層30上選擇性地形成。在第1絕緣層11被形成的溝是以金屬層40埋入。又,於圖1(e)省略觸媒層30之圖示。 金屬層40之材料,例如,為鎳(Ni)、銅(Cu)、鈷(Co)、金(Au)、鋅(Zn)、錫(Sn)、鉻(Cr)、釕(Ru)、或銀(Ag)。 金屬層40之形成,係藉由將基板10浸漬在電鍍液中而進行。電鍍液,例如,係包含金屬層40形成用之金屬離子、還原劑、使金屬離子安定化之安定劑。基板10往電鍍液中之浸漬時間,例如,為2分鐘以下。 其次,去除遮罩圖案32(圖1(f))。遮罩圖案32為光阻劑之場合,例如,使用鹼溶液去除遮罩圖案32。去除遮罩圖案32之後,在第1絕緣層11上,殘存觸媒吸附層20。 利用以上之製造方法,在設置於第1絕緣層11之溝內,設置金屬層40。金屬層40,係用作金屬配線。金屬層40,係具有所謂的金屬鑲嵌構造。 第1實施形態之金屬配線之形成方法,例如,係可以用於具有電晶體等元件之半導體裝置之金屬配線之形成。 其次,說明第1實施形態之作用及效果。 為了半導體裝置之低成本化,期待以低成本形成金屬配線。 圖2係比較例之金屬配線之形成方法之說明圖。圖2係形成金屬配線之製程之剖面圖。 最初,準備基板50。基板50,例如,為單晶矽基板。 其次,在基板50上形成第1絕緣層51。第1絕緣層51,例如,係氧化物、氮化物、或氧氮化物。 其次,在第1絕緣層51上形成與第1絕緣層51不同之第2絕緣層52(圖2(a))。第2絕緣層52,例如,係樹脂層。第2絕緣層52,例如,係光阻劑。 其次,將第2絕緣層52圖案化後形成遮罩圖案72(圖2(b))。例如,第2絕緣層52為光阻劑之場合,利用公知的微影法形成遮罩圖案72。 其次,將遮罩圖案72作為遮罩,蝕刻第1絕緣層51(圖2(c))。藉由蝕刻第1絕緣層51,在第1絕緣層51形成溝。 其次,剝離遮罩圖案72,在第1絕緣層51上形成觸媒吸附層60(圖2(d))。 其次,在觸媒吸附層60上形成觸媒層70(圖2(e))。 其次,在觸媒層70上利用無電解電鍍法形成金屬膜80a(圖2(f))。 其次,去除在第1絕緣層51被形成之溝以外之領域之金屬膜80a(圖2(g))。藉由去除金屬膜80a,形成金屬層80。金屬膜80a,例如,係利用CMP(Chemical Mechanical Polishing)而被去除。第1絕緣層51上的觸媒吸附層60也是利用CMP而與金屬膜80a同時被去除。此外,例如,金屬膜80a,利用濕式蝕刻而被去除。在濕式蝕刻使用之藥液,例如,係鹽酸/過氧化氫水、硝酸/過氧化氫水、硫酸/過氧化氫水。 於以上的比較例之金屬配線之形成方法,在金屬膜80a形成時,並無法在形成於第1絕緣層51之溝內選擇性地形成金屬膜80a。從而,使CMP或濕式蝕刻等去除金屬膜80a之製程成為必要。 相對於此,在第1實施形態之金屬配線之形成方法,是可以在形成於第1絕緣層11之溝內選擇性地形成金屬層40。從而,不需要CMP或濕式蝕刻等之製程。因而,可以低成本形成金屬配線。 以下,詳述在第1實施形態,利用濕式蝕刻法蝕刻第1絕緣層11之製程。圖3係第1實施形態的作用及效果之說明圖。 如上述,第1絕緣層11被蝕刻之後,在第1絕緣層11上,選擇性地殘存觸媒吸附層20。 在矽基板(Si)上,堆積氮化矽膜(SiN)與氧化矽膜(SiO
2),準備圖案化氮化矽膜(SiN)與氧化矽膜(SiO
2)後形成線條&空間圖案之第1試料。 將第1試料浸漬在三氮雜苯化合物水溶液中,形成觸媒吸附層。三氮雜苯化合物水溶液,係包含上述化學式(1)所示之三氮雜苯化合物。其次,在鈀溶液中,浸漬第1試料,形成觸媒層。然後,使用NiB電鍍液,形成鎳層(Ni)。 在形成觸媒吸附層之後、形成觸媒層之前,進行濕式蝕刻以外,製作出進行與第1試料同樣的處理之第2試料。濕式蝕刻之藥液,係使用氫氟酸。 圖3係利用SEM(Scanninng Electron Microscope)之第1試料與第2試料之鎳層形成後之剖面照片。圖3(a)係第1試料,圖3(b)係第2試料。 於圖3(a),鎳層在線條&空間圖案的空間內在線條上為共形地被形成。 圖3(b)之場合,在形成觸媒吸附層之後、形成觸媒層之前,藉由浸漬在氫氟酸的溶液,由氧化矽膜形成的線條被蝕刻且變細。由這可知,觸媒吸附層並未成為濕式蝕刻的遮罩,而氧化矽膜的蝕刻被推進。 再者,與第1試料同樣地,於第2試料,也是鎳層在線條&空間圖案的空間內在線條上為共形地被形成。由這可知,濕式蝕刻之後,仍有觸媒吸附層殘存在表面。 如此,在濕式蝕刻時觸媒吸附層並未成為蝕刻的遮罩之理由,及利用濕式蝕刻而下層的絕緣層被蝕刻後仍有觸媒吸附層殘存在表面之理由,未必清楚。例如,下層的絕緣層被蝕刻後仍有觸媒吸附層殘存在表面,考慮是觸媒吸附層的再附著等,但並沒有確認。 於第1實施形態之金屬配線之形成方法,係藉由利用上述特異的現象,而可以在形成於第1絕緣層11之溝內選擇性地形成金屬層40。 觸媒吸附層20之膜厚,最好是2nm以下。高於上述範圍的話,有觸媒吸附層20成為遮罩,而第1絕緣層11不被蝕刻之虞。 於第1實施形態,係以在金屬層40形成後去除遮罩圖案32之場合為例予以說明,例如,也可以並不去除遮罩圖案32,而利用作為層間絕緣層。 以上,根據第1實施形態之金屬配線之形成方法,可以在形成於絕緣層內之溝內,選擇性地形成金屬配線。從而,可以低成本形成金屬配線。 (第2實施形態) 第2實施形態之金屬配線之形成方法,係:在第1基板上形成第1絕緣層;使第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸後形成觸媒吸附層;在觸媒吸附層上形成與第1絕緣層不同之第2絕緣層;將第2絕緣層圖案化後形成遮罩圖案;將遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻第1絕緣層;在已蝕刻第1絕緣層之領域選擇性地形成觸媒層;在觸媒層上利用無電解電鍍法形成第1金屬層;在形成金屬層之後,去除遮罩圖案;以第1金屬層與第2金屬層相接之方式貼合第1基板、與形成第2金屬層的第2基板。 第2實施形態之金屬配線之形成方法,係於在第1基板上貼合第2基板之點上與第1實施形態不同。以下,針對與第1實施形態重複的內容,省略記載說明。 最初,在第1基板110與第2基板150形成金屬配線。 圖4係第2實施形態之第1基板之金屬配線之形成方法之說明圖。圖4係在第1基板形成金屬配線之製程之剖面圖。第1基板之金屬配線之形成方法,係與第1實施形態之金屬配線之形成方法相同。 最初,準備第1基板110。其次,在第1基板110上形成第1絕緣層111。其次,在第1絕緣層111上形成第1觸媒吸附層120。其次,在第1觸媒吸附層120上形成與第1絕緣層111不同之第2絕緣層112(圖4(a))。 其次,將第2絕緣層112圖案化後形成第1遮罩圖案132(圖4(b))。其次,將第1遮罩圖案132作為遮罩,利用濕式蝕刻法蝕刻第1絕緣層111(圖4(c))。 其次,在第1絕緣層111被蝕刻之領域選擇性地形成第1觸媒層130(圖4(d))。其次,在第1觸媒層130上利用無電解電鍍法形成第1金屬層140(圖4(e))。利用以上之製造方法,在第1基板110上,形成成為第1金屬配線之第1金屬層140。 圖5係第2實施形態之第2基板之金屬配線之形成方法之說明圖。圖5係在第2基板形成金屬配線之製程之剖面圖。第2基板之金屬配線之形成方法,係與第1實施形態之比較例之金屬配線之形成方法相同。 最初,準備第2基板150。其次,在第2基板150上形成第1絕緣層151。其次,在第1絕緣層151上形成與第1絕緣層151不同之第2絕緣層152(圖5(a))。 其次,將第2絕緣層152圖案化後形成第2遮罩圖案172(圖5(b))。其次,將第2遮罩圖案172作為遮罩,蝕刻第1絕緣層151(圖5(c))。 其次,剝離第2遮罩圖案172,在第1絕緣層151上形成第2觸媒吸附層160(圖5(d))。其次,在第2觸媒吸附層160上形成第2觸媒層170(圖5(e))。 其次,在第2觸媒層170上利用無電解電鍍法形成金屬膜180a(圖5(f))。其次,去除在第1絕緣層151被形成之溝以外之領域之金屬膜180a(圖5(g))。利用以上之製造方法,在第2基板150上,形成成為第2金屬配線之第2金屬層180。 圖6係第2實施形態之基板貼合方法之說明圖。圖6係貼合2枚基板之製程之剖面圖。 最初,準備金屬配線分開被形成之第1基板110與第2基板150(圖6(a))。 在第1基板110上,係採用與第1實施形態之金屬配線之形成方法相同方法,形成第1金屬層140。在第1基板110上,係形成第1絕緣層111、第1觸媒吸附層120、第1金屬層140。第1基板110、第1絕緣層111、第1觸媒吸附層120、第1金屬層140,係具有與第1實施形態之基板10、第1絕緣層11、觸媒吸附層20、金屬層40同樣的構成。 在第2基板150上,係採用與比較例之金屬配線之形成方法相同方法,形成第2金屬層180。在第2基板150上,係形成第1絕緣層151、第2觸媒吸附層160、第2金屬層180。第2基板150、第1絕緣層151、第2觸媒吸附層160、第2金屬層180,係具有與比較例之基板50、第1絕緣層51、觸媒吸附層60、金屬層80同樣的構成。 其次,使第2基板150之上下反轉(圖6(b))。 其次,貼合第1基板110與第2基板150(圖6(c))。第1基板110與第2基板150,係以第1金屬層140與第2金屬層180相接之方式貼合。例如,施加壓力以使第1基板110與第2基板150密貼。第1觸媒吸附層120作為黏接層之功能,結合第1基板110與第2基板150。 以下,說明第2實施形態之金屬配線之形成方法之作用及效果。 為了半導體裝置之多功能化或高積體化,有使用基板貼合之場合。基板貼合,係藉由將形成在不同基板之半導體裝置、層積並貼合而一體化。例如,藉由貼合具有不同功能之半導體裝置,可以實現半導體裝置之多功能化。此外,例如,藉由貼合具有同種功能之半導體裝置,可以實現半導體裝置之高積體化。於基板貼合,例如,藉由直接接合被形成在各基板表面之金屬配線彼此,而層積之半導體裝置間得以電性接續。 為了半導體裝置低成本化之採用基板貼合,期待能以低成本實現基板貼合之金屬配線之形成方法。 例如,考慮貼合以比較例之金屬配線之形成方法形成之2枚第2基板150之場合。該場合,在貼合前,或將第2基板150的表面進行電漿處理、或形成黏接層之追加製程是需要的。 於是,例如,在形成黏接層之場合,被要求避開表面的第2金屬層180的領域來形成。這是因為在貼合後的第2金屬層180之間介在黏接層的話,會有上下第2金屬層180的接觸電阻增加,不能得到層積的半導體裝置間的電性接續之疑慮之緣故。 於第2實施形態,在第1基板110表面的第1絕緣層111上,係形成第1觸媒吸附層120。在第1基板110與第2基板150貼合時,在第1基板110的第1絕緣層111、與第2基板的第1絕緣層151之間,存在第1觸媒吸附層120,該第1觸媒吸附層120是作為黏接層之功能。從而,在第1基板110與第2基板150貼合時,並不需要追加製程。從而,根據第2實施形態之金屬配線之形成方法,能以低成本實現基板貼合。 再者,於第1基板110,在表面的第1金屬層140之領域,並未形成第1觸媒吸附層120。換言之,第1觸媒吸附層120,係在第1絕緣層111上以自我對準(self-alignment)形成。從而,第1金屬層140與第2金屬層180之接觸電阻沒有增加。 以上,根據第2實施形態之金屬配線之形成方法,與第1實施形態同樣地,係能以低成本形成金屬配線。再者,可以低成本實現基板貼合。 (第3實施形態) 第3實施形態之金屬配線之形成方法,係:在第1基板上形成第1絕緣層;使第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之第1化合物之溶液接觸後形成第1觸媒吸附層;在第1觸媒吸附層上形成與第1絕緣層不同之第2絕緣層;將第2絕緣層圖案化後形成第1遮罩圖案;將第1遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻第1絕緣層;在已蝕刻第1絕緣層之領域選擇性地形成第1觸媒層;在第1觸媒層上利用無電解電鍍法形成第1金屬層;在形成第1金屬層之後,去除第1遮罩圖案;在第2基板上形成第3絕緣層;使第3絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之第2化合物之溶液接觸後形成第2觸媒吸附層;在第2觸媒吸附層上形成與第3絕緣層不同之第4絕緣層;將第4絕緣層圖案化後形成第2遮罩圖案;將第2遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻第4絕緣層;在已蝕刻第4絕緣層之領域選擇性地形成第2觸媒層;在第2觸媒層上利用無電解電鍍法形成第2金屬層;在形成第2金屬層之後,去除第2遮罩圖案;以第1金屬層與第2金屬層相接之方式貼合第1基板、與第2基板。 第3實施形態之金屬配線之形成方法,也採用與第1實施形態之金屬配線之形成方法相同形成第2基板之金屬配線以外,與第2實施形態相同。以下,針對與第1實施形態及第2實施形態重複的內容,省略記載說明。 最初,在第1基板110與第2基板210形成金屬配線。第1基板之金屬配線之製造方法,係與第2實施形態相同,因而省略。 圖7係第3實施形態之第2基板之金屬配線之形成方法之說明圖。圖7係在第2基板形成金屬配線之製程之剖面圖。第2基板之金屬配線之形成方法,係與第1實施形態之金屬配線之形成方法相同。 最初,準備第2基板210。其次,在第2基板210上形成第3絕緣層211。其次,在第3絕緣層211上形成觸媒吸附層220。其次,在觸媒吸附層220上形成與第3絕緣層211不同之第4絕緣層212(圖7(a))。 其次,將第4絕緣層212圖案化後形成第2遮罩圖案232(圖7(b))。其次,將第2遮罩圖案232作為遮罩,蝕刻第3絕緣層211(圖7(c))。 其次,在第3絕緣層211被蝕刻之領域選擇性地形成第2觸媒層230(圖7(d))。其次,在第2觸媒層230上利用無電解電鍍法形成第2金屬層240(圖7(e))。利用以上之製造方法,在第2基板210上,形成成為第2金屬配線之第2金屬層240。 圖8係第3實施形態之金屬配線之基板貼合方法之說明圖。圖8係貼合2枚基板之製程之剖面圖。 最初,準備金屬配線分開被形成之第1基板110與第2基板210(圖8(a))。 在第1基板110上,係採用與第1實施形態之金屬配線之形成方法相同方法,形成第1金屬層140。在第1基板110上,係形成第1絕緣層111、第1觸媒吸附層120、第1金屬層140。第1基板110、第1絕緣層111、第1觸媒吸附層120、第1金屬層140,係具有與第1實施形態之基板10、第1絕緣層11、觸媒吸附層20、金屬層40同樣的構成。 在第2基板210上,係採用與第1實施形態之金屬配線之形成方法相同方法,形成第2金屬層240。在第2基板210上,係形成第3絕緣層211、第2觸媒吸附層220、第2金屬層240。第2基板210、第3絕緣層211、第2觸媒吸附層220、第2金屬層240,係具有與第1實施形態之基板10、第1絕緣層11、觸媒吸附層20、金屬層40同樣的構成。 其次,使第2基板210之上下反轉(圖8(b))。 其次,貼合第1基板110與第2基板210(圖8(c))。第1基板110與第2基板210,係以第1金屬層140與第2金屬層240相接之方式貼合。 於第3實施形態,在第1基板110表面的第1絕緣層111上,係形成第1觸媒吸附層120。再者,也在第2基板210表面的第3絕緣層211上,形成第2觸媒吸附層220。 從而,提升第1基板110與第2基板210之黏接強度。因而,提升第1基板110與第2基板210之貼合強度。 以上,根據第3實施形態之金屬配線之形成方法,與第1實施形態同樣地,係能以低成本形成金屬配線。再者,與第2實施形態同樣地,可以低成本實現基板貼合。再者,提升第1基板110與第2基板210之貼合強度。 於第2實施形態或第3實施形態說明之基板貼合方法,例如,可以適用於半導體記憶體被形成的基板與邏輯IC被形成的基板之貼合。此外,也可以適用於半導體記憶體被形成的基板彼此貼合。此外,也可以適用於邏輯IC被形成的基板彼此貼合。可以適用於其它不同種或同種的半導體裝置被形成的基板間之貼合。 以上,說明了本發明的幾個實施形態,但這些實施形態只是提示作為例子之用,並未意圖限定發明的範圍。這些新穎的實施形態,能夠以其他種種形態來實施,在不逸脫發明要旨的範圍,可以進行種種的省略、置換、變更。例如,也可以將一實施形態之構成要素置換或變更為其它實施形態之構成要素。本發明的這些實施形態或者其變形,包含於發明的範圍或是要旨,同時包含於申請專利範圍所記載的發明以及其均等的範圍。
10:基板 11:第1絕緣層 12:第2絕緣層 20:觸媒吸附層 30:觸媒層 32:遮罩圖案 40:金屬層 110:第1基板 111:第1絕緣層 112:第2絕緣層 120:第1觸媒吸附層 130:第1觸媒層 132:第1遮罩圖案 140:第1金屬層 150:第2基板 180:第2金屬層 210:第2基板 211:第3絕緣層 212:第4絕緣層 220:第2觸媒吸附層 230:第2觸媒層 232:第2遮罩圖案 240:第2金屬層
圖1(a)~(f)係第1實施形態之金屬配線之形成方法之說明圖。 圖2(a)~(g)係比較例之金屬配線之形成方法之說明圖。 圖3(a)及(b)係第1實施形態之作用及效果之說明圖。 圖4(a)~(f)係第2實施形態之第1基板之金屬配線之形成方法之說明圖。 圖5(a)~(g)係第2實施形態之第2基板之金屬配線之形成方法之說明圖。 圖6(a)~(c)係第2實施形態之基板貼合方法之說明圖。 圖7(a)~(f)係第3實施形態之第2基板之金屬配線之形成方法之說明圖。 圖8(a)~(c)係第3實施形態之基板貼合方法之說明圖。
Claims (14)
- 一種金屬配線之形成方法,其特徵係:在基板上形成第1絕緣層;使前述第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸而形成觸媒吸附層;在前述觸媒吸附層上形成與前述第1絕緣層不同之第2絕緣層;將前述第2絕緣層圖案化而形成遮罩圖案;將前述遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻前述第1絕緣層;在已蝕刻前述第1絕緣層之領域選擇性地形成觸媒層;在前述觸媒層上利用無電解電鍍法形成金屬層。
- 如申請專利範圍第1項記載之金屬配線之形成方法,其中在形成前述金屬層之後,去除前述遮罩圖案。
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中前述化合物係以下述化學式(1)表示之化合物;化學式(1)中,A、B、C之內,至少一個為前述第1官能基,至少一個為前述第2官能基;R1、R2、R3為任意存在之連結基
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中前述第2絕緣層係樹脂。
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中前述第2絕緣層係光阻劑。
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中前述第1絕緣層係氧化物、氮化物、或氧氮化物。
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中前述觸媒吸附層之膜厚係2nm以下。
- 如申請專利範圍第1或2項記載之金屬配線之形成方法,其中在前述濕式蝕刻法使用之藥液,係包含氟化氫、氟化銨、或者磷酸。
- 一種金屬配線之形成方法,其特徵係:在第1基板上形成第1絕緣層;使前述第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之化合物之溶液接觸而形成觸媒吸附層;在前述觸媒吸附層上形成與前述第1絕緣層不同之第2絕緣層;將前述第2絕緣層圖案化而形成遮罩圖案;將前述遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻前述第1絕緣層;在已蝕刻前述第1絕緣層之領域選擇性地形成觸媒層;在前述觸媒層上利用無電解電鍍法形成第1金屬層;在形成前述第1金屬層之後,去除前述遮罩圖案;以前述第1金屬層與第2金屬層相接之方式貼合前述第1基板、與形成前述第2金屬層的第2基板。
- 如申請專利範圍第9項記載之金屬配線之形成方法,其中前述化合物係以下述化學式(1)表示之化合物;化學式(1)中,A、B、C之內,至少一個為前述第1官能基,至少一個為前述第2官能基;R1、R2、R3為任意存在之連結基
- 如申請專利範圍第9或10項記載之金屬配線之形成方法,其中前述第2絕緣層係樹脂。
- 一種金屬配線之形成方法,其特徵係:在第1基板上形成第1絕緣層;使前述第1絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之第1化合物之溶液接觸而形成第1觸媒吸附層;在前述第1觸媒吸附層上形成與前述第1絕緣層不同之第2絕緣層;將前述第2絕緣層圖案化而形成第1遮罩圖案;將前述第1遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻前述第1絕緣層;在已蝕刻前述第1絕緣層之領域選擇性地形成第1觸媒層;在前述第1觸媒層上利用無電解電鍍法形成第1金屬層;在形成前述第1金屬層之後,去除前述第1遮罩圖案;在第2基板上形成第3絕緣層;使前述第3絕緣層之表面,與包含具有三氮雜苯骨格、矽烷醇基及烷氧矽基之任一方之第1官能基、以及由胺基、氫硫基、羧基及疊氮基構成的群選擇出之至少一種第2官能基之第2化合物之溶液接觸而形成第2觸媒吸附層;在前述第2觸媒吸附層上形成與前述第3絕緣層不同之第4絕緣層;將前述第4絕緣層圖案化而形成第2遮罩圖案;將前述第2遮罩圖案作為遮罩,並利用濕式蝕刻法蝕刻前述第4絕緣層;在已蝕刻前述第4絕緣層之領域選擇性地形成第2觸媒層;在前述第2觸媒層上利用無電解電鍍法形成第2金屬層;在形成前述第2金屬層之後,去除前述第2遮罩圖案;以前述第1金屬層與前述第2金屬層相接之方式貼合前述第1基板、與前述第2基板。
- 如申請專利範圍第12項記載之金屬配線之形成方法,其中前述第1化合物及前述第2化合物係以下述化學式(1)表示之化合物;化學式(1)中,A、B、C之內,至少一個為前述第1官能基,至少一個為前述第2官能基;R1、R2、R3為任意存在之連結基
- 如申請專利範圍第12或13項記載之金屬配線之形成方法,其中前述第2絕緣層及前述第4絕緣層係樹脂。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08125121A (ja) * | 1994-08-29 | 1996-05-17 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TW200948476A (en) * | 2007-12-21 | 2009-12-01 | Lam Res Corp | Activation solution for electroless plating on dielectric layers |
US20130078570A1 (en) * | 2011-09-26 | 2013-03-28 | Atsushi Hieno | Method of forming pattern and laminate |
TW201434080A (zh) * | 2013-02-19 | 2014-09-01 | Taiwan Semiconductor Mfg | 半導體元件與其形成方法 |
US20160035948A1 (en) * | 2014-07-31 | 2016-02-04 | Kabushiki Kaisha Toshiba | Electronic component and electronic unit |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2797650B2 (ja) | 1990-05-21 | 1998-09-17 | 松下電器産業株式会社 | 半導体素子の実装方法 |
KR960009074A (ko) | 1994-08-29 | 1996-03-22 | 모리시다 요이치 | 반도체 장치 및 그 제조방법 |
JP2003149831A (ja) | 2001-11-09 | 2003-05-21 | Seiko Epson Corp | 単分子層のパターン形成方法、パターン化単分子層を利用した導電膜パターンの形成方法、及び電気光学装置 |
TWI286372B (en) * | 2003-08-13 | 2007-09-01 | Phoenix Prec Technology Corp | Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same |
TWI288448B (en) * | 2004-09-10 | 2007-10-11 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
JPWO2010010792A1 (ja) * | 2008-07-24 | 2012-01-05 | コニカミノルタホールディングス株式会社 | 導電性パターン形成方法及び有機薄膜トランジスタ |
JP5398678B2 (ja) * | 2010-09-29 | 2014-01-29 | 株式会社東芝 | 光電変換素子 |
JP5479391B2 (ja) * | 2011-03-08 | 2014-04-23 | 株式会社東芝 | 半導体発光素子及びその製造方法 |
JP5772329B2 (ja) | 2011-07-19 | 2015-09-02 | ソニー株式会社 | 半導体装置の製造方法、半導体装置、電子機器 |
JP2013258352A (ja) * | 2012-06-14 | 2013-12-26 | Shindo Denshi Kogyo Kk | 配線基板の製造方法、および配線基板 |
JP2015207678A (ja) * | 2014-04-22 | 2015-11-19 | 京セラサーキットソリューションズ株式会社 | 配線基板の製造方法 |
US20170294408A1 (en) * | 2016-04-08 | 2017-10-12 | Kabushiki Kaisha Toshiba | Semiconductor device that includes a molecular bonding layer for bonding elements |
JP2018049944A (ja) * | 2016-09-21 | 2018-03-29 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体製造装置 |
-
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2018
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08125121A (ja) * | 1994-08-29 | 1996-05-17 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TW200948476A (en) * | 2007-12-21 | 2009-12-01 | Lam Res Corp | Activation solution for electroless plating on dielectric layers |
US20130078570A1 (en) * | 2011-09-26 | 2013-03-28 | Atsushi Hieno | Method of forming pattern and laminate |
US20150261092A1 (en) * | 2011-09-26 | 2015-09-17 | Kabushiki Kaisha Toshiba | Method of forming pattern and laminate |
TW201434080A (zh) * | 2013-02-19 | 2014-09-01 | Taiwan Semiconductor Mfg | 半導體元件與其形成方法 |
US20160035948A1 (en) * | 2014-07-31 | 2016-02-04 | Kabushiki Kaisha Toshiba | Electronic component and electronic unit |
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