TWI661522B - 半導體封裝以及中介層 - Google Patents

半導體封裝以及中介層 Download PDF

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Publication number
TWI661522B
TWI661522B TW107111462A TW107111462A TWI661522B TW I661522 B TWI661522 B TW I661522B TW 107111462 A TW107111462 A TW 107111462A TW 107111462 A TW107111462 A TW 107111462A TW I661522 B TWI661522 B TW I661522B
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TW
Taiwan
Prior art keywords
bump
under
interposer
layer
metal pad
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TW107111462A
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English (en)
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TW201929169A (zh
Inventor
許智愛
Jee Ae Heo
Original Assignee
南韓商三星電機股份有限公司
Samsung Electro-Mechanics Co., Ltd.
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Application filed by 南韓商三星電機股份有限公司, Samsung Electro-Mechanics Co., Ltd. filed Critical 南韓商三星電機股份有限公司
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Publication of TWI661522B publication Critical patent/TWI661522B/zh
Publication of TW201929169A publication Critical patent/TW201929169A/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

一種半導體封裝，包括有機中介層、半導體晶片、保護 層及凸塊下金屬(UBM)層。有機中介層包括絕緣層及設置於絕緣層上的配線層。半導體晶片設置於有機中介層的一個表面上。保護層設置於有機中介層的與上面設置有半導體晶片的所述一個表面相對的另一表面上且具有延伸至配線層的一部分的開口。凸塊下金屬層包括設置於保護層上的凸塊下金屬接墊及設置於開口中且將凸塊下金屬接墊與配線層連接至彼此的凸塊下金屬通孔。至少一個凹槽部分設置於凸塊下金屬接墊的外圓周表面中。

Description

半導體封裝以及中介層
本申請案主張於2017年12月15日在韓國智慧財產局提出申請的韓國專利申請案第10-2017-0173580號的優先權，所述韓國專利申請案的揭露內容全文併入本案供參考。
本發明是有關於一種半導體封裝。
隨著高頻寬記憶體(high bandwidth memory，HBM)的規格的改善以及高頻寬記憶體的使用增加，中介層的市場已生長壯大。當前，主要使用矽作為中介層的材料，但為了增大面積且降低成本已對玻璃或有機中介層進行了開發。
同時，在將中介層與板(例如主板)連接至彼此的焊料球之下添加凸塊下金屬(underbump metallurgy，UBM)層以減輕熱衝擊或機械衝擊，進而提高封裝的可靠性及壽命。然而，內連部分的可靠性受凸塊下金屬層的結構影響，且因此需要使凸塊下金屬層的結構最佳化。
本發明的態樣可提供一種其中可確保電性連接結構的 高可靠性的半導體封裝。
根據本揭露的態樣，可提供一種其中在電性連接結構之下引入凸塊下金屬(UBM)層且凸塊下金屬層的凸塊下金屬接墊被設置成具有包括突出形狀而非圓形形狀的輪廓以增加電性連接結構與凸塊下金屬接墊之間的結合面積的半導體封裝。
根據本揭露的態樣，一種半導體封裝可包括有機中介層、半導體晶片、包封體、保護層及凸塊下金屬層。所述有機中介層包括絕緣層及設置於所述絕緣層上的配線層。所述半導體晶片設置於所述有機中介層的一個表面上且具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊。所述包封體設置於所述有機中介層上且包封所述半導體晶片的至少一部分。所述保護層設置於所述有機中介層的與所述有機中介層的上面設置有所述半導體晶片的所述一個表面相對的另一表面上，且具有開口，所述開口延伸至所述配線層的至少一部分。所述凸塊下金屬層包括凸塊下金屬接墊及凸塊下金屬通孔，所述凸塊下金屬接墊設置於所述保護層上，所述凸塊下金屬通孔設置於所述開口中且將所述凸塊下金屬接墊與所述配線層連接至彼此。至少一個凹槽部分設置於所述凸塊下金屬接墊的外圓周表面中。
根據本揭露的另一態樣，一種半導體封裝可包括半導體晶片、包封體、連接構件、保護層及凸塊下金屬層。所述半導體晶片具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊。所述包封體包封所述半導體晶片的至 少一部分，且所述連接構件設置於所述半導體晶片的所述主動表面上且包括電性連接至所述連接接墊的配線層。所述保護層設置於所述連接構件上且具有開口，所述開口延伸至所述配線層的至少一部分。所述凸塊下金屬層包括凸塊下金屬接墊及凸塊下金屬通孔，所述凸塊下金屬接墊設置於所述保護層上，所述凸塊下金屬通孔設置於所述開口中且將所述凸塊下金屬接墊與被暴露出的所述配線層連接至彼此。當自與所述保護層的表面垂直的方向觀察所述凸塊下金屬接墊時，所述凸塊下金屬接墊的邊界包括至少一凹形部分。
根據本揭露的再一態樣，一種中介層，所述中介層被配置成在所述中介層的上表面上安裝有半導體晶片，所述中介層包括形成所述中介層的主體的絕緣材料、多個配線層及多個通孔、保護層及至少一個連接接墊。所述多個配線層設置於所述主體的絕緣材料中，且設置於所述中介層的所述上表面上以連接至所述半導體晶片的連接接墊。所述多個通孔穿透所述主體的所述絕緣材料以對所述多個配線層中的相鄰的配線層進行內連。所述保護層設置於所述中介層的與所述上表面相對的下表面上且具有多個開口，所述多個開口各自延伸至配線層。所述至少一個連接接墊設置於所述保護層的下表面上且經由連接通孔連接至所述配線層，所述連接通孔延伸穿過所述多個開口中的開口。所述保護層的所述下表面上的被所述至少一個連接接墊佔據的區域的輪廓包括至少一凹形部分。
100A、100B、2310、2320‧‧‧半導體封裝
110、2230‧‧‧中介層
111‧‧‧絕緣層
112‧‧‧配線層
112S‧‧‧連接圖案
113‧‧‧通孔
113S‧‧‧連接通孔
120‧‧‧底部填充樹脂
131‧‧‧半導體晶片/應用專用記憶體電路
131B、132B、133B‧‧‧低熔點金屬
131P、132P、133P‧‧‧連接接墊
132‧‧‧半導體晶片/記憶體
133‧‧‧半導體晶片/記憶體
135‧‧‧連接構件
140‧‧‧包封體
150‧‧‧保護層
151‧‧‧壓痕/開口
160‧‧‧凸塊下金屬層
160P‧‧‧凸塊下金屬接墊
160Ph‧‧‧凹槽部分
160V‧‧‧凸塊下金屬通孔
170‧‧‧電性連接結構/連接結構
1000‧‧‧電子裝置
1010、2110‧‧‧主板
1020‧‧‧晶片相關組件
1030‧‧‧網路相關組件
1040‧‧‧其他組件
1050、1130‧‧‧照相機模組
1060‧‧‧天線
1070‧‧‧顯示器裝置
1080‧‧‧電池
1090‧‧‧訊號線
1100‧‧‧智慧型電話
1101‧‧‧主體
1110‧‧‧母板
1120‧‧‧電子組件
1121‧‧‧中介層封裝
2210‧‧‧球柵陣列基板
2220‧‧‧圖形處理單元/晶片
2240‧‧‧高頻寬記憶體/晶片
2250‧‧‧矽中介層
2260‧‧‧有機中介層/中介層
A‧‧‧區
d1、d2‧‧‧距離
I-I'‧‧‧線
藉由結合附圖閱讀以下詳細說明，將更清晰地理解本揭露的以上及其他態樣、特徵及優點，在附圖中：圖1是示出電子裝置系統的實例的示意性方塊圖。
圖2是示出電子裝置的實例的示意性立體圖。
圖3是示出安裝於電子裝置的主板上的三維(three dimensional，3D)球柵陣列(ball grid array，BGA)封裝的示意性剖視圖。
圖4是示出安裝於主板上的2.5維(2.5 dimension，2.5D)矽中介層封裝的示意性剖視圖。
圖5是示出安裝於主板上的2.5維有機中介層封裝的示意性剖視圖。
圖6是示出半導體封裝的實例的示意性剖視圖。
圖7是沿圖6所示半導體封裝的線I-I'截取的示意性平面圖。
圖8是圖6所示半導體封裝的區A的示意性放大平面圖。
圖9是示出半導體封裝的另一實例的示意性剖視圖。
以下，將參照附圖闡述本揭露中的各示例性實施例。在所述附圖中，為清晰起見，可將各組件的形狀、大小等誇大或風格化。
在本文中，下側、下部部分、下表面等用於指代相對於所述圖式的橫截面朝向包括有機中介層的半導體封裝的安裝表面 的方向，而上側、上部部分、上表面等用於指代與下部方向相反的方向。然而，該些方向是出於解釋方便而進行界定的，且申請專利範圍並非特別受限於上述所界定的方向。
在說明中組件與另一組件的「連接(connection)」的意義包括經由黏合層的間接連接以及兩個組件之間的直接連接。另外，「電性連接(electrically connected)」包括實體連接及儘管如此仍會提供電性連接的實體斷開。應理解，當以「第一(first)」及「第二(second)」來指代元件時，所述元件並非由此受到限制。用語「第一」及「第二」可能僅用於將一個元件與其他元件區分開的目的，且可不限制所述元件的順序或重要性。在一些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。
本文中所使用的用語「示例性實施例」並不指代同一示例性實施例，而是為強調與另一示例性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的示例性實施例被視為能夠藉由彼此整體地或部分地組合而實作。舉例而言，即使並未在另一示例性實施例中闡述在特定示例性實施例中闡述的一個元件，然而除非在本文中提供了相反或矛盾的說明，否則所述元件亦可被理解為與所述另一示例性實施例相關的說明。
使用本文中所使用的用語僅是為了闡述示例性實施例而非限制本揭露。在此種情形中，除非在上下文中另有解釋，否 則單數形式包括複數形式。
電子裝置
圖1是示出電子裝置系統的實例的示意性方塊圖。
參照圖1，電子裝置1000中可容置有主板1010。主板1010可包括實體連接至或電性連接至主板1010的晶片相關組件1020、網路相關組件1030其他組件1040等。該些組件可穿過各種訊號線1090連接至以下將闡述的其他組件。
晶片相關組件1020或晶片組可包括：記憶體晶片，例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory，ROM))、快閃記憶體等；應用處理器晶片，例如中央處理器(例如中央處理單元(central processing unit，CPU))、圖形處理器(例如圖形處理單元(graphics processing unit，GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器等；及邏輯晶片，例如類比至數位轉換器(analog-to-digital converter，ADC)、應用專用積體電路(application-specific integrated circuit，ASIC)等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。
網路相關組件1030可包括利用各種協定支援通訊的組件：例如，無線保真(wireless fidelity，Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers，IEEE) 802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communications，GSM)、全球定位系統(global positioning system，GPS)、通用封包無線電服務(general packet radio service，GPRS)、分碼多重存取(code division multiple access，CDMA)、分時多重存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G協定、4G協定及5G協定、以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與上述晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器、鐵氧體珠粒、低溫共燒陶瓷(low temperature co-fired ceramic，LTCC)、電磁干擾(electromagnetic interference，EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor，MLCC)等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。另外，其他組件1040可與上述晶片相關元件1020或網路相關元件1030一起相互組合。
端視電子裝置1000的類型而定，電子裝置1000可包括可物理性地連接至或電性地連接至主板1010或可不物理性地連接至或不電性地連接至主板1010的其他組件。該些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存單元(例如，硬碟驅動機)(圖中未示出)、光碟(compact disk，CD)驅動機(圖中未示出)、數位多功能光碟(digital versatile disk，DVD)驅動機(圖中未示出)等。然而，該些其他組件並非僅限於此，而是端視電子裝置1000等的類型亦可包括用於各種目的之其他組件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant，PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、膝上型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶、汽車組件等。然而，電子裝置1000並非僅限於此，而是可為處理資料的任何其他電子裝置。
圖2是示出電子裝置的實例的示意性立體圖。
參照圖2，包括有機中介層的半導體封裝可出於各種目的而在如上所述的各種電子裝置1000中使用。舉例而言，母板1110可容置於智慧型電話1100的主體1101中，且各種電子組件1120可物理性地連接至或電性地連接至母板1110。另外，可物理性地連接至或電性地連接至母板1110或可不物理性地連接至或不電性地連接至母板1110的其他組件(例如照相機模組1130)可容置於主體1101中。電子組件1120中的一些可為晶片相關組件，且晶片相關組件中的一些可為中介層封裝1121。同時，所述電子裝置未必僅限於智慧型電話1100，而是可為其他電子裝置。
包括有機中介層的半導體封裝
一般而言，在半導體晶片中整合有諸多精細的電路。然而，半導體晶片本身可能無法用作成品的半導體產品，且可因外部物理衝擊或化學衝擊而被損壞。因此，半導體晶片可能無法單獨使用，而是可被封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。
此處，可需要進行半導體封裝，乃因於電性連接方面，半導體晶片與電子裝置的主板之間存在電路寬度差。詳細而言，半導體晶片的連接接墊的大小及半導體晶片的各連接接墊之間的間隔是非常精細的，但在電子裝置中使用的主板的組件安裝接墊的大小及主板的各組件安裝接墊之間的間隔顯著地大於半導體晶片的連接接墊的大小及各連接接墊之間的間隔。因此，可能難以 將半導體晶片直接安裝於主板上，且可有利地利用用於緩衝半導體晶片與主板之間的電路寬度差的封裝技術。
以下將參照圖式更詳細地闡述藉由上述封裝技術製造的包括有機中介層的半導體封裝。
圖3是示出安裝於電子裝置的主板上的三維球柵陣列(ball grid array，BGA)封裝的示意性剖視圖。
半導體晶片中的應用專用積體電路(application specific integrated circuit，ASIC)(例如圖形處理單元(graphics processing unit，GPU))非常昂貴，且因此以高的良率對應用專用積體電路執行封裝非常重要。為此，在將半導體晶片安裝於可對數千至數十萬個連接接墊進行重佈線的球柵陣列(ball grid array，BGA)基板2210等上之前，製備球柵陣列(BGA)基板2210等，且藉由表面安裝技術(surface mounting technology，SMT)等將例如圖形處理單元2220等昂貴的半導體晶片安裝並封裝於球柵陣列基板2210上，並接著最終安裝於主板2110上。
同時，在為圖形處理單元2220的情形中，有利的是顯著縮短圖形處理單元2220與例如高頻寬記憶體(high bandwidth memory，HBM)等記憶體之間的訊號路徑。為此，可使用其中將例如高頻寬記憶體2240等半導體晶片安裝並接著封裝於中介層2230上並且然後堆疊於其中安裝有圖形處理單元2220的封裝上的層堆疊封裝(package-on-package，POP)形式的產品。然而，在此種情形中，裝置的厚度過度增大，且在顯著縮短訊號路徑方 面存在限制。
圖4是示出安裝於主板上的2.5維矽中介層封裝的示意性剖視圖。
關於一種解決上述問題的方法，可考量藉由2.5維中介層表面安裝技術且接著將例如圖形處理單元2220等第一半導體晶片以及例如高頻寬記憶體2240等第二半導體晶片彼此並排地封裝於矽中介層2250上來製造包括有機中介層的半導體封裝2310。在此種情形中，具有數千至數十萬個連接接墊的圖形處理單元2220及高頻寬記憶體2240可藉由矽中介層2250進行重佈線，且可經由最短的路徑電性連接至彼此。另外，當將包括矽中介層2250的半導體封裝2310再次安裝並重佈線於球柵陣列基板2210等上時，半導體封裝2310可最終安裝於主板2110上。然而，很難在矽中介層2250中形成矽穿孔(through-silicon via，TSV)，且製造矽中介層2250的成本為顯著高的，並且因此矽中介層2250不利於增大面積及降低成本。
圖5是示出安裝於主板上的另一2.5維有機中介層封裝的示意性剖視圖。
作為用於解決上述問題的方法，可考量使用有機中介層2260來代替矽中介層2250。舉例而言，製造半導體封裝2320可包括：利用2.5維中介層表面安裝技術的有機中介層2260，且接著將例如圖形處理單元2220等第一半導體晶片以及例如高頻寬記憶體2240等第二半導體晶片彼此並排地封裝於有機中介層2260 上。在此種情形中，具有數千至數十萬個連接接墊的圖形處理單元2220及高頻寬記憶體2240可藉由有機中介層2260進行重佈線，且可經由最短的路徑電性連接至彼此。另外，當將包括有機中介層2260的半導體封裝2320再次安裝並重佈線於球柵陣列基板2210等上時，半導體封裝2320可最終安裝於主板2110上。另外，有機中介層2260可有利地增大面積且降低成本。
同時，藉由執行在有機中介層2260上安裝晶片2220及2240且接著對所述晶片進行模制的封裝製程來製造包括有機中介層2260的半導體封裝2320。原因在於當不執行模制製程時，不進行封裝處理，因而使得所述封裝可能無法連接至球柵陣列基板2210等。因此，封裝的剛性是藉由模制來維持。然而，當執行模制製程時，封裝可能會出現翹曲，底部填充樹脂的可填充性會劣化，且由於中介層2260的熱膨脹係數(coefficient of thermal expansion，CTE)與上述晶片2220及2240的模制材料之間的失配而使得晶粒與模制材料之間可能出現裂縫。
為解決以上詳細闡述的缺陷，以下將參照圖式闡述其中可確保電性連接結構的高可靠性的半導體封裝。
圖6是示出半導體封裝的實例的示意性剖視圖。
圖7是沿圖6所示半導體封裝的線I-I'截取的示意性平面圖。
圖8是圖6所示半導體封裝的區A的示意性放大平面圖。圖8所示視圖可自設置於圖6所示半導體封裝上方的視角(例 如與提供圖7的平面圖的視角相同的視角)來提供。
參照圖6至圖8，根據本揭露中的示例性實施例的半導體封裝100A可包括中介層110，中介層110包括絕緣層111以及形成於絕緣層111上及絕緣層111中的配線層112及通孔113。半導體封裝100A更包括第一半導體晶片131，第一半導體晶片131設置於中介層110上且具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊131P。半導體封裝100A更包括多個第二半導體晶片132及133，所述多個第二半導體晶片132及133分別與第一半導體晶片131並排地設置於中介層110上且具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊132P及133P。半導體封裝100A更包括：包封體140，設置於中介層110上且包封第一半導體晶片131的至少一部分以及所述多個第二半導體晶片132及133的至少一部分；保護層150，設置於中介層的另一表面上且具有暴露出配線層112的至少一部分的開口；凸塊下金屬(UBM)層160，包括凸塊下金屬接墊160P及凸塊下金屬通孔160V，凸塊下金屬接墊160P設置於保護層150上，凸塊下金屬通孔160V形成於保護層150的開口中且將凸塊下金屬接墊160P與被暴露出的配線層112連接至彼此；以及電性連接結構170，設置於保護層150上且連接至凸塊下金屬接墊160P。
同時，自凸塊下金屬接墊160P的中心至凸塊下金屬接墊160P的邊界的距離可為無規律的。舉例而言，自凸塊下金屬接 墊160P的中心至距中心最遠的邊界的距離d1與自凸塊下金屬接墊160P的中心至最靠近中心的邊界的距離d2可彼此不同。更詳細而言，至少一個凹槽部分160Ph、更佳地多個凹槽部分160Ph可形成於凸塊下金屬接墊160P的外圓周表面中。在此種情形中，距離d1可自凸塊下金屬接墊160P的中心延伸至其中未形成有凸塊下金屬接墊160P的凹槽部分160Ph的區的外圓周表面，且距離d1可大於距離d2，距離d2自凸塊下金屬接墊160P的中心延伸至其中形成有凸塊下金屬接墊160P的凹槽部分160Ph的區的外圓周表面。凸塊下金屬接墊160P的凹槽部分160Ph可被電性連接結構170填充。如上所述，根據示例性實施例的半導體封裝100A包括凸塊下金屬層160，且因此電性連接結構170的可靠性可進一步提高。具體而言，凸塊下金屬接墊160P不是具有簡單的圓形形狀，而是可具有例如在平面中具有突出部分的齒輪形狀，以增大凸塊下金屬接墊160P與電性連接結構170之間的接觸面積從而具有錨定效果且分散剪切應力，進而進一步提高電性連接結構170的可靠性。齒輪形狀可包括彼此間隔開且自凸塊下金屬接墊的中心部分延伸的多個齒突出部。當自與保護層的表面垂直的方向觀察時，凸塊下金屬接墊160P可具有包括至少一凹形部分的不均勻的邊界。
以下將在下文中更詳細地闡述包含於根據示例性實施例的半導體封裝100A中的相應組件。
中介層110可對半導體晶片131、132及133的連接接 墊131P、132P及133P進行重佈線。半導體晶片131、132及133的具有各種功能的數千至數十萬個連接接墊131P、132P及133P可藉由中介層110被重佈線，且可端視所述功能而藉由電性連接結構170物理性地或電性地連接至外部。另外，半導體晶片131、132及133的連接接墊131P、132P及133P可藉由中介層110經由最短的路徑電性連接至彼此。亦即，中介層110可用作連接構件。中介層110可包括：絕緣層111；配線層112，形成於絕緣層111上或絕緣層111中；以及通孔113，穿透絕緣層111且將在不同層上形成的配線層112電性連接至彼此。中介層110的層數可多於圖式中所示的數目或少於圖式中所示的數目。具有此種形式的中介層110可用作2.5維型有機中介層。
絕緣層111可用作中介層110的介電層。舉例而言，可使用絕緣材料作為絕緣層111的材料。在此種情形中，可使用以下材料作為所述絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；其中將熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂，例如味之素構成膜(Ajinomoto build-up film，ABF)等。作為另一選擇，亦可使用其中將熱固性樹脂或熱塑性樹脂與無機填料一起浸入於例如玻璃纖維(或玻璃布或玻璃織物)等核心材料中的樹脂(例如，預浸體等)作為絕緣材料。作為另一選擇，可使用例如感光成像介電(photoimageable dielectric，PID)樹脂等感光性絕緣材料作為所述絕緣材料。當絕緣層111包括多個層時，若需要，則絕緣層111的材料可彼此相同，且作為另一 選擇亦可彼此不同。當絕緣層111包括多個層時，絕緣層111可端視製程而彼此整合於一起，進而使得各絕緣層111之間的邊界可不明顯。
配線層112可用於實質上對連接接墊131P、132P及133P進行重佈線，且端視訊號、功率等將連接接墊131P、132P及133P連接至彼此及/或連接結構170。亦即，連接接墊131P、132P及133P可經由配線層112的連接圖案112S及連接通孔113S電性連接至彼此。配線層112中的每一者的材料可為例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料。配線層112可端視其對應層的設計而執行各種功能。舉例而言，配線層112可包括接地(ground，GND)圖案、電源(power，PWR)圖案、訊號(signal，S)圖案等。此處，訊號(S)圖案可包括除接地(GND)圖案、電源(PWR)圖案等之外的各種訊號，例如資料訊號等。另外，配線層112可包括孔墊(via pad)、電性連接結構接墊(electrical connection structures pad)等。表面處理層可形成於用作接墊的圖案的表面上以將半導體晶片131、132及133安裝於配線層112中。表面處理層無特別限制，且可藉由例如電解鍍金、無電鍍金、有機可焊性保護(organic solderability preservative，OSP)或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(direct immersion gold，DIG)鍍敷、熱空氣焊料均塗(hot air solder leveling，HASL)等形成。
通孔113可將在不同層上形成的配線層112電性連接至 彼此，進而在半導體封裝100A中形成電性路徑。通孔113中的每一者的材料可為例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料。通孔113可被導電材料完全填充，但並非僅限於此。通孔113中的每一者的橫截面形狀可為近似倒梯形形狀，如圖式所示。
底部填充樹脂120可將半導體晶片131、132及133固定至中介層110。可使用包括環氧樹脂等的材料作為底部填充樹脂120的材料。若需要，則底部填充樹脂120可被省略。同時，儘管圖式中未示出，然而若需要，則亦可在中介層110上與半導體晶片131、132及133並聯地(或相鄰地)設置及封裝被動組件。
半導體晶片131、132及133中的每一者可為提供整合於單個晶片中的數百個至數百萬個元件或更多元件的積體電路(integrated circuit，IC)。在此種情形中，半導體晶片中的每一者的主體的基材(base material)可為矽(Si)、鍺(Ge)、砷化鎵(GaAs)等。可在主體中的每一者上形成各種電路。半導體晶片131、132及133的連接接墊131P、132P及133P可將半導體晶片131、132及133電性連接至其他組件。連接接墊131P、132P及133P中的每一者的材料可為例如鋁(Al)等導電材料。可在主體中的每一者上形成暴露出連接接墊131P、132P及133P的保護層，且所述保護層可為氧化物膜、氮化物膜等或者氧化物層與氮化物層構成的雙層。亦可在適當的位置中進一步設置絕緣層等。重佈線層可更形成於半導體晶片131、132及133的主動表面上，且低熔點金 屬131B、132B及133B等亦可分別連接至連接接墊131P、132P及133P。低熔點金屬131B、132B及133B可為熔點低於連接接墊131P、132P及133P的熔點的金屬，例如焊料或包含焊料的合金。半導體晶片131、132及133可經由連接接墊131P、132P及133P及/或經由低熔點金屬131B、132B及133B連接至中介層110的上部部分的被暴露出的配線層112，且可使用例如焊料等連接構件135來進行連接。相應的半導體晶片131、132及133可藉由底部填充樹脂120而被固定至中介層110。
第一半導體晶片131可為應用專用積體電路(例如圖形處理單元)。所述多個第二半導體晶片132及133中的每一者可為記憶體(例如高頻寬記憶體)。亦即，半導體晶片131、132及133中的每一者可為具有數十萬個或更多個輸入/輸出(input/outputs，I/O)的昂貴晶片，但未必僅限於此。第一記憶體及第二記憶體132(例如高頻寬記憶體等)可與應用專用積體電路131(例如圖形處理單元等)並排地設置於應用專用積體電路131的一側，且第三記憶體及第四記憶體133(例如高頻寬記憶體等)可與應用專用積體電路131(例如圖形處理單元等)並排地設置於應用專用積體電路131的另一側。
包封體140可保護半導體晶片131、132及133等。包封體140的包封形式無特別限制，而是可為其中包封體140環繞半導體晶片131、132及133的至少一部分的形式。包封體140的材料無特別限制。舉例而言，可使用絕緣材料作為包封體140的 材料。在此種情形中，可使用以下材料作為所述絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；其中將熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂，例如味之素構成膜等。然而，包封體140的材料並非僅限於此，而是亦可為預浸體等，包括玻璃纖維。作為另一選擇，亦可使用環氧模製化合物(epoxy molding compound，EMC)等作為包封體140的材料。半導體晶片131、132及133的非主動表面可藉由研磨製程而自包封體140暴露出。在此種情形中，半導體晶片131、132及133的非主動表面可設置於與包封體140的上表面的水平高度相同的水平高度上。用語「相同的水平高度」是包括其中各水平高度彼此近似相同(即，包括製程中的誤差)的情形以及其中各水平高度彼此完全相同的情形的概念。
保護層150可保護中介層110不受外部物理衝擊或化學衝擊。保護層150的材料無特別限制。舉例而言，可使用絕緣材料作為保護層150的材料。在此種情形中，絕緣材料可為被闡述為上述中介層110的絕緣層111的絕緣材料的材料，例如，味之素構成膜。保護層150可具有暴露出配線層112的至少一部分的開口。
凸塊下金屬層160可提高電性連接結構170的連接可靠性以提高半導體封裝100A的板級可靠性(board level reliability)。凸塊下金屬層160可包括凸塊下金屬接墊160P及凸塊下金屬通孔160V，凸塊下金屬接墊160P設置於保護層150上， 凸塊下金屬通孔160V形成於保護層150的開口中且將凸塊下金屬接墊160P與被暴露出的配線層112連接至彼此。凸塊下金屬接墊160P及凸塊下金屬通孔160V中的每一者可包含例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等金屬。
自凸塊下金屬接墊160P的中心至凸塊下金屬接墊160P的邊界的距離可為無規律的。舉例而言，自凸塊下金屬接墊160P的中心至距中心最遠的邊界的距離d1與自凸塊下金屬接墊160P的中心至最靠近中心的邊界的距離d2可彼此不同。更詳細而言，至少一個凹槽部分160Ph、更佳地多個凹槽部分160Ph可形成於凸塊下金屬接墊160P的外圓周表面中。在此種情形中，自凸塊下金屬接墊160P的中心至其中未形成有凸塊下金屬接墊160P的凹槽部分160Ph的區的外圓周表面的距離d1可大於自凸塊下金屬接墊160P的中心至其中形成有凸塊下金屬接墊160P的凹槽部分160Ph的區的外圓周表面的距離d2。凸塊下金屬接墊160P的凹槽部分160Ph可被設置成當設置電性連接結構170時，容置電性連接結構170的一部分，電性連接結構170可填充凹槽部分160Ph。如上所述，根據示例性實施例的半導體封裝100A包括具有上述結構的凸塊下金屬層160，且因此電性連接結構170的可靠性可進一步提高。具體而言，凸塊下金屬接墊160P不是具有簡單的圓形形狀，而是可具有例如在平面中具有突出部分的齒輪形狀，以增大凸塊下金屬接墊160P與電性連接結構170之間的接觸面積從而具 有錨定效果且分散剪切應力，進而進一步提高電性連接結構的可靠性。在示例性實施例中，凸塊下金屬接墊160P可突出於保護層150上。同時，凸塊下金屬接墊160P的凹槽部分160Ph的數目等無特別限制，而是可多於圖式中所示的數目等或可少於圖式中所示的數目等。另外，凹槽部分160Ph可具有角形狀而非圓形形狀。亦即，凹槽部分160Ph的詳細形狀可進行各種修改。
凸塊下金屬通孔160V的與中介層110的被暴露出的配線層112接觸的上表面的寬度可小於凸塊下金屬通孔160V的與凸塊下金屬接墊160P接觸的下表面的寬度。此處，寬度是相對於剖視圖來決定。在根據示例性實施例的半導體封裝100A中，中介層110是藉由最後凸塊下金屬層方法(UBM layer last method)來形成，且因此凸塊下金屬通孔160V可被形成為其中凸塊下金屬通孔160V的上表面的寬度小於凸塊下金屬通孔160V的下表面的寬度的梯形形狀。另外，凸塊下金屬通孔160V可為近似填充通孔(filled-via)。
電性連接結構170可將半導體封裝100A物理性地及/或電性地連接至外部。舉例而言，半導體封裝100A可經由電性連接結構170而安裝於球柵陣列基板等上。電性連接結構170中的每一者可由導電材料(例如包括錫(Sn)-鋁(Al)-銅(Cu)合金的焊料等)形成。然而，此僅為實例，且電性連接結構170中的每一者的材料並非僅限於此。電性連接結構170中的每一者可為接腳(land)、球(ball)、引腳(pin)等。電性連接結構170可 被形成為多層式結構或單層結構。當電性連接結構170被形成為多層式結構時，電性連接結構170可包含銅(Cu)柱及焊料。當電性連接結構170被形成為單層結構時，電性連接結構170可包含錫-銀焊料或銅(Cu)。然而，此僅為實例，且電性連接結構170並非僅限於此。
電性連接結構170的數目、間隔、設置形式等無特別限制，而是可由熟習此項技術者端視設計特定細節而充分地進行修改。舉例而言，電性連接結構170可根據連接接墊131P、132P及133P的數目而被設置成數千至數十萬的數量，或者可被設置成數千至數十萬或更多的數量或者數千至數十萬或更少的數量。
圖9是示出半導體封裝的另一實例的示意性剖視圖。
參照圖9，在根據另一示例性實施例的半導體封裝100B中，保護層150可更具有壓痕或開口151，壓痕或開口151形成於保護層150的下表面中且暴露出凸塊下金屬接墊160P的表面以及凸塊下金屬接墊160P的側表面的至少一部分。除其中形成有凸塊下金屬通孔160V的開口以外，亦形成開口151，且凸塊下金屬接墊160P的側表面的至少一部分可經由開口151被暴露出，以使得凸塊下金屬接墊160P與電性連接結構170之間的連接可靠性可得到提高。亦即，凸塊下金屬接墊160P的至少一部分可嵌置於保護層150中。保護層150的下表面可設置於與凸塊下金屬接墊160P的下表面的水平高度實質上相同的水平高度上。原因在於凸塊下金屬接墊160P被形成為暴露至保護層150的表面且接著經受研磨 製程等。開口151然後形成於保護層150中以暴露出凸塊下金屬接墊160P的側表面的至少一部分。用語「相同的水平高度」意味著各表面彼此共面，且忽略端視製程的輕微撓曲等。
凸塊下金屬層160可包括凸塊下金屬接墊160P及凸塊下金屬通孔160V，凸塊下金屬接墊160P嵌置於保護層150中以使得凸塊下金屬接墊160P的側表面的一部分被暴露出，凸塊下金屬通孔160V穿透保護層150的至少一部分且將中介層110的被暴露出的配線層112與凸塊下金屬接墊160P電性連接至彼此。凸塊下金屬接墊160P可具有在保護層150的開口151中突出的突出部分。突出部分的側表面可與開口151的側壁間隔開。電性連接結構170可覆蓋凸塊下金屬接墊160P的被暴露出的表面及側表面。在另一示例性實施例中，凸塊下金屬層160的凸塊下金屬接墊160P可具有非圓形形狀，例如，如上所述平面中的齒輪形狀。亦即，區A的說明與上述說明重疊。
凸塊下金屬通孔160V的與中介層110的被暴露出的配線層112接觸的上表面的寬度可大於凸塊下金屬通孔160V的與凸塊下金屬接墊160P接觸的下表面的寬度。此處，寬度是相對於剖視圖(例如圖9所示剖視圖)來決定。在其中使用以上相對於圖6闡述的凸塊下金屬層的情形中，凸塊下金屬通孔的上表面的寬度大體小於凸塊下金屬通孔的下表面的寬度。另一方面，在根據另一示例性實施例的半導體封裝100B中，使用先凸塊下金屬層方法(UBM layer first method)，且因此凸塊下金屬通孔160V可被形 成為其中凸塊下金屬通孔160V的上表面的寬度大於凸塊下金屬通孔160V的下表面的寬度的倒梯形形狀。另外，凸塊下金屬通孔160V可為近似填充通孔。其他配置的說明與上述重疊，且因此被省略。
如上所述，根據本揭露中的示例性實施例，可提供一種可確保電性連接結構的高可靠性的半導體封裝。
儘管以上已示出並闡述了各示例性實施例，然而對於熟習此項技術者而言將顯而易見的是，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出修改及變型。

Claims (19)

  1. 一種半導體封裝，包括：有機中介層，包括絕緣層及設置於所述絕緣層上的配線層；半導體晶片，設置於所述有機中介層的一個表面上且具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊；包封體，設置於所述有機中介層上且包封所述半導體晶片的至少一部分；保護層，設置於所述有機中介層的與所述有機中介層的上面設置有所述半導體晶片的所述一個表面相對的另一表面上，且所述保護層具有開口，所述開口延伸至所述配線層的至少一部分；以及凸塊下金屬(UBM)層，包括凸塊下金屬接墊及凸塊下金屬通孔，所述凸塊下金屬接墊設置於所述保護層上，所述凸塊下金屬通孔設置於所述開口中且將所述凸塊下金屬接墊與所述配線層連接至彼此，其中至少一個凹槽部分設置於所述凸塊下金屬接墊的外圓周表面中。
  2. 如申請專利範圍第1項所述的半導體封裝，其中自所述凸塊下金屬接墊的中心至其中未設置有所述凸塊下金屬接墊的所述凹槽部分的區的外圓周表面的距離大於自所述凸塊下金屬接墊的所述中心至其中設置有所述凸塊下金屬接墊的所述凹槽部分的區的外圓周表面的距離。
  3. 如申請專利範圍第2項所述的半導體封裝，更包括電性連接結構，所述電性連接結構設置於所述保護層上且連接至所述凸塊下金屬接墊，其中所述凹槽部分被所述電性連接結構填充。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述凸塊下金屬接墊的至少一部分突出於所述保護層的下表面下方。
  5. 如申請專利範圍第4項所述的半導體封裝，其中與所述配線層接觸的所述凸塊下金屬通孔的上表面的寬度小於與所述凸塊下金屬接墊接觸的所述凸塊下金屬通孔的下表面的寬度。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述凸塊下金屬接墊的至少一部分嵌置於所述保護層中。
  7. 如申請專利範圍第6項所述的半導體封裝，其中與所述配線層接觸的所述凸塊下金屬通孔的上表面的寬度大於與所述凸塊下金屬接墊接觸的所述凸塊下金屬通孔的下表面的寬度。
  8. 如申請專利範圍第1項所述的半導體封裝，其中在所述半導體晶片的所述連接接墊上更設置有導電凸塊。
  9. 如申請專利範圍第8項所述的半導體封裝，其中所述導電凸塊包含低熔點金屬。
  10. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶片包括圖形處理單元(GPU)及設置於所述圖形處理單元附近的多個高頻寬記憶體(HBM)，且所述圖形處理單元與所述高頻寬記憶體藉由所述配線層電性連接至彼此。
  11. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶片的所述非主動表面自所述包封體暴露出。
  12. 一種半導體封裝，包括：半導體晶片，具有主動表面及與所述主動表面相對的非主動表面，所述主動表面上設置有連接接墊；包封體，包封所述半導體晶片的至少一部分；連接構件，設置於所述半導體晶片的所述主動表面上且包括電性連接至所述連接接墊的配線層；保護層，設置於所述連接構件上且具有開口，所述開口延伸至所述配線層的至少一部分；以及凸塊下金屬層，包括凸塊下金屬接墊及凸塊下金屬通孔，所述凸塊下金屬接墊設置於所述保護層上，所述凸塊下金屬通孔設置於所述開口中且將所述凸塊下金屬接墊與被暴露出的所述配線層連接至彼此，其中當自與所述保護層的表面垂直的方向觀察所述凸塊下金屬接墊時，所述凸塊下金屬接墊的邊界包括至少一凹形部分。
  13. 如申請專利範圍第12項所述的半導體封裝，其中當自與所述保護層的所述表面垂直的所述方向觀察時，所述凸塊下金屬接墊具有包括多個突出部的形狀，所述多個突出部彼此間隔開且自所述凸塊下金屬接墊的中心部分延伸。
  14. 如申請專利範圍第12項所述的半導體封裝，其中所述保護層的表面在所述凸塊下金屬接墊的所述邊界的所述至少一凹形部分中被暴露出。
  15. 如申請專利範圍第14項所述的半導體封裝，更包括導電凸塊，所述導電凸塊設置於所述半導體晶片的所述凸塊下金屬接墊上且在所述凸塊下金屬接墊的所述邊界的所述至少一凹形部分中延伸。
  16. 一種中介層，所述中介層被配置成在所述中介層的上表面上安裝有半導體晶片，所述中介層包括：絕緣材料，形成所述中介層的主體；多個配線層，設置於所述主體的所述絕緣材料中，且設置於所述中介層的所述上表面上以連接至所述半導體晶片的第一連接接墊；多個通孔，穿透所述主體的所述絕緣材料以對所述多個配線層中的相鄰的配線層進行內連；保護層，設置於所述中介層的與所述上表面相對的下表面上且具有多個開口，所述多個開口各自延伸至所述配線層；以及至少一第二連接接墊，設置於所述保護層的下表面上，且經由連接通孔連接至所述配線層，所述連接通孔延伸穿過所述多個開口中的開口，其中所述保護層的所述下表面上的被所述至少一第二連接接墊佔據的區域的輪廓包括至少一凹形部分。
  17. 如申請專利範圍第16項所述的中介層，其中當自與所述保護層的所述下表面垂直的方向觀察時，被所述至少一第二連接接墊佔據的所述區域具有包括多個突出部的形狀，所述多個突出部被所述至少一凹形部分彼此間隔開。
  18. 如申請專利範圍第16項所述的中介層，其中所述保護層的所述下表面在所述第二連接接墊的邊界的所述至少一凹形部分中被暴露出。
  19. 如申請專利範圍第16項所述的中介層，其中所述保護層的所述下表面上的被所述至少一個連接接墊佔據的所述區域包括沿所述區域的外周邊設置的多個均勻間隔開的凹形部分。
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