TWI651776B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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Publication number
TWI651776B
TWI651776B TW106114167A TW106114167A TWI651776B TW I651776 B TWI651776 B TW I651776B TW 106114167 A TW106114167 A TW 106114167A TW 106114167 A TW106114167 A TW 106114167A TW I651776 B TWI651776 B TW I651776B
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Taiwan
Prior art keywords
wafer
small
substrate
recessed portion
chiplet
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TW106114167A
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English (en)
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TW201807753A (zh
Inventor
邵棟樑
志航 董
余振華
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台灣積體電路製造股份有限公司
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Abstract

半導體封裝及其形成方法。實施例包括在第一基板中形成第一凹陷部，其中所述第一凹陷部的開口的第一面積大於所述第一凹陷部的底部的第二面積。所述實施例亦包括形成第一元件，其中所述第一元件的頂端的第三面積大於所述第一元件的底端的第四面積。實施例亦包括：將所述第一元件放置至所述第一凹陷部中，其中所述第一元件的所述底端面對所述第一凹陷部的所述底部；以及將所述第一元件的側壁接合至所述第一凹陷部的側壁。

Description

半導體封裝及其形成方法
本發明實施例是關於一種半導體封裝及其形成方法。
由於積體電路（IC）的發明，半導體行業已因各種電子元件（亦即電晶體、二極體、電阻器、電容器等）整合密度之不斷提升而經歷快速成長。最重要的是，整合密度的提升乃是源自最小特徵尺寸之不斷減小，而使得更多的元件能夠整合至給定面積之中。
此種整合度提升實質上是從二維（two-dimensional，2D）層面而言，肇因於積體元件所佔據的體積主要位於半導體晶圓的表面上。儘管微影的明顯改良導致在二維積體電路形成方面的顯著改良，然而對於可在二維中達成的密度仍有其物理限制。該些限制之一是製造該些元件所需的最小尺寸。另外，當將更多元件置入一個晶片或晶粒中時，需要更複雜的設計。
在對進一步增大電路密度進行的嘗試中，已探討了三維積體電路（three-dimensional integrated circuits，3DICs）。在三維積體電路的典型形成製程中，將兩個晶片接合在一起且在在每一晶片與基板上接觸墊之間形成電性連接。舉例而言，可藉由將一個晶片貼合於另一晶片頂上來完成兩個晶片的接合。接著將堆疊的晶片接合至載體基板且導線（wire bonds）將每一晶片上的接觸墊電性耦合至載體基板上的接觸墊。然而，此種方是需要較晶片大的載體基板以進行打線接合（wire bonding）。目前嘗試集中於倒裝晶片互連（flip-chip interconnections）以及使用導電球/凸塊在晶片與下方基板之間形成連接，而能夠在相對小的封裝中達成高配線密度。使用焊點結合的傳統晶片堆疊涉及到焊料、助溶劑（flux）及底部填充物。這些製程在間距、結合高度及助溶劑殘渣方面均存在不少問題及限制。
本發明實施例提供一種形成半導體封裝的方法。所述方法包括：在第一基板中形成第一凹陷部，其中所述第一凹陷部的開口的第一面積大於所述第一凹陷部的底部的第二面積；以及形成第一元件，其中所述第一元件的頂端的第三面積大於所述第一元件的底端的第四面積。所述方法亦包括將所述第一元件放置於所述第一凹陷部中，其中所述第一元件的所述底端面對所述第一凹陷部的所述底部；以及將所述第一元件的側壁接合至所述第一凹陷部的側壁。
本發明實施例提供一種形成半導體封裝的方法。所述方法包括：將元件至少局部地插入至在基板的頂表面中形成的凹陷部中，其中所述元件具有錐形輪廓，且其中所述插入使得所述元件沿側向且朝向所述基板的底表面移動。
本發明實施例提供一種半導體元件。所述元件包括：基板，包括位於所述基板的頂表面中的多個凹陷部；以及多個小晶片，分別安置於所述多個凹陷部中，其中所述多個小晶片接合至所述基板。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在…之下（beneath）」、「下面的（below）」、「下部的（lower）」、「上方的（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個組件或特徵與另一（其他）組件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。所述裝置可具有其他定向（旋轉90度或處於其他定向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
圖1A及圖1B說明根據某些實施例的形成積體小晶片結構100的態樣。圖1A顯示示例性小晶片102及示例性基板104。圖1B顯示在已將小晶片102放置至基板104中的凹陷部108中之後的小晶片102。在某些實施例中，小晶片102可為晶片、積體電路晶粒、半導體元件、記憶體晶片、互連線結構、其他類型元件等。小晶片102可包含或可由下列半導體材料所形成:例如Si、SiC、Ge、III-V族半導體材料、II-VI族半導體材料、其他半導體材料、絕緣體上半導體（semiconductor-on-insulator，SOI）材料等半導體材料。在某些實施例中，小晶片102是由一或多種介電材料所形成，例如SiO2 、SiN、聚合物或其他介電材料等。可使用此技術中習知的任意適合的方法或製造技術來形成小晶片102。以下會針對圖6A至圖6D及圖7A至圖7D來闡述形成小晶片102的某些實施例。
在某些實施例中，在小晶片102的頂表面上可選擇安置小晶片金屬化層106。小晶片金屬化層106可形成於小晶片102的主動元件與被動元件之上且可對各種元件進行連接以形成積體電路或積體電路的一部分。小晶片金屬化層106可對在小晶片102上形成的元件進行互連，且亦可提供自小晶片102至外部元件或結構的外部連接。小晶片金屬化層106可由介電材料與導電材料的交替層所形成，其具有對導電材料的各層進行互連的介層窗。可藉由任意適合的製程（例如沈積、鑲嵌、雙重鑲嵌等）來形成小晶片金屬化層106。在某些情形中，可在後端製造製程（back-end-of-line，BEOL）階段中形成小晶片金屬化層106。在某些實施例中，小晶片金屬化層106包括重佈線層（redistribution layer，RDL）。
在某些實施例中，小晶片102可具有介於約1平方微米至約10000平方微米的平面面積，例如約100平方微米。舉例而言，小晶片102可具有為約10微米´10微米的平面尺寸或其他尺寸。在某些實施例中，小晶片102具有小於1平方微米或大於10000平方微米的平面面積。小晶片102可在平面圖中具有正方形形狀、在平面圖中具有矩形形狀或在平面圖中具有其他種形狀。在某些實施例中，小晶片102具有介於約1微米至約500微米的厚度，例如，約2微米、10微米、50微米或另一厚度。在某些實施例中，小晶片102具有小於1微米或大於500微米的厚度。
在某些實施例中，基板104是由玻璃、矽（例如矽晶圓）或其他種半導體材料、氧化矽或其他介電材料製成的晶圓、絕緣體上矽（SOI）晶圓等。在某些實施例中，基板104由金屬、陶瓷材料、塑膠或其他聚合物材料、其組合等製成。在某些實施例中，基板104是元件晶圓、中介板（interposer）、晶粒或積體電路，且可包括主動元件或被動元件、金屬化層、保護層、介層窗或其組合等。在某些實施例中，基板104是載體、空白載體晶圓、舟皿（boat）、框架、封裝等。
基板104包括凹陷部108，其形成為可接納小晶片102形狀。在某些實施例中，凹陷部108形成於安置於基板104的表面上的一或多個介電層中。圖1B顯示放置於凹陷部108中的小晶片102。儘管在其他實施例中，小晶片102的頂表面可位於基板104的頂表面上方或位於基板104的頂表面下面，然而在某些實施例中，當將小晶片102放置於凹陷部108中時，小晶片102的頂表面與基板104的頂表面實質上齊平（如圖1B所示）。在某些實施例中，小晶片金屬化層106的頂表面可與基板104的頂表面實質上齊平。在某些實施例中，凹陷部108的深度大於小晶片102的厚度，進而使得在小晶片102的底表面與凹陷部108的底表面之間存在間隙114。如此一來，可降低因小晶片102的厚度變化或凹陷部108的深度變化帶來的影響。
在放置於凹陷部108內之後，可將小晶片102接合至基板104。在某些實施例中，使用直接接合製程(direct bonding process)將小晶片102接合至基板104。舉例而言，小晶片基板接合製程可形成Si-Si接合、SiO-SiO接合、Si-SiO接合或其他類型的直接接合/鍵結。在某些實施例中，在小晶片102與基板104之間使用中間層來進行小晶片-基板接合。所述中間層可為黏合層、環氧樹脂（epoxy）、樹脂、聚合物或其他類型的接合材料。小晶片-基板接合製程可包括例如表面製備步驟、一或多次退火、浸水或此領域中習知的其他技術。
在某些實施例中，小晶片102的側壁110及凹陷部108的對應側壁112可具有相似的形狀或具有相似的輪廓。多於一個小晶片側壁110及多於一個凹陷部側壁112可具有對應的形狀或輪廓。如此一來，小晶片側壁110與凹陷部側壁112的面積中的某些或全部可在實體上進行接觸。舉例而言，在圖1A所示說明性實施例中，小晶片側壁110為平面的且具有角度θ ，且凹陷部側壁112亦為具有角度θ 的平面。因此，如圖1B所示，當將小晶片102放置於凹陷部108中時，呈相似角度的側壁使得小晶片側壁110的某些部分能夠平行於並在實體上接觸凹陷部側壁112的某些部分。具有呈相似形狀的側壁可使得小晶片102與基板104之間存在更大接觸表面積，此可改良小晶片102與基板104之間的接合。此外，如下所詳細地闡述，具有相似的側壁亦可使得小晶片102於凹陷部108內能夠達成更佳的對準。
在某些實施例中，小晶片的側壁或凹陷部的側壁可能不如圖1A至圖1B所示為平直的或為平面。在其他實施例中，所述側壁中的某些或全部可為彎曲的，側壁的不同部分可具有不同的角度，或者所述側壁可具有不規則的形狀。小晶片或凹陷部可具有側壁角度實質上恆定的一或多個側壁。舉例而言，側壁角度可在正常的製程變化以內為恆定的。小晶片可具有不實質上垂直於小晶片的頂表面或底表面的一或多個側壁。凹陷部可具有不實質上垂直於基板的頂表面或凹陷部的底表面的一或多個側壁。在某些情形中，小晶片的各側壁或凹陷部的各側壁是對稱的。在某些情形中，小晶片的不同的側壁可具有不同的形狀且凹陷部的不同的側壁可具有不同的形狀。
在某些情形中，本文所述小晶片側壁110及凹陷部側壁112可提供增大的放置未對準容差(placement misalignement allowance)且亦可容許放置時達成小晶片102的自對準(self-alignment)。舉例而言，在圖1A中，小晶片側壁110朝小晶片102的底部向內成角度且圖1A所示凹陷部側壁112朝凹陷部的底部向內成角度。在放置小晶片102期間，若小晶片102不與凹陷部108對準或不位於凹陷部108的中心（在圖1A中顯示其未對準為d ），則在小晶片102向下移動至凹陷部108中時，小晶片側壁110將撞擊於凹陷部側壁112上並貼靠凹陷部側壁112滑動。小晶片側壁110與凹陷部側壁112的相似的角度會使得在小晶片102向下移動至凹陷部108中時小晶片102朝居中位置側向位移。小晶片102可向下移動至凹陷部108中直至因兩次或多次撞擊側壁而阻止進一步側向移動或向下移動為止，或者直至小晶片102的底部撞擊於凹陷部108的底部上為止。如此一來，小晶片102可在放置時自行對準，且在放置之後，其初始放置未對準d 可減小至零或近乎於零。在某些情形中，在放置之後，小晶片102的頂表面可與基板104的頂表面實質上齊平，而在某些情形中，在放置之後，小晶片102的頂表面可位於基板104的頂表面上方或位於基板104的頂表面下面。
此種自對準行為可在放置時能夠達成增大的未對準容差。在某些情形中，若至少小晶片側壁110的底部位於凹陷部側壁112的至少頂部之上，則小晶片102可自行對準。因此，既然具有側向未對準容差，則小晶片102在放置時可在所述側向未對準容差內自對準。其他小晶片、凹陷部及實施例的未對準容差端視例如以下因素而定：小晶片側壁及凹陷部側壁的角度或形狀；小晶片的厚度及尺寸；及凹陷部的深度及尺寸。儘管在其他情形中，未對準容差可小於約700微米或大於約700微米，然而在某些情形中，未對準容差可為約700微米。未對準容差越大能夠使小晶片越快地被放置，乃因放置工具可能並不需要過多時間來使小晶片精確地對準對應的凹陷部。此外，本文所述小晶片的自對準行為可使小晶片在放置之後具有近乎於零的未對準，儘管放置期間具有相當大的未對準容差。
圖2A至圖2C說明根據某些實施例的積體小晶片晶圓200的態樣。積體小晶片晶圓200包括整合至單個晶圓206中的多個小晶片202a-202c。圖2A至圖2C已表示出小晶片202a-202c中的某些小晶片，當然亦可將較所示出者更多或更少的小晶片整合至晶圓206中。晶圓206可為半導體晶圓（例如矽晶圓）或不同類型的晶圓或基板（例如以上針對圖1A至圖1B中的基板104所述者）。各別小晶片202a-202c可為相同的元件或不同的元件或者可為先前所述不同類型的小晶片（例如，圖1A至圖1B所示小晶片102）。舉例而言，某些小晶片202a-202c可為與其他小晶片202a-202c不同的積體晶粒。小晶片202a-202c亦可由不同的材料形成。舉例而言，在單個晶圓206上，一個小晶片202a可由矽形成，另一小晶片202b可由GaAs形成，且第三小晶片202c可由GaN形成。小晶片202a-202c的其他材料及組合亦是可能的。此外，可使用不同的處理技術來形成小晶片202a-202c，且小晶片202a-202c可具有不同的尺寸、形狀、厚度等。如此一來，異質小晶片可整合在單個晶圓或基板上。
在某些實施例中，在將小晶片放置至小晶片的凹陷部之前先對每一小晶片進行測試。在對小晶片進行測試之後，可僅選擇合格的小晶片用於積體小晶片晶圓中。如此一來，積體小晶片晶圓可具有高的晶粒合格率（Known Good Die，KGD）。小晶片測試可因此提高例如以下圖3A至圖3C所闡述的封裝等包含有積體小晶片晶粒的元件的總體良率。
圖2A至圖2C說明包括形成於小晶片202a-202c及晶圓206之上的可選重佈線層208的積體小晶片晶圓200。重佈線層208可包括與小晶片202a-202c及晶圓206接觸的接點以及小晶片202a-202c與晶圓206之間的互連，如圖2C更詳細所示。在某些實施例中，可在後端製造製程階段中形成重佈線層208。如此一來，可使用單個重佈線層形成製程來對包括先前所述不同類型的小晶片在內的多個小晶片進行互連。在某些實施例中。某些小晶片202a-202c包括例如以上在圖1A至圖1B中所述的小晶片金屬化層106等小晶片金屬化層。重佈線層208可安置於小晶片金屬化層之上並連接至小晶片金屬化層。在某些情形中，在小晶片上使用小晶片金屬化層可減少原本所需的上覆重佈線層的層數。
在某些實施例中，積體小晶片晶圓200包括多個積體小晶片晶粒。在圖2A中的剖視圖及圖2B中的平面圖中顯示示例性積體小晶片晶粒204。積體小晶片晶粒中的每一者可自積體小晶片晶圓200單體化，如圖2B所示。積體小晶片晶粒可包括以不同的排列位於相鄰位置的多個不同的小晶片。
圖3A至圖3C說明根據某些實施例的經封裝的積體小晶片晶粒的態樣。圖3A說明使用積體小晶片晶粒204的示例性積體扇出型（Integrated Fan-Out，InFO）結構300。積體小晶片晶粒204可包括一或多個小晶片（例如，圖1A至圖1B所示小晶片102）。在示例性積體扇出型結構300中，晶粒204的重佈線層208接合至或以其他方式連接至積體扇出型結構300的封裝重佈線層302。晶粒重佈線層208與封裝重佈線層302可在積體扇出型結構300內在小晶片與其他元件之間進行電性連接並形成互連。封裝重佈線層302連接至外部連接件304。晶粒204的寬度小於積體扇出型結構300的寬度，且晶粒204被包封體306環繞。
圖3B說明使用積體小晶片晶粒204的示例性積體扇入型（Integrated Fan-In，InFI）結構310。在示例性積體扇入型結構310中，積體小晶片晶粒204的重佈線層208接合至或以其他方式連接至積體扇入型結構310的封裝重佈線層312。晶粒重佈線層208與封裝重佈線層312可在積體扇入型結構310內在小晶片與其他元件之間進行電性連接並形成互連。封裝重佈線層312連接至外部連接件314。晶粒204的寬度相同於或大於積體扇入型結構310的寬度。
圖3C說明使用積體小晶片晶粒204的示例性倒裝晶片晶片規模封裝（Flip-Chip Chip-Scale Package，FCCSP）結構320。在示例性倒裝晶片晶片規模封裝結構320中，積體小晶片晶粒204的重佈線層208接合至或以其他方式連接至倒裝晶片晶片規模封裝結構320的封裝重佈線層322。晶粒重佈線層208與封裝重佈線層322可在倒裝晶片晶片規模封裝結構320內在小晶片與其他元件之間進行電性連接並形成互連。封裝重佈線層322連接至外部連接件324。
圖3A至圖3C繪示某些示例性積體小晶片封裝，但亦可為包含積體小晶片晶粒的其他類型的封裝。在某些實施例中，積體小晶片晶粒可在不使用基板穿孔（through-substrate-via，TSV）或中介板的情況下用於積體扇出型、積體扇入型、倒裝晶片晶片規模封裝(FCCSP)、基板上晶圓上晶片（Chip-on-Wafer-on-Substrate，CoWoS）或其他類型的封裝中。在某些實施例中，使用在積體小晶片晶粒上形成的重佈線層可降低封裝重佈線層所需的複雜性或減少封裝重佈線層所需的層的數目。此外，使用標準後端製程在積體小晶片晶粒上形成重佈線層可降低形成積體小晶片封裝所需的總體複雜性或減少形成積體小晶片封裝所需的製程步驟的數目。
圖4A至圖4D說明根據某些實施例的晶圓-晶圓接合製程中的中間步驟。圖4A說明第一積體小晶片晶圓400及第二積體小晶片晶圓402的示例性剖視圖，且圖4C說明第一晶圓400及第二晶圓402的平面圖。第一積體小晶片晶圓400包括多個第一積體小晶片晶粒404、且第二積體小晶片晶圓402包括多個第二積體小晶片晶粒406。積體小晶片晶粒404、積體小晶片晶粒406中的每一者可包括一或多個小晶片（例如，圖1A至圖1B所示小晶片102）。圖4B說明將第一晶圓400接合至第二晶圓402以形成堆疊式晶圓結構450的示例性剖視圖，且圖4D說明對第一晶圓400與第二晶圓402進行接合以形成堆疊式晶圓結構450的平面圖。可使用直接接合、介電接合(dielectric bonding)、金屬接合(metal bonding)、混合接合(hybrid bonding)或其他接合技術將第一晶圓400接合至第二晶圓402。第一晶圓400與第二晶圓402可被接合成使得帶有小晶片的表面面對彼此（「面對面（face-to-face）」）。此外，可將每一晶圓400、晶圓402上的重佈線層接合在一起以在兩個晶圓上的重佈線層與小晶片之間形成互連。舉例而言，可使晶圓400、晶圓402對準，進而使得重佈線層上的接觸墊在接合之後電性連接。在某些情形中，在晶圓400、晶圓402之間可安置有中間互連線層、基板或中介板。在其他實施例中，可將積體小晶片晶圓接合至不同類型的晶圓或基板。
晶圓400、晶圓402可被接合成使得第一晶粒404對準第二晶粒406以在堆疊式晶圓結構450中形成堆疊式晶粒408。在接合之後，可將堆疊式晶粒408自堆疊式晶圓結構450單體化。在某些實施例中，在將小晶片放置於晶圓400、晶圓402上之前對小晶片進行測試。藉由僅使用已知合格小晶片，積體小晶片晶粒為合格的可能性可得到極大提高。如此一來，第一晶圓400可含有高晶粒合格率的第一晶粒404，且第二晶圓402可含有高晶粒合格率的第二晶粒406。此可使得堆疊式晶圓結構450含有高晶粒合格率的堆疊式晶粒408。在某些情形中，亦可在接合之前對晶粒404、晶粒406進行測試。在某些情形中，晶圓400、晶圓402及堆疊式晶圓結構450的晶粒合格率可為100%或近乎100%。在某些情形中，第一晶粒404具有與第二晶粒408大約相同的面積，且因此可減少或消除因晶粒面積失配而導致的面積懲罰（area penalty）。
圖5A至圖5C說明根據實施例的其它堆疊式積體小晶片晶圓配置的態樣。積體小晶片晶圓中的每一者可包括一或多個小晶片（例如圖1A至圖1B所示小晶片102）或積體小晶片晶粒（例如圖2A至圖2C所示積體小晶片晶粒204）。舉例而言，在圖5A中，積體小晶片晶圓500面對面接合至積體小晶片晶圓502，且積體小晶片晶圓504面朝下接合至晶圓502。此形成第一三層堆疊式晶圓506。在圖5B中，積體小晶片晶圓510面對面接合至積體小晶片晶圓512，且積體小晶片晶圓514面朝上接合至晶圓512。此形成第二三層堆疊式晶圓516。在圖5C中，積體小晶片晶圓520面對面接合至積體小晶片晶圓522以形成第一堆疊式晶圓530，且積體小晶片晶圓524面對面接合至積體小晶片晶圓526以形成第二堆疊式晶圓532。第一堆疊式晶圓530接合至第二堆疊式晶圓532以形成四層堆疊式晶圓534。在其他實施例中，一或多個積體小晶片晶圓可接合至一或多種不同類型的晶圓，並接合至較圖5A至圖5C所示更多或更少的晶圓。可使用直接接合、介電接合、金屬接合、混合接合或其他接合技術來對晶圓進行接合。在某些情形中，可使用貫穿晶圓的一或多個基板穿孔（TSV）來形成對小晶片、重佈線層或其他結構的內部連接或外部連接。對於形成包括至少一個積體小晶片晶圓的堆疊式晶圓而言，亦可存在其他組合、配置、連接或接合程序。在某些情形中，積體小晶片晶圓中的某些或全部可具有具有相同面積的積體小晶片晶粒。
圖6A至圖6D說明根據實施例形成小晶片614的中間步驟。各別小晶片614可為相同的元件或不同的元件或者可為先前所述不同類型的小晶片（例如圖1A至圖1B所示小晶片102）。圖6A顯示示例性基板604及小晶片區602。小晶片區602表示基板604中的將形成小晶片614的位置。示例性基板604可為半導體基板（例如，矽基板、絕緣體上矽基板、GaAs基板或其他種半導體基板）或者可為先前所述其他種類型的基板材料。已對基板604進行了處理，進而使得小晶片區602含有電路、電晶體、電阻器、其他被動元件及主動元件等。舉例而言，可使用此項技術中習知的製造技術在每一小晶片區602中形成積體電路。在某些實施例中，在基板604之上形成小晶片金屬化層。
圖6B顯示在基板604的表面之上形成支撐層610之後的基板604。支撐層610可為SiN、氧化物、其他介電材料、聚合物或其他種材料。基板604的底部亦可如圖6B所示被薄化。舉例而言，可藉由蝕刻製程及/或例如機械研磨製程或化學機械拋光（chemical mechanical polishing，CMP）製程等平坦化製程來達成基板604的薄化。基板604可被薄化至大約小晶片區602的底表面，如圖6B所示。在某些實施例中，則不執行薄化製程或以與所示者不同的步驟來執行所述薄化製程。
圖6C顯示在其底表面上安置有罩幕612的基板604。已將罩幕612圖案化以在後續蝕刻步驟期間保護小晶片區602。罩幕612可為例如光阻或硬罩幕且可使用任意適合的光微影技術來將罩幕612圖案化。
在將罩幕612圖案化之後，對基板604的犧牲部分（sacrificial portion）進行蝕刻以隔離小晶片區602。在圖6C中標記出各小晶片區602之間的示例性犧牲部分616。在對基板604的犧牲部分進行蝕刻之後，經隔離的小晶片614依舊貼合至支撐層610。在已隔離出小晶片614之後將罩幕612移除。圖6D顯示貼合至支撐層610的經隔離的小晶片614。
可使用任意適合的濕式蝕刻技術或乾式蝕刻技術來移除基板604的犧牲部分。舉例而言，在其中基板604是具有定向（100）的矽的實施例中，可使用例如氫氧化鉀（KOH）、乙二胺鄰苯二酚（ethylenediamine pyrocatechol，EDP）、四甲基氫氧化胺（Tetramethy1ammoniumhydroxide，TMAH）或其他蝕刻劑等各向異性蝕刻劑。在此實例中，各向異性蝕刻劑可使得每一小晶片614對應於矽定向（111）而具有實質上平坦的側壁。小晶片614的側壁對應於矽定向（111）而具有為約54.74°的角度。可使用適合使用各向異性蝕刻劑的其他基板，例如GaAs基板、GaN基板或其他基板。使用各向異性蝕刻劑能夠確保對側壁角度及平坦度之重製性。然而，在其他實施例中，可使用各向同性蝕刻（isotropic etching）、乾式蝕刻或蝕刻技術的組合來隔離開小晶片並對小晶片側壁進行造形，所述對小晶片側壁進行造形包括形成具有其他角度的小晶片側壁。
圖7A至圖7E說明根據實施例形成小晶片714的中間步驟。獨立小晶片714可為相同的元件或不同的元件或者可為先前所述不同類型的小晶片（例如圖1A至圖1B所示小晶片102）。圖7A顯示示例性基板704及小晶片區702。小晶片區702表示基板704中的將形成小晶片714的位置。示例性基板704可為半導體基板或者可為先前所述另一種類型的基板材料。已對基板704進行了處理以形成先前所述小晶片區702。
圖7B說明在小晶片區702之上形成可選小晶片金屬化層706。在某些實施例中，在基板704之上形成小晶片金屬化層706且接著移除各小晶片區702之間的小晶片金屬化層706的部分。可藉由此項技術中習知的光微影圖案化及蝕刻來移除小晶片金屬化層706的所述部分。在其他實施例中，不使用小晶片金屬化層706。
圖7C說明在小晶片金屬化層706處將載體710黏貼至基板704。在某些情形中，載體710可藉由黏合劑進行黏貼或載體710本身可為黏合性材料。載體710可為玻璃載體、陶瓷載體、晶圓、框架、板、基板等。載體710亦可為膠帶、膜（例如晶粒貼合膜（die-attach film）或其他膜）、聚合物等。載體710可為剛性或撓性的載體。
基板704的底部亦可如圖7C所示被薄化。舉例而言，可藉由蝕刻製程及/或例如機械研磨製程或化學機械拋光（CMP）製程等平坦化製程來達成基板704的薄化。基板704可被薄化至小晶片區702的底表面附近，如圖7C所示。在某些實施例中，則不執行薄化製程或以與所示者不同的步驟來執行所述薄化製程。
圖7D顯示在其底表面上安置有罩幕712的基板704。已將罩幕712圖案化以在後續蝕刻步驟期間保護小晶片區702。罩幕712可為例如光阻或硬罩幕且可使用任意適合的光微影技術來將罩幕712圖案化。
在將罩幕712圖案化之後，對基板704的犧牲部分進行蝕刻以隔離小晶片區702。在圖7D中標記出各小晶片區702之間的示例性犧牲部分716。在對基板704的犧牲部分進行蝕刻之後，經隔離的小晶片714依舊貼合至載體710。在已隔離出小晶片714之後將罩幕712移除。圖7E顯示貼合至載體710的經隔離的小晶片714。
與以上針對圖6A至圖6D闡述的實施例相似，可使用任意適合的濕式蝕刻技術或乾式蝕刻技術來移除基板704的犧牲部分。在某些實施例中，可使用各向異性蝕刻來隔離小晶片714。作為說明性實例，圖7E顯示小晶片714的側壁在各向異性蝕刻之後對應於矽定向（111）而具有為約54.74°的角度。然而，在其他實施例中，可使用各向同性蝕刻、乾式蝕刻或蝕刻技術的組合來隔離小晶片並對小晶片側壁進行造形。
圖8A至圖8C說明根據實施例形成基板802中的凹陷部808的中間步驟。各別凹陷部808可與本文中先前所述凹陷部（例如，圖1A至圖1B所示凹陷部108）相似。圖8A顯示示例性基板802及凹陷部區804。凹陷部區804表示基板802內的將形成凹陷部808的位置。示例性基板802可為半導體基板或者可為先前所述另一種類型的基板材料。
圖8B顯示在其頂表面上安置有罩幕806的基板802。已將罩幕806圖案化以在後續蝕刻步驟期間保護基板802的靠近凹陷部區804的部分。罩幕806可為例如光阻或硬罩幕且可使用任意適合的光微影技術來將罩幕806圖案化。
圖8C說明已對凹陷部區804進行蝕刻形成凹陷部808的基板802。可使用任意適合的濕式蝕刻技術或乾式蝕刻技術（包括與上述小晶片隔離蝕刻相似的蝕刻技術）來移除凹陷部區804。在某些實施例中，可使用各向異性蝕刻來隔離凹陷部區804。舉例而言，可使用氫氧化鉀或另一種各向異性蝕刻劑在矽基板中蝕刻凹陷部區804。舉例而言，圖8C顯示凹陷部808的側壁在各向異性蝕刻之後對應於矽定向（111）而具有為約54.74°的角度。然而，在其他實施例中，可使用各向同性蝕刻、乾式蝕刻或蝕刻技術的組合來形成凹陷部並對凹陷部側壁進行造形。
在某些情形中，可藉由相似的各向異性蝕刻來形成小晶片及對應的凹陷部，且因此小晶片及對應的凹陷部具有平坦的側壁及相同的側壁角度。舉例而言，小晶片及基板兩者均可為矽且均可使用相似的各向異性蝕刻劑來進行蝕刻，進而使得小晶片與凹陷部兩者均可具有為約54.74°的側壁角度。使用相似的技術形成小晶片側壁及凹陷部側壁可使得能夠達成改良的小晶片-自對準及改良的小晶片-基板接合。在其他情形中，可由不同的材料來形成小晶片與基板或使用不同的蝕刻劑或技術來對小晶片與基板進行蝕刻。
圖9A至圖9D說明根據實施例將小晶片902放置至凹陷部906中的中間步驟。小晶片902及凹陷部906可與本文中先前所述的小晶片及凹陷部（例如，圖1A至圖1B所示小晶片102及凹陷部108）相似。圖9A顯示貼合至支撐層910的多個小晶片。在某些實施例中，支撐層910可為與圖6A至圖6D所述的支撐層610相似的層，且在某些實施例中，支撐層910可為不同類型的層、膜或載體。支撐層910被框架912固持，且支撐層910被定位成使得至少一個小晶片近似對準於基板904中的對應的凹陷部上方。舉例而言，小晶片902近似對準於凹陷部906上方。如圖9A所示，工具900向下朝小晶片902移動。工具900可為拾取及放置工具、工具頭等，且可使用真空抽吸來固持小晶片。在某些實施例中，工具900可在小晶片放置期間使用力回饋（force-feedback）。
在圖9B中，工具900已向下移動，以推動小晶片902以使得支撐層910的支撐小晶片902的一部分破碎，從而使小晶片902分離。其他小晶片依舊貼合至支撐層910。在某些情形中，工具900可使用真空來固持小晶片902。小晶片902可在小晶片902及凹陷部906的特定未對準容差以內相對於凹陷部906呈未對準狀態，如圖9B所示。在圖9C中，工具900已將小晶片902移動至凹陷部906中。若小晶片902未對準至凹陷部906，則小晶片902將在小晶片902進入凹陷部906時自對準至凹陷部906。在某種情形中，工具900暫時利用真空來固持小晶片902，且當小晶片902已進入凹陷部906時，釋放真空。
在圖9D中，已完全將小晶片902放置於凹陷部906內。由於自對準，已放置的小晶片902的未對準可約為零。在放置小晶片902之後，工具900可釋放其真空並移動至另一小晶片以重複所述放置步驟。可在後續步驟中藉由蝕刻、研磨、化學機械拋光或其他技術來將支撐層910的保持於小晶片902上的一部分移除。
圖10A至圖10D說明根據實施例將小晶片902放置於凹陷部906中的中間步驟。圖10A顯示貼合至膜1010的多個小晶片。在某些實施例中，膜1010可為與圖7A至圖7E所述的支撐層710相似的膜、膠帶或其他載體，且在某些實施例中，膜1010可為不同類型的膜、膠帶或載體。膜1010被框架1012固持，且膜1010被定位成使得至少一個小晶片近似對準於基板904中的對應的凹陷部上方。舉例而言，小晶片902近似對準於凹陷部906上方。如圖10A所示，工具900朝小晶片902向下移動。
在圖10B中，工具900已向下移動，以推動小晶片902，進而使得膜1010的支撐小晶片902的一部分彎曲或向下延伸。其他小晶片依舊貼合至膜1010。在圖10C中，工具900已將小晶片902移動至凹陷部906中，從而進一步使膜1010彎曲或延伸。若小晶片902未對準至凹陷部906，則小晶片902將在小晶片902進入凹陷部906時自對準至凹陷部906。
在圖10D中，已使小晶片902自膜1010分離且已撤回工具900。在某些情形中，在已撤回工具900之前將小晶片902自膜1010分離，且在其他情形中，在撤回工具900時使小晶片902自膜1010分離。在某些情形中，膜1010的彎曲的部分或延伸的部分朝膜1010的原始位置縮回，如圖10D所示。在某些情形中，工具900將小晶片902的大部分或全部推動至凹陷部906中，且在其他情形中，工具900在將小晶片902的大部分或全部放置於凹陷部906內之前撤回。一旦自膜1010分離，小晶片902便向下移動至凹陷部906中直至小晶片902位於凹陷部906內為止。由於自行對準，所放置的小晶片902的未對準可約為零。在放置小晶片902之後，工具900可移動至另一小晶片以重複放置過程。
圖11A至圖11D說明根據實施例將小晶片902放置至凹陷部906中的中間步驟。圖11A顯示工具900在先前已拾取小晶片902之後藉由真空來固持小晶片902。工具900被定位成使得小晶片902近似對準於凹陷部906上方。如圖11A所示，工具900向下朝小晶片902移動。在圖11B中，工具900已向下移動，從而朝凹陷部906推動小晶片902。在圖11C中，工具900已將小晶片902部分地移動至凹陷部906中。儘管已部分地將小晶片902放置於凹陷部906內，然而工具900可釋放其真空並移動至另一小晶片來重複所述放置製程。若小晶片902未對準至凹陷部906，則小晶片902將在小晶片902進入凹陷部906時自對準至凹陷部906。一旦自工具900釋放，小晶片902便向下移動至凹陷部906中，直至小晶片902位於凹陷部906內為止。在圖11D中，小晶片902已完全地放置於凹陷部906內。由於自對準，已放置的小晶片902的未對準可約為零。
圖12A至圖12C說明根據實施例的積體小晶片製造製程中的中間步驟。圖12A顯示積體小晶片晶圓1200的一部分。積體小晶片晶圓1200可與本文中先前所述積體小晶片晶圓（例如，圖2A至圖2C所示積體小晶片晶圓200）相似。在圖12A中，已將小晶片1202放置於基板1204上其各自相應的凹陷部內。圖12A至圖12C所示各小晶片1202分別具有小晶片金屬化層，且在圖12A中標記出示例性小晶片金屬化層1212。在其他情形中，某些小晶片1202、所有小晶片1202或沒有任何小晶片1202可具有小晶片金屬化層。在可選的步驟中，齊平工具頭1210在小晶片1202上進行按壓以使各小晶片1202齊平並確保將小晶片1202牢牢地放置於各自相應的凹陷部內。在某些情形中，齊平工具頭1210可在小晶片金屬化層上進行按壓，或者若不存在小晶片金屬化層，則直接在小晶片上進行按壓。齊平工具頭1210可使小晶片1202各別地齊平或者如圖12A所示同時使一組小晶片1202齊平。齊平工具頭1210可橫跨整個晶圓、單個晶粒、一組晶粒或橫跨另一區或另一組同時使各小晶片1202齊平。
在圖12B中，同時對所有的小晶片1202進行接合。如先前所述，可使用直接接合、中間接合材料或如上所述其他接合技術來將小晶片1202接合至基板1204。在某些情形中，在放置小晶片之前，在凹陷部內沈積中間接合材料。接合製程可包括向整個積體小晶片晶圓1200施加熱製程，例如，烘烤、固化、退火或其他熱製程。在圖12C中，在小晶片1202及基板1204之上形成重佈線層1220。
圖13A及圖13B說明根據某些實施例形成經接合小晶片結構1300的態樣。圖13A顯示包括基板1304、可選介電層1306及小晶片1308的示例性頂部晶圓1302。在某些實施例中，頂部晶圓1302可為晶圓、晶片、積體電路晶粒、半導體元件、記憶體晶片、互連線結構、其他種類型的元件等。可選介電層1306可為一或多個介電層、一或多個金屬化層、重佈線層、互連線層、保護層或其他種類型的層。可選介電層1306可包括SiO2 或其他種類型氧化物、SiN、聚合物或其他種材料的一或多個層。在某些實施例中，頂部晶圓1302包括一或多個積體小晶片，例如圖2A至圖2C所示或者在此揭露內容其他位置處的積體小晶片晶圓200。
小晶片1308形成於可選介電層1306的表面上。在某些實施例中，小晶片1308形成於基板1304的表面上。小晶片1308可由半導體材料或例如SiO2 、SiN、聚合物或其他種介電材料等一或多種介電材料形成。小晶片1308可含有互連線、接觸墊、穿孔或其他導電特徵。可使用此項技術中習知的任意適合的方法或製造技術來形成小晶片1308。以下會針對圖16A至圖16B來闡述形成小晶片1308的某些實施例。
小晶片1308可具有與上述其他小晶片（例如，小晶片102）相似的尺寸或形狀。小晶片1308可在平面圖中具有正方形形狀、在平面圖中具有矩形形狀、在平面圖中具有十字形狀或在平面圖中具有其他形狀。在某些情形中，小晶片1308可在平面圖中具有約0.4微米或大於約0.4微米的長度，例如約1微米、2微米、10微米、100微米或另一長度。在某些情形中，小晶片1308具有約0.8微米或大於約0.8微米的厚度，例如約1微米、2微米、10微米、100微米或另一厚度。
在某些實施例中，基板1304可為由玻璃、矽（例如，矽晶圓）或其他種半導體材料、氧化矽或其他介電材料製成的晶圓、絕緣體上矽晶圓等或其他種類型的基板。在某些實施例中，基板1304可由金屬、陶瓷材料、塑膠或其他聚合物材料、其組合等製成。基板1304可為元件晶圓、中介板、晶粒或積體電路，且可包括主動元件或被動元件、金屬化層、保護層、介層窗、組合等。基板1304亦可為載體、空白載體晶圓、舟皿、框架、封裝等。
圖13A亦顯示包括基板1314、介電層1316及凹陷部1318的示例性底部晶圓1310。在某些實施例中，底部晶圓1310可為晶圓、晶片、積體電路晶粒、半導體元件、記憶體晶片、互連線結構、其他類型的元件等。介電層1316可包括一或多個介電層、一或多個金屬化層、重佈線層、互連線層、保護層或其他類型的層。介電層1316可包括SiO2 、SiN、其他類型的氧化物、聚合物或其他種材料的一或多個層。在某些實施例中，底部晶圓1310包括一或多個積體小晶片，例如圖2A至圖2C所示或者在此揭露內容其他位置處的積體小晶片晶圓200。
凹陷部1318形成於介電層1316的表面中且被造形成接納小晶片1308。凹陷部1318可完全穿過介電層1316延伸或如圖13A所示局部地穿過介電層1316延伸。可使用此項技術中習知的任意適合的方法或製造技術來形成凹陷部1318。以下會針對圖17A至圖17B來闡述形成凹陷部1318的某些實施例。在某些實施例中，凹陷部1318形成於基板1314中，且不存在介電層1316中的某些或全部。
在某些實施例中，凹陷部1318可具有與本文所述其他凹陷部（例如，圖1A所示凹陷部108）相似的尺寸或形狀。在某些實施例中，凹陷部1318可在平面圖中具有正方形形狀、在平面圖中具有矩形形狀、在平面圖中具有十字形狀或在平面圖中具有其他形狀。在某些實施例中，凹陷部1318可在平面圖中具有約0.4微米或大於約0.4微米的長度，例如約1微米、2微米、10微米、100微米或另一長度。在某些實施例中，凹陷部1318具有約0.8微米或大於約0.8微米的深度，例如約1微米、2微米、10微米、100微米或另一深度。
圖13B顯示將頂部晶圓1302接合至底部晶圓1310以形成經接合小晶片結構1300。在經接合小晶片結構1300中，將小晶片1308放置至凹陷部1318中。在某些實施例中，凹陷部1318的深度大於小晶片1308的厚度，進而使得在小晶片1308的底表面與凹陷部1318的底表面之間存在間隙。如此一來，可減弱因小晶片1308的厚度變化或凹陷部1318的深度變化帶來的影響。在某些實施例中，可在放置期間將小晶片1308及凹陷部1318浸入水中以利於自對準，以下會更詳細地予以闡述。
在將頂部晶圓1302與底部晶圓1310接合於一起、進而使得小晶片1308放置於凹陷部1318內之後，可將頂部晶圓1302接合至底部晶圓1310。在某些實施例中，將小晶片1308接合至凹陷部1318的側壁。在某些實施例中，將介電層1306接合至介電層1316。在某些實施例中，接合製程是直接接合製程、混合接合製程或其他種接合製程。舉例而言，所述接合製程可形成SiO-SiO接合、金屬-金屬接合或其他種類型的接合。所述接合製程可包括例如表面製備步驟、一或多次退火、浸水或此領域中習知的其他技術。
在某些實施例中，小晶片1308的側壁1320及凹陷部1318的對應側壁1322可具有相似的形狀或具有相似的輪廓。多於一個小晶片側壁1320及多於一個凹陷部側壁1322可具有對應的形狀或輪廓。如此一來，小晶片側壁1320與凹陷部側壁1322的面積中的某些、大部分或全部可在實體上進行接觸。舉例而言，在圖13A所示說明性實施例中，小晶片側壁1320實質上為平面且具有角度θ，且凹陷部側壁1322實質上亦為具有角度θ的平面。因此，如圖13B所示，當將小晶片1308放置於凹陷部1318中時，呈相似角度的側壁使得小晶片側壁1320的部分能夠平行於並在實體上接觸凹陷部側壁1322的部分。此與先前論述的小晶片及凹陷部（例如在圖1A至圖1B所示者）的行為相似。具有呈相似形狀的側壁可使得小晶片1308與凹陷部1318之間存在更大的接觸表面積，此可改良小晶片1308與凹陷部1318之間的接合。此外，如文中所詳細地闡述，具有相似的側壁亦可使得小晶片1308在凹陷部1318內的對準能夠改善，且因此使頂部晶圓1302與底部晶圓1310的對準能夠改善。
在某些實施例中，小晶片的側壁或凹陷部的側壁可能不如圖13A至圖13B所示為平直的或為平坦的。所述小晶片可具有具有實質上恆定的側壁角度的一或多個側壁。在其他實施例中，所述側壁中的某些或全部可為彎曲的，側壁的不同部分可具有不同的角度，或者所述側壁可具有不規則的形狀。在某種情形中，小晶片的各側壁或凹陷部的各側壁是對稱的。在某種情形中，小晶片的不同的側壁可具有不同的形狀且凹陷部的不同的側壁可具有不同的形狀。
在某些情形中，本文所述小晶片1308及凹陷部1318可使得能夠達成頂部晶圓1302與底部晶圓1312的自對準。本文所述小晶片1308及凹陷部1318亦可使頂部晶圓1302及底部晶圓1312能夠減少因用於使頂部晶圓1302對準底部晶圓1312的對準工具的不精確而造成的未對準。舉例而言，在圖13A中，小晶片側壁1320朝小晶片1308的底部向內成角度，且圖13A所示凹陷部側壁1322朝凹陷部1318的底部向內成角度。在頂部晶圓1302的對準期間，若頂部晶圓1302不精確地對準底部晶圓1310，則在小晶片1308向下移動至凹陷部1318中時，小晶片側壁1320將撞擊於凹陷部側壁1322上並貼靠凹陷部側壁1322滑動。小晶片側壁1320與凹陷部側壁1322的相似的角度會使得在小晶片1308向下移動至凹陷部1318中時小晶片1308朝更對準的位置側向位移。小晶片1308可向下移動至凹陷部1318中直至頂部晶圓1302（不包括小晶片1308）的底表面接觸底部晶圓1310的頂表面為止。如此一來，頂部晶圓1302可自對準至底部晶圓1310。在某些情形中，若小晶片側壁1320的至少底部位於凹陷部側壁1322的至少頂部之上，小晶片1308便可進行自對準。此種自對準動作類似於以上針對圖1A至圖1B所示實施例所闡述者。
在圖13A至圖13B所示實例中，對準期間的初始未對準d i 可減小至最終未對準d f ，其中d i ＞d f 。如此一來，即便對準工具的對準容差或不精確值大於d f ，最終未對準仍可為約d f 或小於約d f 。在某些實施例中，最終未對準d f 可為0.1微米、0.2微米、0.5微米、1.0微米或另一距離。圖13C說明頂部晶圓1302及底部晶圓1310的剖視圖，其中標記出了小晶片1308及凹陷部1318的尺寸。圖13C中的標記尺寸是示例性尺寸，可對所述示例性尺寸進行控制或規範以配置小晶片1308及凹陷部1318的尺寸及形狀。亦可對其它未被標記的尺寸或特性進行控制，例如小晶片1308的垂直於剖視圖的長度或凹陷部1318垂直於剖視圖的長度。在圖13C所示說明性實例中，小晶片1308具有頂部寬度Wc 、底部寬度Bc 、厚度Tc 及側壁角度q c 。凹陷部1318具有頂部寬度Wr 、底部寬度Br 、深度Dr 及側壁角度q r 。在某些實施例中，仍能達成小晶片1308與凹陷部1318的自對準的小晶片1308與凹陷部1318的最大初始未對準d i 是由d i =（Wr -Bc ）給出。在某些情形中，Bc 及Wr 可被配置成使得此最大初始未對準d i =（Wr -Bc ）大於或等於對準工具的預期不精確值。如此一來，儘管因對準工具而存在預期未對準，小晶片1308仍可能夠自對準至凹陷部1318。在某些實施例中，最終未對準d f 可為預定的，且接著可由d f =（Wr -Wc ）來確定Wr 及/或Wc ，且可由d f =（Br -Bc ）來確定Br 及/或Bc 。作為另一說明性實例，若已知小晶片1308的Bc 、Tc 及側壁角度q c ，則可由表達式Wc =Bc +2Tc /tan(q c )來確定頂部寬度Wc 。如此一來，小晶片1308及凹陷部1318便可以某些尺寸形成以適應於具體對準工具的已知不精確值、製程規範、設計限制或其他因素。
因此，小晶片1308與凹陷部1318的自對準行為可使得能夠達成在初始對準期間更大的未對準容差及減小的最終未對準兩者。其他小晶片、凹陷部及實施例的未對準容差端視例如小晶片側壁及凹陷部側壁的角度或形狀、小晶片的厚度及尺寸及凹陷部的深度及尺寸等因素而定。較大的未對準容差可能夠達成較快的對準，乃因對準工具可能並不需要過多時間來使具有小晶片的基板精確地對準具有對應的凹陷部的基板。
圖14A及圖14B說明根據某些實施例的形成堆疊式晶圓結構1400的態樣。圖14A繪示將示例性頂部晶圓1402接合至示例性底部晶圓1410以形成堆疊式晶圓結構1400的剖視圖。頂部晶圓1402包括基板1404、具有接觸墊1426的介電層1406及小晶片1408。底部晶圓1410包括基板1414、具有接觸墊1428的介電層1416及凹陷部1418。頂部晶圓1402或底部晶圓1410可與本文中所述其他晶圓相似，例如上述頂部晶圓1302或底部晶圓1310。頂部晶圓1402或底部晶圓1410可包括未在圖14A至圖14B中顯示的層、結構或特徵。圖14A至圖14B所示接觸墊1426及接觸墊1428是說明性實例，且在某些實施例中，可各自不完全貫穿介電層1406或介電層1416而延伸。在某些實施例中，接觸墊1426或接觸墊1428可為重佈線層、金屬化層、介層窗、主動元件或被動元件、中介板或其他導電特徵或層的一部分或可電性連接至重佈線層、金屬化層、介層窗、主動元件或被動元件、中介板或其他導電特徵或層。小晶片1408或凹陷部1418可與先前所述小晶片1308或凹陷部1318相似。其他實施例包括小晶片1408或凹陷部1418的其他數目、形狀或排列形式。
圖14B說明將頂部晶圓1402接合至底部晶圓1410以形成堆疊式晶圓結構1400的示例性剖視圖。已使頂部晶圓1402對準底部晶圓1410，且已將小晶片1408放置至其對應的凹陷部1418中。在對準期間，可利用或可不利用小晶片1408及凹陷部1418的自對準行為。在某些實施例中，在接合之後使堆疊式晶圓結構1400單體化。可使用直接接合、介電接合、金屬接合、混合接合或其他接合技術來將頂部晶圓1402接合至底部晶圓1410。在某些實施例中，可將介電層1406接合至介電層1416。此外，可將頂部晶圓1402上的接觸墊1426接合至底部晶圓1410上的接觸墊1428以在兩個晶圓之間形成互連。如此一來，頂部晶圓1402與底部晶圓1410可進行電性連接並在存在於頂部晶圓1402及底部晶圓1410中的或存在於頂部晶圓1402及底部晶圓1410上的元件或結構之間形成互連。
圖15A及圖15B說明根據某些實施例的形成堆疊式晶圓結構1500的態樣。圖15A繪示將示例性頂部晶圓1502接合至示例性底部晶圓1510以形成堆疊式晶圓結構1500的剖視圖。頂部晶圓1502包括具有接觸墊1526的介電層1506、導電連接件1530及小晶片1508。底部晶圓1510包括具有接觸墊1528的介電層1516、導電連接件1532及凹陷部1518。頂部晶圓1502或底部晶圓1510可與本文中所述其他晶圓相似，例如上述頂部晶圓1302或底部晶圓1310。頂部晶圓1502或底部晶圓1510可包括未在圖15A至圖15B中顯示的層、結構或特徵。
參照圖15A至圖15B，在接觸墊1526上形成導電連接件1530且在接觸墊1528上形成導電連接件1532。在某些實施例中，接觸墊1526或接觸墊1528可為凸塊下金屬化層（Under-Bump Metallization，UBM）。導電連接件1530或導電連接件1532可為球柵陣列（ball grid array，BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件1530或導電連接件1532可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。在某些實施例中，藉由以下方式來形成導電連接件1530或導電連接件1532：首先藉由例如蒸鍍、電鍍、印刷焊料轉移、植球等常用方法來形成焊料層。一旦已在結構上形成焊料層，則可執行迴焊以將材料造形成所期望的凸塊形狀。在另一實施例中，導電連接件1530或導電連接件1532是藉由濺鍍、印刷、電鍍、無電解電鍍、化學氣相沈積（chemical vapor deposition，CVD）等形成的金屬柱（例如銅柱）。金屬柱可為無焊料的（solder free）且具有實質上垂直的側壁。在某些實施例中，在金屬柱導電連接件1530或金屬柱導電連接件1532的頂部上形成金屬頂蓋層（圖中未顯示）。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合，且可藉由鍍覆製程來形成。在某些實施例中，存在導電連接件1530或導電連接件1532。
圖15B說明將頂部晶圓1502接合至底部晶圓1510以形成堆疊式晶圓結構1500的示例性剖視圖。已使頂部晶圓1502對準底部晶圓1510，且已將小晶片1508放置至其對應的凹陷部1518中。在對準期間，可利用或可不利用小晶片1508及凹陷部1518的自對準行為。在某些實施例中，在接合之後使堆疊式晶圓結構1500單體化。可將頂部晶圓1502的導電連接件1530接合至底部晶圓1510的導電連接件1532以在兩個晶圓之間形成互連結構1534。在實施例中，藉由迴焊製程來將頂部晶圓1502接合至底部晶圓1510。在此迴焊製程期間，導電連接件1530接觸導電連接件1532及金屬化圖案106以將頂部晶圓1502實體地及電性地耦合至底部晶圓1510。在某些實施例中，存在導電連接件1530或導電連接件1532，且將一個晶圓上的導電連接件接合至相對的晶圓的接觸墊。在某些實施例中，可在頂部晶圓1502與底部晶圓1510之間環繞導電連接件1530、導電連接件1532或小晶片1508形成底部填充物（圖中未顯示）。
在圖15A至圖15B所示實施例中，小晶片1508的厚度（Tc ）大於凹陷部1518的深度（Dr ）以使得在頂部晶圓1502與底部晶圓1510之間存在間隙g 。間隙g 可由g =（Tc -Dr ）近似地確定。間隙g 使得存在使導電連接件1530與導電連接件1532進行迴焊或接合的空間。在某些情形中，小晶片1508的厚度（Tc ）及凹陷部1518的深度（Dr ）可用以確定間隙g 的具體高度。因此，可對間隙g 的高度進行調整，以例如使導電連接件1530或導電連接件1532的接合的特性最佳化或以其他方式調整導電連接件1530或導電連接件1532的接合的特性。
圖16A至圖16D說明根據實施例形成小晶片1608的中間步驟。各別小晶片1608可為相同的元件或不同的元件或者可為先前所述不同類型的小晶片（例如，圖13A至圖13C所示小晶片1308）。圖16A顯示示例性基板1604、具有接觸墊1626的第一介電層1606及具有小晶片區1602的第二介電層1610。小晶片區1602表示欲自基板1604形成小晶片1608的位置。示例性基板1604可為半導體基板、晶圓、積體電路晶粒或者可為先前所述其他種類型的基板。第一介電層1606或第二介電層1610可與圖13A至圖13C所示介電層1316相似，或與先前所述介電層相似。在某些實施例中，第二介電層1610是第一介電層1606的一部分。
圖16B顯示在其表面上安置有罩幕1612的第二介電層1610。已將罩幕1612圖案化以在後續蝕刻步驟期間保護小晶片區1602。罩幕1612可為例如光阻或硬罩幕且可使用任意適合的光微影技術來將罩幕1612圖案化。在將罩幕1612圖案化之後，對第二介電層1610的犧牲部分進行蝕刻以隔離小晶片區1608。在移除第二介電層1610的犧牲部分之後，可暴露出接觸墊1626。在對第二介電層1610的犧牲部分進行蝕刻之後，經隔離的小晶片1608依舊存在。在已隔離出小晶片1608之後將罩幕1612移除。
可使用任意適合的濕式蝕刻技術或乾式蝕刻技術來移除第二介電層1610的犧牲部分。舉例而言，可使用反應性離子蝕刻（Reactive Ion Etching）或其他電漿蝕刻製程來移除第二介電層1610的某些部分。在其他實施例中，可使用各向同性蝕刻、乾式蝕刻或蝕刻技術的組合來隔離小晶片並對小晶片側壁進行造形，包括形成具有其他角度的小晶片側壁。舉例而言，可藉由調整電漿蝕刻製程的適宜參數來控制小晶片側壁的角度。在某些實施例中，可形成小晶片1608作為後端製造製程（BEOL）階段的一部分。
圖17A至圖17B說明根據實施例形成凹陷部1718的中間步驟。各別凹陷部1718可與本文中先前所述凹陷部（例如，圖13A至圖13B所示凹陷部1318）相似。圖17A顯示示例性基板1704以及具有接觸墊1728及凹陷部區1702的介電層1706。凹陷部區1702表示介電層1706中的將形成凹陷部1718的位置。示例性基板1704可為半導體基板、晶圓、積體電路晶粒或者可為先前所述其他種類型的基板。介電層1706可與圖13A至圖13C所示介電層1316相似，或與先前所述其他介電層相似。
圖17B顯示在其表面上安置有罩幕1712的介電層1706。已將罩幕1712圖案化以在後續蝕刻步驟期間保護介電層1706的靠近凹陷部區1702的部分。罩幕1712可為例如光阻或硬罩幕且可使用任意適合的光微影技術來將罩幕1712圖案化。在將罩幕1712圖案化之後，對介電層1706的凹陷部區1702進行蝕刻以形成凹陷部1718。在已形成凹陷部1718之後移除罩幕1612。
可使用任意適合的濕式蝕刻技術或乾式蝕刻技術來移除介電層1706的凹陷部區1702。舉例而言，可使用反應性離子蝕刻或其他電漿蝕刻製程來移除介電層1706的某些部分。在其他實施例中，可使用各向同性蝕刻、乾式蝕刻或蝕刻技術的組合來形成凹陷部並對凹陷部側壁進行造形，包括形成具有其他角度的凹陷部側壁。舉例而言，可藉由調整電漿蝕刻製程的適宜參數來控制凹陷部側壁的角度。在某些實施例中，可形成凹陷部1718作為後端製造製程（BEOL）階段的一部分。可使用任意適合的濕式蝕刻技術或乾式蝕刻技術（包括與上述用於形成圖16B所示小晶片1608的蝕刻技術相似的蝕刻技術）來移除凹陷部區1702。使用相似的技術形成小晶片側壁及凹陷部側壁可使得能夠達成改良的小晶片自對準及改良的小晶片-基板接合。
圖18A及圖18B說明根據某些實施例形成堆疊式晶圓結構1800的態樣。圖18A繪示將示例性頂部晶圓1802接合至示例性底部晶圓1810以形成堆疊式晶圓結構1800的剖視圖。頂部晶圓1802包括具有接觸墊1826的頂部介電層1806。在頂部介電層1806上安置有頂部小晶片1808，且頂部介電層1806亦包括頂部凹陷部1819。底部晶圓1810包括具有接觸墊1828的底部介電層1816。在底部介電層1816上安置有底部小晶片1809，且底部介電層1816亦包括底部凹陷部1818。頂部晶圓1802或底部晶圓1810可類似於本文中所述其他晶圓，例如上述頂部晶圓1302或底部晶圓1310。頂部晶圓1802或底部晶圓1810可包括未在圖18A至圖18B中顯示的層、結構或特徵。圖18A至圖18B所示接觸墊1826及接觸墊1828是說明性實例，且在某些實施例中可各自不完全貫穿介電層1806或介電層1816而延伸。在某些實施例中，接觸墊1826或接觸墊1828可為重佈線層、金屬化層、介層窗、主動元件或被動元件、中介板或其他導電特徵或層的一部分或可電性連接至重佈線層、金屬化層、介層窗、主動元件或被動元件、中介板或其他導電特徵或層。頂部小晶片1808、底部小晶片1809、頂部凹陷部1819或底部凹陷部1818可與先前所述小晶片1308或凹陷部1318相似。其他實施例包括小晶片或凹陷部的其他數目、形狀或排列形式。
圖18B說明使頂部晶圓1802對準並接合至底部晶圓1810以形成堆疊式晶圓結構1800的示例性剖視圖。已將頂部小晶片1808放置至底部凹陷部1818中，且已將底部小晶片1809放置至頂部凹陷部1819中。在對準期間，可利用或可不利用小晶片及凹陷部的自對準行為。在某些實施例中，在接合之後使堆疊式晶圓結構1800單體化。可使用直接接合、介電接合、金屬接合、混合接合或其他接合技術來將頂部晶圓1802接合至底部晶圓1810。在某些實施例中，可將介電層1806接合至介電層1816。此外，可將頂部晶圓1802上的接觸墊1826接合至底部晶圓1810上的接觸墊1828以在兩個晶圓之間形成互連。如此一來，頂部晶圓1802與底部晶圓1810可進行電性連接並在存在於頂部晶圓1802及底部晶圓1810中的或存在於頂部晶圓1802及底部晶圓1810上的元件或結構之間形成互連。
圖19A至圖19C說明根據某些實施例形成堆疊式晶圓結構的態樣。圖19A至圖19C繪示將示例性頂部晶圓1902的一部分接合至示例性底部晶圓1910以分別形成堆疊式晶圓結構1900a至堆疊式晶圓結構1900c的平面圖。頂部晶圓1902或底部晶圓1910可相似於本文中所述其他晶圓，例如先前在圖13A至圖18A中所述頂部晶圓或底部晶圓。圖19A至圖19C亦顯示示例性小晶片區1908，其中小晶片及其對應的凹陷部可位於頂部晶圓1902及/或底部晶圓1910上。小晶片區1908的小晶片或凹陷部可與先前在圖13A至圖18A中所述的小晶片或凹陷部相似。
圖19A顯示具有四個矩形小晶片區1908的示例性堆疊式晶圓結構1900a。在某些情形中，使用矩形小晶片區1908（具體而言，使用如圖19A所示具有相對長的尺寸的矩形小晶片區1908）可改良頂部晶圓1902與底部晶圓1910的最終角度對準。將小晶片區1908分離亦可改良最終角度對準。圖19A顯示排列有多個小晶片區1908的示例性堆疊式晶圓結構1900b。在某些實施例中，小晶片區1908可被分佈成使頂部晶圓1902及/或底部晶圓1910的主動區域最大化。小晶片區1908可例如具有不對稱的分佈及/或具有不規則的尺寸或形狀。圖19C顯示具有十字形狀的小晶片區1908的示例性堆疊式晶圓結構1900c。在某些情形中，小晶片區1908可被造形成有利於沿多於一個軸線進行對準（例如，圖19C所示十字形狀）。在某些實施例中，小晶片區1908可被造形成例如環形狀、T形狀、H形狀、散列標記（hash-mark）形狀、在一或多個方向上具有多個「分支」或被造形成其他形狀。在某些實施例中，一或多個小晶片區1908可位於切割道區中，此可有助於節省主動區域。其他實施例包括小晶片或凹陷部的其他數目、形狀或排列形式。
本發明的實施例可達成以下優點：能夠自對準，從而能夠提高在小晶片放置期間的未對準容差；以及在小晶片放置之後能夠達到近乎於零的未對準。可將不同類型的多個小晶片整合於單個基板中，包括使用不同的製程技術製成的小晶片、由不同的半導體製成的小晶片，具有不同的形狀及尺寸的小晶片，或具有其他不同性質的小晶片。如此一來，可達成異質小晶片整合。接合在一起的積體小晶片晶粒可具有相似的面積，從而減少因面積失配而導致的面積懲罰。可使用後端製程在小晶片之上形成金屬化層，從而減少在後續封裝製程期間所需要的步驟或層的數目。在某些情形中，積體小晶片晶粒的使用可減少或消除在封裝中對中介板或基板穿孔的需要。亦可在晶圓上進行整合之前對小晶片進行測試，從而達成近乎100%的晶粒合格率。本發明的實施例可達成其他優點，例如能夠自對準從而使得未對準容差增大、且在晶圓-晶圓對準、晶片-晶圓對準或晶片-晶片對準期間的最終未對準減小。
根據實施例，一種形成半導體封裝的方法，其包括：在第一基板中形成第一凹陷部，其中所述第一凹陷部的開口的第一面積大於所述第一凹陷部的底部的第二面積；以及形成第一元件，其中所述第一元件的頂端的第三面積大於所述第一元件的底端的第四面積。所述方法亦包括將所述第一元件放置於所述第一凹陷部中，其中所述第一元件的所述底端面對所述第一凹陷部的所述底部；以及將所述第一元件的側壁接合至所述第一凹陷部的側壁。根據實施例，所述的方法更包括在所述第一元件之上及所述第一基板之上形成重佈線層。根據實施例，所述的方法更包括在所述第一基板中形成第二凹陷部，且更包括在所述第二凹陷部中放置第二元件。根據實施例，所述第一元件包含第一半導體材料且所述第二元件包含不同於所述第一半導體材料的第二半導體材料。
根據另一實施例，一種形成半導體封裝的方法，其包括：將元件至少局部地插入至在基板的頂表面中形成的凹陷部中，其中所述元件具有錐形輪廓，且其中所述插入使得所述元件沿側向且朝向所述基板的底表面移動。根據實施例，所述方法更包括使所述半導體元件的頂表面相對於所述基板的所述頂表面齊平。根據實施例，所述方法更包括將所述半導體元件接合至所述基板。根據實施例，其中所述接合包括在所述半導體元件與所述基板之間形成直接接合。根據實施例，其中所述半導體元件的所述突出部分的高度小於所述凹陷部的深度。根據實施例，其中所述半導體元件的所述突出部分包含介電材料。根據實施例，所述方法更包括使所述半導體元件自支撐膜分離。
根據另一實施例，一種半導體元件，其包括：基板，包括位於所述基板的頂表面中的多個凹陷部；以及多個小晶片，分別安置於所述多個凹陷部中，其中所述多個小晶片接合至所述基板。根據實施例，所述元件更包括安置於所述多個小晶片及所述基板之上的重佈線層，其中所述重佈線層電性連接至所述多個小晶片。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100‧‧‧積體小晶片結構
102、614、714、1608‧‧‧小晶片
104、604、704、802、904、1204、1304、1314、1404、1414、1604、1704‧‧‧基板
106、706、1212‧‧‧小晶片金屬化層
108、808、906、1318、1418、1518、1718‧‧‧凹陷部
110、1320‧‧‧小晶片側壁
112、1322‧‧‧凹陷部側壁
114‧‧‧間隙
200、500、504、502、510、512、514、520、522、524、526、1200‧‧‧積體小晶片晶圓
202a、202b、202c、902、1202、1308、1408、1508‧‧‧小晶片
204‧‧‧積體小晶片晶粒
206‧‧‧晶圓
208、1220‧‧‧重佈線層
300‧‧‧積體扇出型結構
302、312、322‧‧‧封裝重佈線層
304、314、324‧‧‧外部連接件
306‧‧‧包封體
310‧‧‧積體扇入型結構
320‧‧‧倒裝晶片晶片規模封裝
400‧‧‧第一積體小晶片晶圓
402‧‧‧第二積體小晶片晶圓
404‧‧‧第一積體小晶片晶粒
406‧‧‧第二積體小晶片晶粒
408‧‧‧堆疊式晶粒
450、1400、1500、1800、1900a、1900b、1900c‧‧‧堆疊式晶圓結構
506‧‧‧第一三層堆疊式晶圓
516‧‧‧第二三層堆疊式晶圓
530‧‧‧第一堆疊式晶圓
532‧‧‧第二堆疊式晶圓
534‧‧‧四層堆疊式晶圓
602、702、1602、1908‧‧‧小晶片區
610、910‧‧‧支撐層
612、712、806、1612、1712‧‧‧罩幕
616、716‧‧‧犧牲部分
710‧‧‧載體
804、1702‧‧‧凹陷部區
900‧‧‧工具
912、1012‧‧‧框架
1010‧‧‧膜
1210‧‧‧齊平工具頭
1300‧‧‧經接合小晶片結構
1302、1402、1502、1802、1902‧‧‧頂部晶圓
1310、1410、1510、1810、1910‧‧‧底部晶圓
1306、1316、1406、1416、1506、1516、1706‧‧‧介電層
1426、1428、1526、1528、1626、1728、1826、1828‧‧‧接觸墊
1530、1532‧‧‧導電連接件
1534‧‧‧互連結構
1606‧‧‧第一介電層
1610‧‧‧第二介電層
1806‧‧‧頂部介電層
1808‧‧‧頂部小晶片
1809‧‧‧底部小晶片
1816‧‧‧底部介電層
1818‧‧‧底部凹陷部
1819‧‧‧頂部凹陷部
B c 、B r ‧‧‧底部寬度
D r ‧‧‧深度
T c ‧‧‧厚度
W c 、W r ‧‧‧頂部寬度
θ‧‧‧角度
θ c 、θ r ‧‧‧側壁角度
δ‧‧‧未對準/初始放置未對準
δ i ‧‧‧初始未對準/最大初始未對準
δ f ‧‧‧最終未對準
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A至圖1B說明根據某些實施例的積體小晶片（integrated-chiplet）結構。 圖2A至圖2C說明根據某些實施例的積體小晶片晶圓。 圖3A至圖3C說明根據某些實施例的積體小晶片封裝。 圖4A至圖4D說明根據某些實施例的積體小晶片晶圓-晶圓接合。 圖5A至圖5C說明根據某些實施例的積體小晶片晶圓-晶圓接合。 圖6A至圖6D說明根據某些實施例的形成小晶片的中間步驟。 圖7A至圖7E說明根據某些實施例的形成小晶片的中間步驟。 圖8A至圖8C說明根據某些實施例的形成積體小晶片結構的基板的中間步驟。 圖9A至圖9D說明根據某些實施例的形成積體小晶片晶圓的中間步驟。 圖10A至圖10D說明根據某些實施例的形成積體小晶片晶圓的中間步驟。 圖11A至圖11D說明根據某些實施例的形成積體小晶片晶圓的中間步驟。 圖12A至圖12C說明根據某些實施例的形成積體小晶片晶圓的中間步驟。 圖13A至圖13C說明根據某些實施例的形成經接合小晶片結構的中間步驟。 圖14A至圖14B說明根據某些實施例的形成堆疊式晶圓結構的中間步驟。 圖15A至圖15B說明根據某些實施例的形成堆疊式晶圓結構的中間步驟。 圖16A至圖16B說明根據某些實施例的形成小晶片的中間步驟。 圖17A至圖17B說明根據某些實施例的形成凹陷部的中間步驟。 圖18A至圖18B說明根據某些實施例的形成堆疊式晶圓結構的中間步驟。 圖19A至圖19C說明根據某些實施例的堆疊式晶圓結構。

Claims (10)

  1. 一種形成半導體封裝的方法，包括：在第一基板中形成第一凹陷部，其中所述第一凹陷部的開口的第一面積大於所述第一凹陷部的底部的第二面積；形成第一元件，其中所述第一元件的頂端的第三面積大於所述第一元件的底端的第四面積；將所述第一元件放置於所述第一凹陷部中，其中所述第一元件的所述底端面對所述第一凹陷部的所述底部；以及將所述第一元件的側壁接合至所述第一凹陷部的側壁，使所述第一元件的頂表面與所述第一基板的頂表面實質上齊平。
  2. 如申請專利範圍第1項所述的方法，其中形成所述第一凹陷部包括形成所述第一凹陷部的側壁，所述側壁相對於所述第一基板的所述頂表面具有實質上恆定的側壁角度，其中所述第一凹陷部的所述側壁角度實質上不垂直於所述第一基板的所述頂表面。
  3. 如申請專利範圍第2項所述的方法，其中所述第一元件的所述側壁相對於所述第一元件的頂表面具有實質上恆定的角度，所述實質上恆定的角度大約相同於所述第一凹陷部的所述側壁角度。
  4. 如申請專利範圍第2項所述的方法，其中所述側壁角度為約54.7度。
  5. 如申請專利範圍第1項所述的方法，其中將第一元件放置至所述第一凹陷部中包括使所述第一元件的側壁的一部分沿所述第一凹陷部的側壁的一部分滑動，所述第一元件的所述側壁在實體上接觸所述第一凹陷部的所述側壁。
  6. 一種形成半導體封裝的方法，包括：使半導體元件對準基板，所述對準包括：將所述半導體元件的突出部分至少局部地插入至在所述基板的頂表面中形成的凹陷部中，其中所述半導體元件的所述突出部分具有錐形輪廓(tapered profile)，且其中所述插入使得所述半導體元件沿側向且朝向所述基板的底表面移動，且使所述半導體元件的頂表面與所述基板的所述頂表面實質上齊平。
  7. 如申請專利範圍第6項所述的方法，更包括使所述半導體元件的所述突出部分的側壁撞擊於所述凹陷部的側壁上。
  8. 如申請專利範圍第6項所述的方法，更包括將所述半導體元件接合至所述基板，所述接合包括在所述半導體元件與所述基板之間形成直接接合。
  9. 一種半導體元件，包括：基板，包括位於所述基板的頂表面中的多個凹陷部；以及多個小晶片，分別安置於所述多個凹陷部中，其中所述多個小晶片接合至所述基板，所述多個小晶片的頂表面與所述基板的所述頂表面實質上齊平。
  10. 如申請專利範圍第9項所述的半導體元件，其中所述多個小晶片中的第一小晶片包含與所述多個小晶片中的第二小晶片不同的半導體材料。
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