CN107768258B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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CN107768258B
CN107768258B CN201710708941.4A CN201710708941A CN107768258B CN 107768258 B CN107768258 B CN 107768258B CN 201710708941 A CN201710708941 A CN 201710708941A CN 107768258 B CN107768258 B CN 107768258B
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core
recess
substrate
wafer
core particle
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CN107768258A (zh
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邵栋梁
董志航
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例公开了半导体封装件及其形成方法。实施例包括在第一衬底中形成第一凹槽，其中第一凹槽的开口的第一面积大于第一凹槽的底部的第二面积。实施例还包括形成第一器件，其中第一器件的顶端的第三面积大于第一器件的底端的第四面积。实施例还包括将第一器件放置在第一凹槽中，其中第一器件的底端面向第一凹槽的底部，以及将第一器件的侧壁接合到第一凹槽的侧壁。

Description

半导体封装件及其形成方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及半导体封装件及其形成方法。
背景技术
自从集成电路(IC)的发明，由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业已经经历了快速增长。在大多数情况下，集成密度的这种改进来自于最小特征尺寸的重复减少，这允许更多的组件被集成到给定的区域中。
这些整合改进本质上是二维(2D)的，因为集成部件占据的体积基本上在半导体晶圆的表面上。虽然光刻技术的显著改进已经导致2D IC形成的显著改善，但是对在两个维度上可以实现的密度有物理限制。这些限制之一是制造这些部件所需的最小尺寸。此外，当更多的器件被放入一个芯片或管芯时，需要更复杂的设计。
为了进一步提高电路密度，已经研究了三维集成电路(3DIC)。在3DIC的典型的形成工艺中，将两个芯片接合在一起，并且在每个芯片和衬底上的接触焊盘之间形成电连接。例如，可以通过将一个芯片附接在另一个芯片上来实现两个芯片的接合。堆叠的芯片然后被接合到载体衬底，并且引线接合将每个芯片上的接触焊盘电耦合到载体衬底上的接触焊盘。然而，这需要比芯片的更大的载体衬底以用于引线接合。最近更多的尝试集中在倒装芯片互连和导电球/凸块的使用以形成芯片和下面的衬底之间的连接，从而允许在较小封装件中的高引线密度。使用焊接接头的传统芯片堆叠包括焊料、焊剂和底部填充。所有这些工艺都产生了对节距、接头高度和焊剂残留物的问题和限制。
发明内容
根据本发明的一个方面，提供了一种形成半导体器件的方法，包括：在第一衬底中形成第一凹槽，其中，所述第一凹槽的开口的第一面积大于所述第一凹槽的底部的第二面积；形成第一器件，其中，所述第一器件的顶端的第三面积大于所述第一器件的底端的第四面积；将所述第一器件放置在所述第一凹槽中，其中，所述第一器件的所述底端面向所述第一凹槽的所述底部；以及将所述第一器件的侧壁接合到所述第一凹槽的侧壁。
根据本发明的另一个方面，提供了一种形成半导体器件的方法，包括：将半导体器件对准至衬底，所述对准包括：将所述半导体器件的突出部分至少部分地插入至形成在所述衬底的顶表面中的凹槽中，其中，所述半导体器件的所述突出部分具有锥形轮廓，并且所述插入导致所述半导体器件横向和朝向所述衬底的底表面的移位。
根据本发明的又一个方面，提供了一种半导体器件，包括：衬底，包括在所述衬底的顶表面中的多个凹槽；以及多个芯粒，分别设置在所述多个凹槽中，其中，所述多个芯粒接合到所述衬底。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A至图1B示出了根据一些实施例的集成芯粒结构。
图2A至图2C示出了根据一些实施例的集成芯粒晶圆。
图3A至图3C示出了根据一些实施例的集成芯粒封装件。
图4A至图4D示出了根据一些实施例的集成芯粒晶圆至晶圆接合。
图5A至图5C示出了根据一些实施例的集成芯粒晶圆至晶圆接合。
图6A至图6D示出了根据一些实施例的形成晶圆的中间步骤。
图7A至图7E示出了根据一些实施例的形成芯粒的中间步骤。
图8A至图8C示出了根据一些实施例的形成集成芯粒结构的衬底的中间步骤。
图9A至图9D示出了根据一些实施例的形成集成芯粒晶圆的中间步骤。
图10A至图10D示出了根据一些实施例的形成集成芯粒晶圆的中间步骤。
图11A至图11D示出了根据一些实施例的形成集成芯粒晶圆的中间步骤。
图12A至图12C示出了根据一些实施例的形成集成芯粒晶圆的中间步骤。
图13A至图13C示出了根据一些实施例的形成接合芯粒结构的中间步骤。
图14A至图14B示出了根据一些实施例的形成堆叠晶圆结构的中间步骤。
图15A至图15B示出了根据一些实施例的形成堆叠晶圆结构的中间步骤。
图16A至图16B示出了根据一些实施例的形成芯粒的中间步骤。
图17A至图17B示出了根据一些实施例的形成凹槽的中间步骤。
图18A至图18B示出了根据一些实施例形成堆叠晶圆结构的中间步骤。
图19A至图19C示出了根据一些实施例的堆叠晶圆结构。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
图1A和图1B示出了根据一些实施例的形成集成芯粒(chiplet)结构100的方面。图1A示出了示例性芯粒102和示例性衬底104。图1B示出了芯粒102已经放置在衬底104中的凹槽108中之后的芯粒102。在一些实施例中，芯粒102可以是芯片、集成电路管芯、半导体器件、存储器芯片、互连结构、另一类型的器件等。芯粒102可以包括半导体材料或者由半导体材料(诸如Si、SiC、Ge、III-V族半导体材料、II-VI族半导体材料、另一种半导体材料、绝缘体上半导体(SOI)材料等)形成。在一些实施例中，芯粒102由一种或多种介电材料(诸如SiO2、SiN、聚合物或另一介电材料)形成。芯粒102可以使用本领域已知的任何合适的方法或制造技术来形成。下面将参考图6A至图6D和图7A至图7D描述形成芯粒102的一些实施例。
在一些实施例中，可选的芯粒金属化层106设置在芯粒102的顶表面上。芯粒金属化层106可以形成在芯粒102的有源和无源器件上方，并且可以连接各种器件以形成集成电路或集成电路的部分。芯粒金属化层106可以互连形成在芯粒102上的器件，并且还可以提供从芯粒102至外部器件或结构的外部连接。芯粒金属化层106可以由介电和导电材料的交替层形成，同时通孔将各导电材料层互连。芯粒金属化层106可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些情况下，芯粒金属化层106可以形成在制造工艺的后段制程(BEOL)阶段中。在一些实施例中，芯粒金属化层106包括再分布层(RDL)。
在一些实施例中，芯粒102可以具有在约1μm2至约10000μm2之间的平面图面积，诸如约100μm2。例如，芯粒102可以具有约10μm×10μm或其它尺寸的平面图尺寸。在一些实施例中，芯粒102具有小于1μm2或大于10000μm2的平面图面积。芯粒102可以具有在平面图中的正方形形状、在平面图中的矩形形状或者在平面图中的另一形状。在一些实施例中，芯粒102具有约1μm至约500μm之间的厚度，诸如约2μm、10μm、50μm或另一厚度。在一些实施例中，芯粒102具有小于1μm或大于500μm的厚度。
在一些实施例中，衬底104是由玻璃、硅(例如，硅晶圆)或另一半导体材料、氧化硅或其它介电材料、SOI晶圆等制成的晶圆。在一些实施例中，衬底104由金属、陶瓷材料、塑料或其它聚合物材料、它们的组合等制成。在一些实施例中，衬底104是器件晶圆、中介片、管芯或集成电路，并且可以包括有源或无源器件、金属化层、钝化层、通孔、它们的组合等。在一些实施例中，衬底104是载体、空白载体晶圆、晶舟、框架、封装件等。
衬底104包括成形为容纳芯粒102的凹槽108。在一些实施例中，凹槽108形成在设置在衬底104的表面上的一个或多个介电层中。图1B示出了放置在凹槽108中的芯粒102。在一些实施例中，当芯粒102放置在凹槽108中时，芯粒102的顶表面基本上与衬底104的顶表面平齐(如图1B所示)，尽管在其它实施例中芯粒102的顶表面可以在衬底104的顶表面之上或之下。在一些实施例中，芯粒金属化层106的顶表面可以与衬底104的顶表面基本平齐。在一些实施例中，凹槽108的深度大于芯粒102的厚度，使得在芯粒102的底表面和凹槽108的底表面之间存在间隙114。以这种方式，由于芯粒102的厚度或凹槽108的深度的变化的影响可以减小。
在放置在凹槽108内之后，芯粒102可以接合到衬底104。在一些实施例中，使用直接接合工艺将芯粒102接合到衬底104。例如，芯粒-衬底接合工艺可以形成Si-Si键，SiO-SiO键，Si-SiO键或其它类型的直接键合。在一些实施例中，在芯粒102和衬底104之间使用中间层用于芯粒-衬底接合。中间层可以是粘合剂层、环氧树脂、树脂、聚合物或另一种类型的接合材料。芯粒接合工艺可以包括例如表面制备步骤、一个或多个退火、水浸或本领域已知的其它技术。
在一些实施例中，芯粒102的侧壁110和凹槽108的对应的侧壁112可以具有相似的形状或具有相似的轮廓。多于一个芯粒侧壁110和多于一个的凹槽侧壁112可以具有相应的形状或轮廓。以这种方式，芯粒侧壁110和凹槽侧壁112的部分或全部区域可以物理接触。例如，在图1A所示的示例性实施例中，芯粒侧壁110是平面的并且具有θ的角，并且凹槽侧壁112也是具有θ角的平面。因此，如图1B所示，当芯粒102放置在凹槽108中时，类似倾斜的侧壁允许芯粒侧壁110的部分与凹槽侧壁112的部分平行并且物理接触。具有类似形状的侧壁可以允许芯粒102和衬底104之间的更多接触表面积，这可以改善芯粒102和衬底104之间的接合。此外，具有相似侧壁的还可以允许芯粒102在凹槽108内改进的对准，下面更详细地描述。
在一些实施例中，芯粒或凹槽的侧壁可以不是如图1A至图1B所示为直的或平面的。在其它实施例中，侧壁的一些或全部可以是弯曲的，侧壁的不同部分可以具有不同的角度，或者侧壁可以具有不规则形状。芯粒或凹槽可具有一个或多个具有基本上恒定的侧壁角的侧壁。例如，在正常工艺变化中侧壁角可以是恒定的。芯粒可以具有基本上不垂直于芯粒的顶部或底部表面的一个或多个侧壁。凹槽可以具有基本上不垂直于衬底的顶表面或凹槽的底表面的一个或多个侧壁。在一些情况下，芯粒或凹槽的侧壁是对称的。在一些情况下，芯粒的不同侧壁可以具有不同的形状，并且凹槽的不同侧壁可以具有不同的形状。
在一些情况下，如本文所述的芯粒侧壁110和凹槽侧壁112可以使得置放不对准的容错增大，并且还可以允许芯粒102在置放期间的自对准。例如，在图1A中，芯粒侧壁110朝向芯粒102的底部向内倾斜，并且图1A所示的凹槽侧壁112朝向凹槽的底部向内倾斜。在芯粒102放置期间，如果芯粒102不对准或未位于凹槽108中心(在图1A中示出为不对准δ)，则当芯粒102向下移动时，芯粒侧壁110将撞击凹槽侧壁112并且靠着凹槽侧壁112滑动。当芯粒102向下移动到凹槽108中时，芯粒侧壁110和凹槽侧壁112的类似角度使得芯粒102朝向居中的位置横向偏移。芯粒102可以向下移动到凹槽108中直到两个或更多的撞击侧壁阻止进一步的横向或向下移动，或直到芯粒102的底部撞击凹槽108的底部。以这种方式，芯粒102可以在放置期间自对准，并且初始置放不对准δ在放置后减至零或接近零。在一些情况下，芯粒102的顶表面可以在放置之后基本上与衬底104的顶表面齐平，并且在一些情况下，芯粒102的顶表面可以在放置后在衬底104的顶表面之上或之下。
这种自对准行为可使得放置期间的不对准的容差增大。在一些情况下，如果芯粒侧壁110的至少底部在凹槽侧壁112的至少顶部之上，则芯粒102可以自对准。因此，存在横向不对准容差，超过该容差，在放置期间芯粒102可以自对准。其它芯粒、凹槽和实施例的不对准容差取决于诸如芯粒侧壁和凹槽侧壁的角度或形状、芯粒的厚度和尺寸以及凹槽的深度和尺寸等因素。在一些情况下，不对准容差可以高达约700μm，尽管在其它情况下，不对准容差可以小于或大于约700μm。较大的不对准容差可以实现更快的芯粒放置，因为放置工具可能不需要太多的时间精确地将芯粒对准到相应的凹槽。此外，本文所述的芯粒的自对准行为尽管可能导致在放置期间存在大的不对准容差，但是在放置之后，芯粒具有接近零的不对准。
图2A至图2C示出了根据一些实施例的集成芯粒晶圆200的方面。集成芯粒晶圆200包括集成到单个晶圆206中的多个芯粒202a至202c。图2A至图2C中已经示出了一些芯粒202a至202c，尽管比所示的更多或更少的芯粒可以集成到晶圆206中。晶圆206可以是半导体晶圆(例如，硅晶圆)或不同类型的晶圆或衬底，诸如上文关于图1A至图1B中的衬底104所描述。各个芯粒202a至202c可以是与之前所述相同的也可以是不同的器件或不同类型的芯粒(例如，图1A至图1B所示的芯粒102)。例如，一些芯粒202a至202c可以是与其它芯粒202a至202c不同的集成管芯。芯粒202a至202c也可以由不同的材料形成。例如，在单个晶圆206上，可以由硅形成一个芯粒202a，可以由GaAs形成另外一个芯粒，可以由GaN形成第三个芯粒。芯粒202a至202c的其它材料和组合是可能的。此外，芯粒202a至202c可以使用不同的处理技术形成，并且可以具有不同的尺寸、形状、厚度等。以这种方式，多样化的芯粒可以集成在单个晶圆或衬底上。
在一些实施例中，每个芯粒在其放置到其凹槽中之前被测试。在芯粒测试之后，可以只选择好的芯粒用于集成芯粒晶圆。以这种方式，集成芯粒晶圆可以具有高的已知良好管芯(KGD)。因此，芯粒测试可能因此增加合并集成芯粒管芯的器件(诸如下面在图3A至图3C中描述的封装件)的总体产量。
图2A至图2C示出了集成芯粒晶圆200，集成芯粒晶圆200包括形成在芯粒202a至202c和晶圆206上方的可选的RDL 208。RDL 208可以包括至芯粒202a至202c和晶圆206的接触件和以及在芯粒202a至202c和晶圆206之间的互连件，如图2C中更详细所示。在一些实施例中，RDL 208可以形成在制造工艺的BEOL阶段。以这种方式，可以使用单个RDL形成工艺来互连多个芯粒，包括如前所述的不同类型的芯粒。在一些实施例中，一些芯粒202a至202c包括芯粒金属化层，诸如上面在图1A至图1B中描述的金属化层106。RDL 208可以布置在芯粒金属化层上方并且与芯粒金属化层连接。在一些情况下，在芯粒上使用芯粒金属化层可以减少覆盖的RDL原本需要的层数。
在一些实施例中，集成芯粒晶圆200包括多个集成芯粒管芯。在图2A中的横截面中和在图2B的平面图中示出了示例性集成芯粒管芯204。如图2B所示，每个集成芯粒可以从集成芯粒晶圆200分割。集成芯粒可以包括以不同布置相邻定位的多个不同的芯粒。
图3A至图3C示出了根据一些实施例的封装件集成芯粒管芯的方面。图3A示出了使用集成芯粒管芯204的示例性集成扇出型(InFO)结构300。集成芯粒管芯204可以包括一个或多个芯粒(例如，图1A至图1B所示的芯粒102)。在示例性InFO结构300中，管芯204的RDL208接合至或以其它方式连接至InFO结构300的封装件RDL 302。管芯RDL 208和封装件RDL302可以电连接并且形成芯粒与InFO结构300内的其它器件之间的互连。封装件RDL 302连接到外部连接件304。管芯204的宽度小于InFO结构300的宽度，并且管芯204被密封剂306包围。
图3B示出使用集成芯粒204的示例性集成扇入型(InFI)结构310。在示例性InFI结构310中，集成芯粒管芯204的RDL 208接合至或以其它方式连接至封装件InFI结构310的RDL 312。管芯RDL 208和封装件RDL 312可以电连接并且形成芯粒和InFI结构310内的其它器件之间的互连。封装件RDL 312连接至外部连接件314。管芯204的宽度与InFI结构310的宽度相同或比InFI结构310的宽度更大。
图3C示出了使用集成芯粒管芯204的示例性倒装芯片级封装件(Flip-Chip Chip-Scale Package，FCCSP)结构320。在示例性FCCSP结构320中，集成芯粒管芯204的RDL 208接合至或以其它方式连接到FCCSP结构320的封装件RDL 322。管芯RDL 208和封装件RDL 322可以电连接并且形成芯粒和FCCSP结构320内的其它器件之间的互连。封装件RDL 322连接到外部连接件314。
图3A至图3C示出了一些示例性集成芯粒封装件，但是其它类型的包含集成芯粒管芯的封装件是可能的。在一些实施例中，可以在InFO、InFI FCCSP、晶圆衬底芯片(CoWoS)或其它类型的封装件中使用集成芯粒，而不使用衬底通孔(TSV)或中介片。在一些实施例中，使用形成在集成芯粒管芯上的RDL可以降低封装件RDL所需的层的复杂性或数量。此外，使用标准BEOL工艺在集成芯粒管芯上形成RDL可以降低形成集成芯粒封装件所需的整体复杂性或工艺步骤数量。
图4A至图4D示出了根据一些实施例的晶圆至晶圆接合过程中的中间步骤。图4A示出了第一集成芯粒晶圆400和第二集成芯粒晶圆402的示例性截面图，图4C示出了第一晶圆400和第二晶圆402的平面图。第一集成芯粒晶圆400包括多个第一集成芯粒管芯404，第二集成芯粒晶圆402包括多个第二集成芯粒管芯406。集成芯粒管芯404、406的每一个可以包括一个或多个芯粒(例如，图1A至1B中示出的芯粒102)。图4B示出了第一晶圆400接合至第二晶圆402以形成堆叠晶圆结构450的示例横截面，并且图4D示出了第一晶圆400和第二晶圆402接合以形成堆叠晶圆结构450的平面图。第一晶圆400可以使用直接接合、电介质接合、金属接合、混合接合或另一种接合技术接合到第二晶圆402。第一晶圆400和第二晶圆402可以被接合，使得具有芯粒的表面彼此面对(“面对面”)。此外，每个晶圆400、402上的RDL可以接合在一起，以在两个晶圆上的RDL和芯粒之间形成互连。例如，晶圆400、402可以对准，使得在接合之后RDL上的接触焊盘电连接。在一些情况下，中间互连层、衬底或中介片可以设置在晶圆400、402之间。在其它实施例中，集成芯粒晶圆可以接合到不同类型的晶圆或衬底。
可以将晶圆400、402接合，使得第一管芯404与第二管芯406对准，以在堆叠晶圆结构450中形成堆叠的管芯408。在接合之后，堆叠的管芯408可以从堆叠晶圆结构450分割。在一些实施例中，芯粒在放置在晶圆400、402之前被测试。通过仅使用已知的好芯粒，可以大大提高集成芯粒管芯是好的的可能性。以这种方式，第一晶圆400可以包含高KGD的第一管芯404，并且第二晶圆402可以包含高KGD的第二管芯406。这可能导致包含高KGD的堆叠管芯408的堆叠晶圆结构450。在一些情况下，管芯404、406也可以在接合之前进行测试。在一些情况下，晶圆400、402和堆叠晶圆结构450的KGD可以处于或接近100％。在一些情况下，第一管芯404具有与第二管芯408大致相同的面积，从而可以减少或消除由于管芯区域失配引起的面积损失。
图5A至图5C示出了根据实施例的其它堆叠集成芯粒晶圆配置的方面。集成芯粒晶圆中的每一个可以包括一个或多个芯粒(例如，图1A至图1B中所示的芯粒102)或集成芯粒管芯(例如，图2A至图2C所示的集成芯粒管芯204)。例如，在图5A中，集成芯粒晶圆500面对面地接合到集成芯粒晶圆502，并且集成芯粒晶圆504面朝下地接合到晶圆502。这形成第一3层堆叠晶圆506。在图5B中，集成芯粒晶圆510面对面地接合到集成芯粒晶圆512，并且集成芯粒晶圆514面朝上地接合到晶圆512。这形成第二3层堆叠晶圆516。在图5C中，集成芯粒晶圆520面对面地接合到集成芯粒晶圆522以形成第一堆叠晶圆530，并且集成芯粒晶圆524面对面地接合到集成芯粒晶圆526以形成第二堆叠晶圆532。第一堆叠晶圆530接合到第二堆叠晶圆532以形成4层堆叠晶圆534。在其它实施例中，一个或多个集成芯粒晶圆可以接合到一个或多个不同类型的晶圆，并且接合到比图5A至图5C所示的更多或更少的晶圆。可以使用直接接合、电介质接合、金属接合、混合接合或另一种接合技术来接合晶圆。在一些情况下，可以使用通过晶圆的一个或多个衬底通孔(TSV)来形成与芯粒、RDL或其它结构的内部或外部连接。其它组合、配置、连接或接合方法可能用于形成包括至少一个集成芯粒晶圆的堆叠晶圆。在某些情况下，集成芯粒晶圆的部分或全部可以具有相同面积的集成芯粒管芯。
图6A至图6D示出了根据实施例形成芯粒614的中间步骤。单独的芯粒614可以是与之前描述相同的或者是(例如，图1A至图1B所示的芯粒102)不同的器件或不同类型的芯粒。图6A示出了示例性衬底604和芯粒区域602。芯粒区域602指示将由衬底604形成芯粒614的位置。示例衬底604可以是半导体衬底(例如，硅衬底、SOI衬底、GaAs衬底或另一半导体衬底)或如上所述的另外类型的衬底材料。衬底604已经被处理，使得芯粒区域602包含电路、晶体管、电阻器、其它无源和有源器件等。例如，可以使用本领域已知的制造技术在每个芯粒区域602中形成集成电路。在一些实施例中，在衬底604上形成芯粒金属化层。
图6B示出了在衬底604的表面上方形成支撑层610之后的衬底604。支撑层610可以是SiN、氧化物、另一种介电材料、聚合物或其它材料。如图6B所示，衬底604的底部也可以薄化。衬底604的薄化可以例如通过蚀刻工艺和/或平面化工艺(例如机械研磨工艺或化学机械抛光(CMP))工艺来实现。如图6B所示，衬底604可以被薄化至芯粒区域602的底表面附近。在一些实施例中，薄化工艺不执行或在与所示不同的步骤执行
图6C示出了具有设置在其底表面上的掩模612的衬底604。掩模612已经被图案化以在随后的蚀刻步骤期间保护芯粒区域602。掩模612可以是例如光刻胶或硬掩模，并且可以使用任何合适的光刻技术来图案化。
在掩模612已被图案化之后，蚀刻衬底604的牺牲部分以隔离芯粒区域602。在芯粒区域602之间的示例牺牲部分616在图6C中被标记。在蚀刻衬底604的牺牲部分之后，隔离的芯粒602保持附接到支撑层610。在芯粒614被隔离之后，去除掩模612。图6D示出了附接到支撑层610的隔离的芯粒614。
可以使用任何合适的湿或干蚀刻技术去除衬底604的牺牲部分。例如，在衬底604是具有(100)晶向的硅的实施例中，可以使用各向异性蚀刻剂，诸如KOH、EDP、TMAH或另一种蚀刻剂。在该实例中，各向异性蚀刻剂可以导致每个芯粒614具有对应于(111)硅晶向的基本平坦的侧壁。芯粒614侧壁具有对应于(111)硅晶向的约54.74°的角。可以使用具有各向异性蚀刻剂的其它合适的衬底，诸如GaAs、GaN等。使用各向异性蚀刻剂可以在侧壁角和平面度上允许更多的可复制性。然而，在其它实施例中，各向同性蚀刻、干蚀刻或蚀刻技术的组合可以用于分离芯粒和使芯粒侧壁成形，包括形成具有其它角度的芯粒侧壁。
图7A至图7E示出了根据实施例的形成芯粒714的中间步骤。各个芯粒714可以是与之前所描述的(例如，图1A至图1B中所示的芯粒102)相同的或者不同的器件或不同类型的芯粒。图7A示出了示例性衬底704和芯粒区域702。芯粒区域702指示将由衬底704形成芯粒714的位置。示例衬底704可以是如前所述的半导体衬底或另一类型的衬底材料。衬底704已经被处理以形成如前所述的芯粒区域702。
图7B示出了形成在芯粒区域702上方的可选的芯粒金属化层706。在一些实施例中，芯粒金属化层706形成在衬底704上方，然后去除芯粒金属化层706在芯粒区域702之间的部分。芯粒金属化层706的部分可以通过本领域已知的光刻图案化和蚀刻来去除。在其它实施例中，不使用芯粒金属化层706。
图7C示出了在芯粒金属化层706处固定到衬底705的载体710。在一些情况下，载体710可以通过粘合剂固定或者是其本身就是粘合剂材料。载体710可以是玻璃载体、陶瓷载体、晶圆、框架、板、衬底等。载体710也可以是胶带、膜(例如，管芯附着膜或其它膜)、聚合物等。载体710可以是刚性的或柔性的。
如图7C所示，衬底704的底部也可以薄化。衬底704的薄化可以例如通过蚀刻工艺和/或平坦化工艺(诸如机械研磨工艺或化学机械抛光(CMP)工艺)来实现。如图7C所示，衬底704可以被薄化至芯粒区域702的底表面附近。在一些实施例中，薄化工艺不执行或者在与所示不同的步骤执行。
图7D示出了具有设置在其底表面上的掩模712的衬底704。掩模712已被图案化以在随后的蚀刻步骤期间保护芯粒区域702。掩模712可以是例如光刻胶或硬掩模，并且可以使用任何合适的光刻技术来图案化。
在掩模712已经被图案化之后，蚀刻衬底704的牺牲部分以隔离芯粒区域702。在芯粒区域702之间的示例性牺牲部分716在图7D中被标记。在蚀刻衬底704的牺牲部分之后，隔离的芯粒714保持附着到载体710上。在芯粒714已被隔离后，去除掩模712。图7E示出了附接到载体710的隔离的芯粒714。
类似于上面关于图6A至图6D描述的实施例，可以使用任何合适的湿或干蚀刻技术去除衬底704的牺牲部分。在一些实施例中，可以使用各向异性蚀刻来隔离芯粒714。作为说明性示例，图7E示出了在各向异性蚀刻之后具有对应于(111)硅晶向的约54.74°的角的芯粒714侧壁。然而，在其它实施例中，可以使用各向同性蚀刻，干蚀刻或蚀刻技术的组合来隔离芯粒和使芯粒侧壁成形。
图8A至图8C示出了根据实施例的在衬底802中形成凹槽808的中间步骤。各个凹槽808可以类似于本文之前所述的凹槽(例如，图1A至图1B所示的凹槽108)。图8A示出了示例性衬底802和凹槽区域804。凹槽区域804表示在衬底802内将形成凹槽808的位置。示例性衬底802可以是半导体衬底或如前所述的另一类型的衬底材料。
图8B示出了具有设置在其顶表面上的掩模806的衬底802。掩模806已被图案化以在随后的蚀刻步骤期间保护衬底802的邻近凹槽区域804的部分。掩模806可以是例如光刻胶或硬掩模，并且可以使用任何合适的光刻技术来图案化。
图8C示出了在凹槽区域804已经被蚀刻以形成凹槽808之后的衬底802。凹槽区域804可以使用任何合适的湿或干蚀刻技术去除，包括类似于上面所描述的芯粒隔离蚀刻的蚀刻技术。在一些实施例中，可以使用各向异性蚀刻来隔离各凹槽区域804。例如，可以使用KOH或另一种各向异性蚀刻剂来蚀刻硅衬底中的凹槽区域804。例如，图8C示出了在各向异性蚀刻之后具有对应于(111)硅晶向的约54.74°的角的凹槽808侧壁。然而，在其它实施例中，可以使用各向同性蚀刻、干蚀刻或蚀刻技术的组合来形成凹槽和使凹槽侧壁成形。
在一些情况下，可以通过类似的各向异性蚀刻形成芯粒和相应的凹槽，因此具有相同侧壁角的平面侧壁。例如，芯粒和衬底都可以是硅，并且都使用类似的各向异性蚀刻剂进行蚀刻，使得芯粒和凹槽都可以具有约54.74°的侧壁角。使用类似技术形成芯粒侧壁和凹槽侧壁可以允许改善芯粒自对准和改善芯粒-衬底接合。在其它情况下，芯粒和衬底可以由不同的材料形成或使用不同的蚀刻剂或技术蚀刻。
图9A至图9D示出了根据实施例的将芯粒902放置到凹槽906中的中间步骤。芯粒902和凹槽906可以类似于本文前面所述的芯粒和凹槽(例如，图1A至图1B所示的芯粒102和凹槽108)。图9A示出了连接到支撑层910的多个芯粒。在一些实施例中，支撑层910可以是类似于图6A至图6D中所述的支撑层610的层，并且在一些实施例中，支撑层910可以是不同类型层、膜或载体。支撑层910由框架912保持，并且支撑层910被定位成使得至少一个芯粒近似地对准在衬底904中的相应凹槽上方。例如，芯粒902大致对齐在凹槽906上方。由于图9A示出了工具900朝向芯粒902向下移动。工具900可以是拾取和放置工具、工具头等，并且可以使用真空抽吸来保持芯粒。在一些实施例中，工具900可以在芯粒放置期间使用反馈力。
在图9B中，工具900已经向下移动，推动芯粒902，使得支撑层910的支撑芯粒902的部分断裂，分离芯粒902。另一芯粒保持附着到支撑层910上。在一些情况下，工具900可以使用真空来保持芯粒902。如图9B所示，芯粒902可以在芯粒902和凹槽906的特定不对准容差内相对于凹槽906不对准。在图9C中，工具900已经将芯粒902移动到凹槽906中。如果芯粒902不对准凹槽906，芯粒902在进入凹槽906时将自动对准凹槽906。在一些情况下，工具900用真空暂时保持芯粒902，并且当芯粒902进入凹槽906时真空被释放。
在图9D中，芯粒902已经完全放置在凹槽906内。由于自对准，放置的芯粒902的不对准可以是约零。在放置芯粒902之后，工具900可以释放其真空并且移动到另一个芯粒以重复放置过程。支撑层910的保留在芯粒902上的部分可以在随后的步骤中通过蚀刻、研磨、CMP或其它技术去除。
图10A至图10D示出了根据实施例的将芯粒902放置到凹槽906中的中间步骤。图10A示出了附接至膜1010的多个芯粒。在一些实施例中，膜1010可以是类似于如图7A至图7E描述的支撑层710的膜、胶带或其它载体，并且在一些实施例中，膜1010可以是不同类型的膜、胶带或载体。膜1010由框架1012保持，并且膜1010被定位成使得至少一个芯粒几乎在衬底904中的相应凹槽上方对齐。例如，芯粒902大致对齐在凹槽906上方。如图10A显示，工具900朝向芯粒902向下移动。
在图10B中，工具900向下移动，推动芯粒902，使得膜1010的支撑芯粒902的部分向下弯曲或向下拉伸。另外的芯粒保持附着在膜1010上。在图10C中，工具900已经将芯粒902移动到凹槽906中，进一步弯曲或拉伸膜1010。如果芯粒902不对准凹槽906，芯粒902将进入凹槽906时自对准凹槽906。
在图10D中，芯粒902已经从膜1010分离，并且工具900已被撤出。在一些情况下，在工具900已经被撤回之前，芯粒902从膜1010上脱离，并且在其它情况下，随着工具900被取出，芯粒902与膜1010分离。在某些情况下，如图10D所示，膜1010的弯曲或拉伸部分朝向其原始位置缩回。在一些情况下，工具900将芯粒902大致或全部地推动至凹槽906，并且在其它情况下，工具900在将芯粒902大致或完全放置在凹槽906内之前退出。一旦与膜1010分离，芯粒902向下移动到凹槽906中，直到其位于凹槽906内。由于自对准，放置的芯粒902的不对准可以为约零。在放置芯粒902之后，工具900可以移动到另一个芯粒以重复放置过程。
图11A至图11D示出了根据实施例的将芯粒902放置到凹槽906中的中间步骤。图11A示出了通过真空保持芯粒902的工具900，工具900已预先拾取芯粒902。工具900被定位成使得芯粒902大致对齐在凹槽906上方。如图11A所示，工具900朝向芯粒902向下移动。在图11B中，工具900已向下移动，将芯粒902推向凹槽906。在图10C中，工具900已将芯粒902部分地移动到凹槽906中。当芯粒902部分地放置在凹槽906，工具900可以释放它的真空并且移动到另一个芯粒以重复放置过程。如果芯粒902不对准凹槽906，芯粒902在进入凹槽906时将自动对准凹槽906。一旦从工具900释放，芯粒902向下移动进入凹槽906，直到芯粒902位于凹槽906内。在图11D中，芯粒902已经完全放置在凹槽906内。由于自对准，所放置的芯粒902的不对准可以是约零。
图12A至图12C示出了根据实施例的集成芯粒制造过程中的中间步骤。图12A示出了集成芯粒晶圆1200的部分。集成芯粒晶圆1200可以类似于本文之前描述的集成芯粒晶圆(例如，图2A至图2C所示的集成芯粒晶圆200)。在图12A中，芯粒1202已经放置在衬底1204上的它们各自的凹槽内。图12A至图12C所示的芯粒1202各自具有芯粒金属化层，并且在图12A中标记示例性芯粒金属化层1212。在其它情况下，全部芯粒或者没有一个芯粒1202可以具有芯粒金属化层。在可选步骤中，调平(leveling)工具头1210按压在芯粒102上以使各芯粒102平整并确保各芯粒102被牢固地放置在它们各自的凹槽内。在一些情况下，调平工具头1210可以压在芯粒金属化层上，或者如果没有芯粒金属化层，则直接按压在芯粒上。调平工具头1210可以单独或同时地调平一组芯粒102，如图12A所示。调平工具头1210可以同时调平分布在整个晶圆、单个管芯、一组管芯或分布在另一个区域或组上的芯粒102。
在图12B中，所有芯粒1202同时接合。如前所述，芯粒1202可以使用直接接合、中间接合材料或如前所述的另一接合技术接合到衬底1204。在一些情况下，中间接合材料在放置芯粒之前在凹槽内沉积。接合工艺可以包括将热工艺(例如烘烤、固化、退火或其它热工艺)应用于整个集成芯粒晶圆1200。在图12C中，RDL 1220形成在芯粒1202和衬底1204上方。
图13A和图13B示出了根据一些实施例的形成接合芯粒结构1300的方面。图13A示出了包括衬底1304、可选介电层1306和芯粒1308的示例性顶部晶圆1302。在一些实施例中，顶部晶圆1302可以是晶圆、芯粒、集成电路管芯、半导体器件、存储器芯片、互连结构、另一种类型的器件等。可选的介电层1306可以是一个或多个介电层、一个或多个金属化层、RDL、互连层、钝化层或其它类型的层。可选的介电层1306可以包括SiO2或另一种类型的氧化物、SiN、聚合物或其他材料的一层或多层。在一些实施例中，顶部晶圆1302包括一个或多个集成芯粒，诸如图2A至图2C或本公开的其它部分所示的集成芯粒晶圆200。
芯粒1308形成在可选的介电层1306的表面上。在一些实施例中，芯粒1308形成在衬底1304的表面上。芯粒1308可以由半导体材料形成或一个或多个介电材料，诸如SiO2、SiN、聚合物或其它介电材料形成。芯粒1308可以包含互连件、接触焊盘、通孔或其它导电部件。芯粒1308可以使用本领域已知的任何合适的方法或制造技术来形成。下面将参照图16A至图16B描述形成芯粒1308的一些实施例。
芯粒1308可以具有与上述其它芯粒(例如芯粒102)相似的尺寸或形状。芯粒1308可以具有平面图中的正方形形状、平面图中的矩形形状、平面图中的十字形状或平面图中的另一种形状。在一些情况下，芯粒1308在平面图中可以具有约0.4μm或更大的长度，诸如约1μm、2μm、10μm、100μm或另一长度。在一些情况下，芯粒1308具有约0.8μm或更大的厚度，诸如约1μm、2μm、10μm、100μm或另一厚度。
在一些实施例中，衬底1304可以是由玻璃、硅(例如，硅晶圆)或另一种半导体材料、氧化硅或其它介电材料、SOI晶圆等制成的晶圆或是其它类型的衬底。在一些实施例中，衬底1304可以由金属、陶瓷材料、塑料或其它聚合物材料、它们的组合等制成。衬底1304可以是器件晶圆、中介片、管芯或集成电路，并且可以包括有源或无源器件、金属化层、钝化层、通孔、它们的组合等。衬底1304也可以是载体、空白载体晶圆、晶舟、框架、封装件等。
图13A还示出了包括衬底1314、介电层1316和凹槽1318的示例性底部晶圆1310。在一些实施例中，底部晶圆1310可以是晶圆、芯片、集成电路管芯、半导体器件、存储器芯片、互连结构、另一种类型的器件等。介电层1316可以包括一个或多个介电层、一个或多个金属化层、RDL、互连层、钝化层或其它类型的层。介电层1316可以包括SiO2、SiN、另一种类型的氧化物、聚合物或另一种材料的一层或多层。在一些实施例中，底部晶圆1310包括一个或多个集成芯粒，诸如图2A至图2C或本公开的其它部分所示的集成芯粒晶圆200。
凹槽1318形成在介电层1316的表面中，并且被成形为容纳芯粒1308。凹槽1318可以完全延伸穿过介电层1316，或者如图13A所示部分延伸穿过介电层1316。可以使用本领域已知的任何合适的方法或制造技术来形成凹槽1318。下面参照图17A至图17B描述形成凹槽1318的一些实施例。在一些实施例中，凹槽1318形成在衬底1314中，而介电层1316的部分或全部不存在。
在一些实施例中，凹槽1318可以具有与本文所述的其它凹槽(诸如图1A所示的凹槽108)类似的尺寸或形状。在一些实施例中，凹槽1318可以具有在平面图中的正方形形状、平面图中的矩形形状、平面图中的十字形状或平面图中的另一形状。在一些实施例中，凹槽1318在平面图中可以具有约0.4μm或更大的长度，诸如约1μm、2μm、10μm、100μm或另一长度。在一些实施例中，凹槽1318具有约0.8μm或更大的深度，诸如约1μm、2μm、10μm、100μm或另一深度。
图13B示出了接合到底部晶圆1310以形成接合的芯粒结构1300的顶部晶圆1302。在接合的芯粒结构1300中，将芯粒1308放置在凹槽1318中。在一些实施例中，凹槽1318的深度大于芯粒1308的厚度，使得在芯粒1308的底表面和凹槽1318的底表面之间存在间隙。以这种方式，可以减小由于芯粒1308的厚度或凹槽1318的深度的变化的影响。在一些实施例中，芯粒1308和凹槽1318可以在放置期间浸入水中以促进自对准，下面将更详细地描述。
在顶部晶圆1302和底部晶圆1310被带到一起使得芯粒1308被放置在凹槽1318内之前，顶部晶圆1302可以接合到底部晶圆1310。在一些实施例中，芯粒1308接合到凹槽1318的侧壁。在一些实施例中，介电层1306接合到介电层1316。在一些实施例中，接合过程是直接接合工艺、混合接合工艺或另一接合工艺。例如，接合工序可以形成SiO-SiO接合、金属-金属接合或其它类型的接合。接合方法可以包括例如表面处理步骤、一次或多次退火、水浸或本领域已知的其它技术。
在一些实施例中，芯粒1308的侧壁1320和凹槽1318的对应侧壁1322可以具有相似的形状或具有相似的轮廓。多于一个芯粒侧壁1320和多于一个的凹槽侧壁1322可以具有相应的形状或轮廓。以这种方式，芯粒侧壁1320和凹槽侧壁1322的一些、大部分或全部区域可以物理接触。例如，在图13A所示的示例性实施例中，芯粒侧壁1320基本上是平面的并且具有θ的角，并且凹槽侧壁1322也基本上是具有θ角的平面。因此，如图13B所示，当芯粒1308被放置在凹槽1318中时，类似倾斜的侧壁允许芯粒侧壁1320的部分与凹槽侧壁1322的部分平行并且物理接触。这与之前讨论的芯粒和凹槽的行为类似，例如图1A至图1B所示。具有类似形状的侧壁可以允许芯粒1308和凹槽1318之间的更多接触表面积，这可以改善芯粒1308和凹槽1318之间的接合。此外，具有相似侧壁还可以使芯粒1308在凹槽1318内的对准改善，并且从而改善了顶部晶圆1302与底部晶圆1310的对准，下面将更详细地描述。
在一些实施例中，芯粒或凹槽的侧壁可以不是如图13A至图13B所示的直的或平面的。芯粒可以具有一个或多个具有基本上恒定的侧壁角的侧壁。在其它实施例中，侧壁的一些或全部可以是弯曲的，侧壁的不同部分可以具有不同的角度，或者侧壁可以具有不规则形状。在一些情况下，芯粒的侧壁或凹槽的侧壁是对称的。在一些情况下，芯粒的不同侧壁可以具有不同的形状，并且凹槽的不同侧壁可以具有不同的形状。
在一些情况下，如本文所述的芯粒1308和凹槽1318可以允许顶部晶圆1302与底部晶圆1310的自对准。如本文所述的芯粒1308和凹槽1318还可以允许顶部晶圆1302和底部晶圆1310减少由于用于将顶部晶圆1302对准底部晶圆1310的对准工具的不精确性而引起的不对准。例如，在图13A中，芯粒侧壁1320朝向芯粒1308的底部向内倾斜，并且图13A所示的凹槽侧壁1322朝向凹槽1318的底部向内倾斜。在顶部晶圆1302对准期间，如果顶部晶圆1302不精确地对准底部晶圆1310，则当芯粒1308向下移动到凹槽1318中时芯粒侧壁1320将撞击凹槽侧壁1322并且抵靠凹槽侧壁1322滑动。芯粒侧壁1320和凹槽侧壁1322的相似的角度在芯粒1308向下移动到凹槽1318中时导致芯粒1308横向移向更加对准的位置。芯粒1308可以向下移动到凹槽1318中，直到顶部晶圆1302(不包括芯粒1308)的底表面接触底部晶圆1310的顶表面。以这种方式，顶部晶圆1302可以与底部晶圆1310自对准。在一些情况下，如果芯粒侧壁1320的至少底部在凹槽侧壁1322的至少顶部上方，则芯粒1308可以自对准。该自对准动作类似于上面关于图1A至图1B所示的实施例所描述的自对准动作。
在图13A至图13B所示的示例中，对准期间的初始不对准δi可以减小到最终不对准δf，其中δi>δf。以这种方式，即使对准容差或对准工具的不精确度大于δf，最终的不对准可以约为δf或更小。在一些实施例中，最终的不对准δf可以是0.1μm、0.2μm、0.5μm、1.0μm或另一个距离。图13C示出了顶部晶圆1302和底部晶圆1310的横截面，其中标记了芯粒1308和凹槽1318的尺寸。图13C中的标记尺寸是可以被控制或定制以配置芯粒1308和凹槽1318的尺寸和形状的示例尺寸。还可以控制未标记的其它尺寸或特性，例如芯粒1308的或凹槽1318的垂直于横截面的长度。在图13C所示的说明性示例中，芯粒1308具有顶部宽度Wc、底部宽度Bc、厚度Tc和侧壁角θc。凹槽1318具有顶部宽度Wr、底部宽度Br、深度Dr和侧壁角θr。在一些实施例中，仍然允许芯粒1308和凹槽1318自对准的芯粒1308和凹槽1318的最大初始不对准δi由δi＝(Wr-Bc)得到。在某些情况下，Bc和Wr可以被配置为使得最大初始不对准δi＝(Wr-Bc)大于或等于对准工具的预期不精确度。以这种方式，尽管由于对准工具而导致预期的不对准，芯粒1308可以能够自对准凹槽1318。在一些实施例中，可以预定最终不对准δf，并且然后可以从δf＝(Wr-Wc)确定Wr和/或Wc，并且可以从δf＝(Br-Bc)确定Br和/或Bc。作为另一说明性示例，如果芯粒1308的Bc、Tc和侧壁角θc是已知的，则可以从表达式Wc＝Bc+2Tc/tan(θc)确定顶部宽度Wc。以这种方式，芯粒1308和凹槽1318可以形成为一定尺寸以适应特定对准工具的、工艺规格、设计限制或其它因素的已知不精确性。
因此，芯粒1308和凹槽1318的自对准行为可以使在初始对准期间对不对准的容差增大和最终不对准减小。对于其它芯粒、凹槽和实施例的不对准容差取决于诸如芯粒侧壁和凹槽侧壁的角度或形状、芯粒的厚度和尺寸以及凹槽的深度和尺寸等因素。较大的不对准容差可以实现更快的对准，因为对准工具可能不需要太多的时间将具有芯粒的衬底精确地对准至具有相应凹槽的衬底。
图14A和图14B示出了根据一些实施例的形成堆叠晶圆结构1400的方面。图14A示出了示例性顶部晶圆将要接合至示例性底部晶圆1410以形成堆叠晶圆结构1400的1402的横截面。顶部晶圆1402包括衬底1404、具有接触焊盘1426的介电层1406和芯粒1408。底部晶圆1410包括衬底1414、具有接触焊盘1428的介电层1416和凹槽1418。顶部晶圆1402或底部晶圆1410可以类似于本文所述的其它晶圆，诸如上面描述的顶部晶圆1302或底部晶圆1310。顶部晶圆1402或底部晶圆1410可以包括图14A至图14B中未示出的层、结构或部件。如图14A至图14B所示的接触焊盘1426和接触焊盘1428是说明性实例，并且在一些实施例中可以分别不完全延伸穿过介电层1406或介电层1416。在一些实施例中，接触焊盘1426或接触焊盘1428可以是RDL、金属化层、通孔、有源或无源器件、中介片或其它导电部件或层的部分或电连接至RDL、金属化层、通孔、有源或无源器件、中介片或其它导电部件或层。芯粒1408或凹槽1418可以类似于之前描述的芯粒1308或凹槽1318。其它实施例包括芯粒1408或凹槽1418的其它数量、形状或布置。
图14B示出了顶部晶圆1402接合到底部晶圆1410以形成堆叠晶圆结构1400的示例性横截面。顶部晶圆1402已经对准到底部晶圆1410，并且芯粒1408已经被放置在它们对应的凹槽1418。芯粒1408和凹槽1418的自对准行为可以在对准期间被使用或者可以不被使用。在一些实施例中，堆叠晶圆结构1400在接合之后被分割。顶部晶圆1402可以使用直接接合、介电接合、金属接合、混合接合或另一接合技术接合到底部晶圆1410。在一些实施例中，介电层1406可以接合到介电层1416。此外，顶部晶圆1402上的接触焊盘1426可以接合到底部晶圆1410上的接触焊盘1428，以在两个晶圆之间形成互连。以这种方式，顶部晶圆1402和底部晶圆1410可以电连接，并且在顶部晶圆1402和底部晶圆1410中或上存在的器件或结构之间形成互连。
图15A和图15B示出了根据一些实施例的形成堆叠晶圆结构1500的方面。图15A示出了示例性顶部晶圆1502要接合到示例性底部晶圆1510以形成堆叠晶圆结构1500的横截面。顶部晶圆1502包括具有接触焊盘1526的介电层1506、导电连接件1530和芯粒1508。底部晶圆1510包括具有接触焊盘1528的介电层1516、导电连接件1532和凹槽1518。顶部晶圆1502或底部晶圆1510可以类似于本文所述的其它晶圆，诸如以上所描述的顶部晶圆1302或底部晶圆1310。顶部晶圆1502或底部晶圆1510可以包括图15A至图15B中未示出的层、结构或部件。
参考图15A至图15B，导电连接件1530形成在接触焊盘1526上，并且导电连接件1532形成在接触焊盘1528上。在一些实施例中，接触焊盘1526或接触焊盘1528可以是凸块下金属(UBM)。导电连接件1530或导电连接件1532可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镍钯浸金技术(ENEPIG)形成的凸块等。导电连接件1530或导电连接件1532可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，导电连接件1530或导电连接件1532通过利用诸如蒸发、电镀、印刷焊料转移、置球等常用的方法初始形成焊料层来形成。一旦已经在结构上形成了焊料层，则可以进行回流以便将材料成形为期望的凸块形状。在另一个实施例中，导电连接件1530或导电连接件1532是通过溅射、印刷、电镀、无电镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，金属盖层(未示出)形成在金属柱导电连接件1530或金属柱导电连接件1532的顶部上。金属盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀法工艺形成。在一些实施例中，存在导电连接件1530或导电连接件1532。
图15B示出了顶部晶圆1502接合到底部晶圆1510以形成堆叠晶圆结构1500的示例性横截面。顶部晶圆1502已经对准到底部晶圆1510，并且芯粒1508已经被放置在它们对应的凹槽1518中。芯粒1508和凹槽1518的自对准行为可以在对准期间使用或可以不被使用。在一些实施例中，堆叠晶圆结构1500在接合之后被分割。顶部晶圆1502的导电连接件1530可以接合到底部晶圆1510的导电连接件1532，以在两个晶圆之间形成互连1534。在一个实施例中，顶部晶圆1502通过回流工艺接合到底部晶圆1510。在该回流工艺期间，导电连接件1530与导电连接件1532和金属化图案106接触，以将顶部晶圆1502物理和电耦合到底部晶圆1510。在一些实施例中，存在导电连接件1530或导电连接件1532并且一个晶圆上的导电连接件接合到相对晶圆的接触焊盘。在一些实施例中，可以在顶部晶圆1502和底部晶圆1510之间并且围绕导电连接件1530、导电连接件1532或芯粒1508形成底部填充物(未示出)。
在图15A至图15B所示的实施例中，芯粒1508的厚度(Tc)大于凹槽1518的深度(Dr)，使得间隙g存在于顶部晶圆1502和底部晶圆之间。间隙g可以从g＝(Tc-Dr)近似地确定。间隙g允许用于导电连接件1530和导电连接件1532回流或接合的空间。在一些情况下，芯粒1508的厚度(Tc)和凹槽1518的深度(Dr)可以被配置为确定间隙g的特定高度。因此，可以调整间隙g的高度，例如，以优化或以其它方式调节导电连接件1530或导电连接件1532的接合的特性。
图16A至图16B示出了根据实施例的形成芯粒1608的中间步骤。单个芯粒1608可以是与之前描述的(例如，图13A至图13C所示的芯粒1308)相同的或者是不同的器件或不同类型的芯粒。图16A示出了示例性衬底1604、具有接触焊盘1626的第一介电层1606和具有芯粒区域1602的第二介电层1610。芯粒区域1602指示将从衬底604形成芯粒1608的位置。示例衬底1604可以是如前所述的半导体衬底、晶圆、集成电路管芯或另一种类型的衬底。第一介电层1606或第二介电层1610可以类似于图13A至图13C所示的介电层1316，或类似于之前描述的其它介电层。在一些实施例中，第二介电层1610是第一介电层1606的部分。
图16B示出了具有设置在其表面上的掩模1612的第二介电层1610。掩模1612已经被图案化以在随后的蚀刻步骤期间保护芯粒区域1602。掩模1612可以是例如光刻胶或硬掩模，并且可以使用任何合适的光刻技术来图案化。在掩模1612已被图案化之后，蚀刻第二介电层1610的牺牲部分以隔离芯粒区域1608。在去除第二介电层1610的牺牲部分之后，可以暴露接触焊盘1626。在蚀刻第二介电层1610的牺牲部分之后，保留隔离的芯粒1608。在芯粒1608已被隔离之后，去除掩模1612。
可以使用任何合适的湿或干蚀刻技术去除第二介电层1610的牺牲部分。例如，可以使用RIE蚀刻或其它等离子体蚀刻工艺来去除第二介电层1610的部分。在其它实施例中，可以使用各向同性蚀刻、干蚀刻或蚀刻技术的组合来分离芯粒和使芯粒侧壁成形，包括形成具有其它角度的芯粒侧壁。例如，可以通过调整等离子体蚀刻工艺的适当参数来控制芯粒侧壁的角度。在一些实施例中，芯粒1608可以作为制造工艺的后段制程(BEOL)阶段的部分形成。
图17A至图17B示出了根据实施例的形成凹槽1718的中间步骤。各个凹槽1718可以类似于本文之前所述的(例如，图13A至图13B所示的凹槽1318)凹槽。图17A示出了示例性衬底1704和具有接触焊盘1728和凹槽区域1702的介电层1706。凹槽区域1702表示在介电层1706中将要形成凹槽1718的位置。示例性衬底1704可以是半导体衬底、晶圆、集成电路管芯或如前所述的其它类型的衬底。介电层1706可以类似于图13A至图13C所示的介电层1316，或类似于之前描述的其它介电层。
图17B示出了具有设置在其表面上的掩模1712的介电层1706。掩模1712已经被图案化以在随后的蚀刻步骤期间保护介电层1706的邻近凹槽区域1702的部分。掩模1712可以是例如光刻胶或硬掩模，并且可以使用任何合适的光刻技术来图案化。掩模1712已经被图案化之后，蚀刻介电层1706的凹槽区域1702以形成凹槽1718。在形成凹槽1718之后，去除掩模1712。
可以使用任何合适的湿或干蚀刻技术去除介电层1706的凹槽区域1702。例如，可以使用RIE蚀刻或其它等离子体蚀刻工艺来去除介电层1706的部分。在其它实施例中，可以使用各向同性蚀刻、干蚀刻或蚀刻技术的组合来形成凹槽和使凹槽侧壁成形，包括形成具有其它角度的凹槽侧壁。例如，可以通过调整等离子体蚀刻工艺的适当参数来控制凹槽侧壁的角度。在一些实施例中，凹槽1718可以作为制造工艺的后段制程(BEOL)阶段的部分形成。可以使用任何合适的湿或干蚀刻技术去除凹槽区域1702，包括与上述用于形成图16B所示的芯粒1608的蚀刻技术类似的蚀刻技术。使用类似技术形成芯粒侧壁和凹槽侧壁可以使芯粒自对准改善和使芯粒衬底接合改善。
图18A和图18B示出了根据一些实施例的形成堆叠晶圆结构1800的方面。图18A示出了示例性顶部晶圆1802要接合到示例性底部晶圆1810以形成堆叠晶圆结构1800的横截面。顶部晶圆1802包括具有接触焊盘1826的顶部介电层1806。顶部晶圆1808布置在顶部介电层1806上，并且顶部介电层1806还包括顶部凹槽1819。底部晶圆1810包括具有接触焊盘1428的底部介电层1416。底部电极1809设置在底部介电层1816上，并且底部介电层1816还包括底部凹槽1818。顶部晶圆1802或底部晶圆1810可以类似于本文所述的其它晶圆，诸如上述晶圆1302或底部晶圆1310。顶部晶圆1802或底部晶圆1810可以包括图18A至图18B中未示出的层、结构或部件。如图18A至图18B所示的接触焊盘1826和接触焊盘1828是示例性实例，并且在一些实施例中，可以分别不完全延伸穿过介电层1806或介电层1816。在一些实施例中，接触焊盘1826或接触焊盘1828可以是RDL、金属化层、通孔、有源或无源器件、中介片或其它导电部件或层的部分或电连接RDL、金属化层、通孔、有源或无源器件、中介片。顶部芯粒1808、底部芯粒1809、顶部凹槽1819或底部凹槽1818可以类似于之前描述的芯粒1308或凹槽1318。其它实施例包括芯粒或凹槽的其它数量、形状或布置。
图18B示出了顶部晶圆1802对准且接合到底部晶圆1810以形成堆叠晶圆结构1800的示例性横截面。顶部芯粒1808已经被放置到底部凹槽1818中，并且底部芯粒1809具有被放置在顶部凹槽1819中。在对准期间，芯粒和凹槽的自对准行为可以被使用或可能不被使用。在一些实施例中，堆叠晶圆结构1800在接合之后被分割。顶部晶圆1802可以使用直接接合、电介质接合、金属接合、混合接合或另一种接合技术接合到底部晶圆1810。在一些实施例中，介电层1806可以接合到电介质1816。此外，顶部晶圆1802上的接触焊盘1826可以接合到底部晶圆1810上的接触焊盘1828，以在两个晶圆之间形成互连。以这种方式，顶部晶圆1802和底部晶圆1810可以电连接并且在顶部晶圆1802和底部晶圆1810中或上存在的器件或结构之间形成互连。
图19A至图19C示出了根据一些实施例的形成堆叠晶圆结构的方面。图19A至图19C分别示出了示例性顶部晶圆1902结合到示例性底部晶圆1910以形成堆叠晶圆结构1900a至1900c的部分的平面图。顶部晶圆1902或底部晶圆1910可以类似于本文所述的其它晶圆，例如之前在图13A至图18A中描述的顶部晶圆或底部晶圆。图19A至图19C还示出了示例性芯粒区域1908，其中芯粒及其相应的凹槽可以位于顶部晶圆1902和/或底部晶圆1910上。芯粒区域1908的芯粒或凹槽可以类似于之前在图13A至图18A中描述的芯粒或凹槽。
图19A示出了具有四个矩形芯粒区域1908的示例性堆叠晶圆结构1900a。在一些情况下，使用矩形芯粒区域1908，特别是使用具有如图19A所示的相对较长尺寸的芯粒区域，可以改善顶部晶圆1902至底部晶圆1910的最终角对准。分离芯粒区域1908还可以改善最终角对准。图19A示出了具有多个芯粒区域1908的布置的堆叠晶圆结构1900b的示例。在一些实施例中，各芯粒区域1908可以被分布以使顶部晶圆1902和/或底部晶圆1910的有源区域最大化。芯粒区域1908例如可以具有不对称分布和/或具有不规则的尺寸或形状。图19C示出了具有十字形芯粒区域1908的示例性堆叠晶圆结构1900c。在一些情况下，芯粒区域1908可以被成形为便于沿多于一个轴线对准，诸如图19C所示的十字形。在一些实施例中，芯粒区域1908可以被成形为诸如环形、T形、H形、散列标记形状的配置，在一个或多个方向上具有多个“分支”，或者以其它构造成形。在一些实施例中，一个或多个芯粒区域1908可以位于划线区域中，这可以帮助保存有源区域。其它实施例包括芯粒或凹槽的其它数量、形状或布置。
本公开的实施例可以实现诸如自对准的优点，从而允许在芯粒放置期间增加的不对准容差以及芯粒放置之后的接近零的不对准。不同类型的多个芯粒可以集成到单个衬底中，包括使用不同工艺技术制成的由不同的半导体制成、具有不同的形状和尺寸或其它不同的性质芯粒。以这种方式，可以实现异质芯粒的整合。接合在一起的集成芯粒管芯可能具有相似的面积，减少了由于面积不匹配造成的面积损失。可以使用BEOL方法在芯粒上方形成金属化层，减少在随后的包装过程中所需的步骤或层的数量。在某些情况下，使用集成芯粒可以减少或消除对封装件中的中介片或TSV的需求。在将芯粒集成到晶圆之前，还可以测试芯粒，使KGD接近100％。本公开的实施例可以实现其它优点，例如自对准，允许在晶圆至晶圆、芯片至晶圆或芯片至芯片对准期间的增加的对准容差和减小的最终不对准。
根据实施例，一种方法包括在第一衬底中形成第一凹槽，其中第一凹槽的开口的第一面积大于第一凹槽的底部的第二面积，并且形成第一器件，其中第一器件的顶端的第三面积大于所述第一器件的底端的第四面积。该方法还包括将第一器件放置在第一凹槽中，其中第一器件的底端面向第一凹槽的底部，并将第一器件的侧壁接合到第一凹槽的侧壁。
在一些实施例中，形成所述第一凹槽包括形成相对于所述第一衬底的顶表面具有基本上恒定的侧壁角度的所述第一凹槽的侧壁，其中，所述第一凹槽的所述侧壁角度基本上不垂直于所述第一衬底的所述顶表面。
在一些实施例中，所述第一器件的所述侧壁相对于所述第一器件的顶表面具有与所述第一凹槽的所述侧壁角度大致相同且基本上恒定的角度。
在一些实施例中，所述侧壁角度为约54.7度。
在一些实施例中，该方法还包括：在所述第一器件上方和在所述第一衬底上方形成再分布层。
在一些实施例中，该方法还包括：在所述第一衬底中形成第二凹槽，并且还包括在所述第二凹槽中放置第二器件。
在一些实施例中，所述第一器件包括第一半导体材料，并且所述第二器件包括与所述第一半导体材料不同的第二半导体材料。
在一些实施例中，将所述第一器件放置在所述第一凹槽中包括沿着所述第一凹槽的侧壁的部分滑动所述第一器件的侧壁的部分，所述第一器件的所述侧壁物理地接触所述第一凹槽的所述侧壁。
在一些实施例中，形成所述第一器件包括去除介电层的设置在第二衬底上的部分。根据另一个实施例，一种方法包括将器件至少部分地插入形成在衬底的顶表面中的凹槽中，其中该器件具有锥形轮廓，并且其中该插入导致器件的横向和朝向衬底的底表面的移位。
在一些实施例中，该方法还包括：将所述半导体器件的所述突出部分的侧壁撞击在所述凹槽的侧壁上。
在一些实施例中，该方法还包括：使所述半导体器件的顶表面相对于所述衬底的所述顶表面平整。
在一些实施例中，该方法还包括：将所述半导体器件接合到所述衬底。
在一些实施例中，所述接合包括在所述半导体器件和所述衬底之间形成直接接合。
在一些实施例中，所述半导体器件的所述突出部分的高度小于所述凹槽的深度。
在一些实施例中，所述半导体器件的所述突出部分包括介电材料。
在一些实施例中，该方法还包括：从支撑膜分离所述半导体器件。
根据另一个实施例，半导体器件包括衬底，该衬底在衬底的顶表面中包括多个凹槽和分别设置在多个凹槽中的多个芯粒，其中多个芯粒接合到衬底。
在一些实施例中，所述多个芯粒的第一芯粒包括与所述多个芯粒中的第二芯粒不同的半导体材料。
在一些实施例中，半导体器件还包括：再分布层，设置在所述多个芯粒和所述衬底上方，其中，所述再分布层电连接到所述多个芯粒。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
在第一衬底中形成第一凹槽，其中，所述第一凹槽的开口的第一面积大于所述第一凹槽的底部的第二面积；
形成第一器件，其中，所述第一器件的顶端的第三面积大于所述第一器件的底端的第四面积；
将所述第一器件放置在所述第一凹槽中，其中，所述第一器件的所述底端面向所述第一凹槽的所述底部，通过所述第一凹槽的侧壁和所述第一器件的侧壁的配合，使得所述第一器件在所述放置期间自对准直至所述第一器件的初始放置不对准在放置后减至零；以及
将所述第一器件的侧壁接合到所述第一凹槽的侧壁；
其中，将所述第一器件放置在所述第一凹槽中之后，所述第一器件的所述底端与所述第一凹槽的所述底部存在间隙。
2.根据权利要求1所述的方法，其中，形成所述第一凹槽包括形成相对于所述第一衬底的顶表面具有恒定的侧壁角度的所述第一凹槽的侧壁，其中，所述第一凹槽的所述侧壁角度不垂直于所述第一衬底的所述顶表面。
3.根据权利要求2所述的方法，其中，所述第一器件的所述侧壁相对于所述第一器件的顶表面具有与所述第一凹槽的所述侧壁角度相同且恒定的角度。
4.根据权利要求2所述的方法，其中，所述侧壁角度为54.7度。
5.根据权利要求1所述的方法，还包括：在所述第一器件上方和在所述第一衬底上方形成再分布层。
6.根据权利要求1所述的方法，还包括：在所述第一衬底中形成第二凹槽，并且还包括在所述第二凹槽中放置第二器件。
7.根据权利要求6所述的方法，其中，所述第一器件包括第一半导体材料，并且所述第二器件包括与所述第一半导体材料不同的第二半导体材料。
8.根据权利要求1所述的方法，其中，将所述第一器件放置在所述第一凹槽中包括沿着所述第一凹槽的侧壁的部分滑动所述第一器件的侧壁的部分，所述第一器件的所述侧壁物理地接触所述第一凹槽的所述侧壁。
9.根据权利要求1所述的方法，其中，形成所述第一器件包括去除介电层的设置在第二衬底上的部分。
10.一种形成半导体器件的方法，包括：
将第一半导体器件和第二半导体器件附接至支撑膜；和
将所述第一半导体器件对准至衬底，所述对准包括：
将所述第一半导体器件的突出部分至少部分地插入至形成在所述衬底的顶表面中的凹槽中，其中，所述第一半导体器件的所述突出部分具有锥形轮廓，并且所述插入导致所述第一半导体器件横向和朝向所述衬底的底表面的移位，其中，当所述第一半导体器件与所述衬底对准时，所述第二半导体器件附接至所述支撑膜并且比所述第一半导体器件更远离所述衬底地布置；
其中，将所述第一半导体器件放置在所述凹槽中之后，所述第一半导体器件的底端与所述凹槽的底部存在间隙。
11.根据权利要求10所述的方法，还包括：将所述第一半导体器件的所述突出部分的侧壁撞击在所述凹槽的侧壁上。
12.根据权利要求10所述的方法，还包括：使所述第一半导体器件的顶表面相对于所述衬底的所述顶表面平整。
13.根据权利要求10所述的方法，还包括：将所述第一半导体器件接合到所述衬底。
14.根据权利要求13所述的方法，其中，所述接合包括在所述第一半导体器件和所述衬底之间形成直接接合。
15.根据权利要求10所述的方法，其中，所述第一半导体器件的所述突出部分的高度小于所述凹槽的深度。
16.根据权利要求10所述的方法，其中，所述第一半导体器件的所述突出部分包括介电材料。
17.根据权利要求10所述的方法，还包括：从支撑膜分离所述第一半导体器件。
18.一种半导体器件，包括：
衬底，包括在所述衬底的顶表面中的多个凹槽；以及
多个芯粒，分别设置在所述多个凹槽中，其中，所述多个芯粒接合到所述衬底；
其中，所述多个芯粒中的至少一个芯粒的底端与所述多个凹槽中的至少一个凹槽的底部存在间隙，并且至少在所述间隙的顶部处，所述至少一个芯粒的侧壁与所述至少一个凹槽的侧壁直接物理接触。
19.根据权利要求18所述的半导体器件，其中，所述多个芯粒的第一芯粒包括与所述多个芯粒中的第二芯粒不同的半导体材料。
20.根据权利要求18所述的半导体器件，还包括：再分布层，设置在所述多个芯粒和所述衬底上方，其中，所述再分布层电连接到所述多个芯粒。
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