CN114072907A - 使用互连装置的连接多芯片 - Google Patents

使用互连装置的连接多芯片 Download PDF

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Publication number
CN114072907A
CN114072907A CN202080044797.9A CN202080044797A CN114072907A CN 114072907 A CN114072907 A CN 114072907A CN 202080044797 A CN202080044797 A CN 202080044797A CN 114072907 A CN114072907 A CN 114072907A
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Prior art keywords
interconnect
chip
region
interconnect region
pitch
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CN202080044797.9A
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J·A·德拉克鲁斯
B·哈巴
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Adeia Semiconductor Technologies LLC
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Invensas LLC
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Publication of CN114072907A publication Critical patent/CN114072907A/zh
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Abstract

本文公开了用于使用互连装置来连接多个芯片的技术。在一些配置中，芯片上的一个或多个互连区可以彼此相邻，使得第一互连区的至少一部分边缘位于与第二互连区的边缘相邻。例如，互连区可以位于芯片的角落处，使得互连区的一个或多个边缘与另一芯片的互连区的一个或多个边缘对齐。包括至少一个互连区的芯片也可以被定位或者使用其他布局(诸如但不限于风轮布局)来直接键合到互连装置。在一些配置中，多于一个互连区可以被包括在芯片上。

Description

使用互连装置的连接多芯片
相关申请
本申请要求于2019年6月19日提交的题为“Connecting Multiple Chips Usingan Interconnect Device”临时美国专利申请序列号62/863,367的优先权权益，其整体通过引用被并入本文中。
背景技术
当今，集成电路(IC)几乎在所有的电子设备中使用。计算机设备、移动电子设备和其他电子设备通过IC的小尺寸和低成本成为可能。为了增加IC的密度，多个IC位于多芯片模块(MCM)上。MCM涉及电子组装件，其中多个IC、半导体管芯和/或其它分立元件通常被集成到统一衬底上。
随着IC技术持续扩展，对存在的互连技术满足芯片制造者对诸如高带宽、低功率、良好散热、可靠性和低成本的要求是越来越困难的。此外，在MCM中将组件中的不同组件进行对准是困难的。
附图说明
图1是描绘了示例性嵌入式管芯作为晶片形式的有源桥的示意图。
图2是描述了互连装置上的芯片的说明性布局的示意图，该芯片包括每一芯片的角落上的互连区。
图3是描绘了其中多个芯片利用互连装置的实施例示意图，该互连装置形成大于掩模版的组合覆盖区(footprint area)。
图4是描绘了互连装置上的芯片的说明性风轮布局的示意图。图5是描绘了包括多个互连区和多个互连装置的芯片的说明性布局的示意图。
图6A至图6B是描述了每个互连装置的多个芯片的说明性工艺流程的示意图。
图7是描绘了说明性2.5D解决方案的示意图。
图8是用于利用互连装置来连接多个芯片的说明性技术的流程图。
具体实施方式
下面的详细描述涉及使用互连装置来连接多芯片(也在本文中称作“管芯”)的技术。通常，管芯是半导体材料块，该半导体材料块包括被配置为执行一个或多个功能的一个或多个电路。互连可以被用于连接和创建在芯片/管芯上的不同电路之间的电连接。互连可以包括信令互连和/或电力互连，该信令互连可以用于电路之间的通信，该电力互连可以用于向不同的电路提供电力。本文中所描述的互连装置提供了在不同管芯之间的电连接，使得连接可以提供高带宽信令。
根据一些配置，管芯可以使用具有与现有技术相比更小的间距的互连区来进行连接。例如，在一些配置中，由互连装置利用的间隙可以非常小(例如，2μm至10μm)。这些间距与现有的技术相比较是更小的，现有技术的间距通常大于50μm。
在一些配置中，相邻的芯片/管芯可以被设置为使得第一芯片的互连区与第二芯片的另一互连区相邻。如本文所使用的，“互连区”是芯片中将被键合到互连装置的部分(例如，“键合区”)的部分。芯片可以包括多于一个互连区，并且(多个)互连区可以位于芯片上的各种位置。在一些配置中，芯片包括在芯片的角落处的互连区。在其他配置中，互连区可以处于芯片上的其他位置。例如，互连区可以邻近于芯片的边缘。在再一些配置中，多于一个互连区可以被包括在芯片上。例如，芯片可以包括在芯片的第一边缘和芯片的第二边缘上的互连区。互连区也可以位于芯片上的其他位置，诸如芯片上的任何位置。
如所简要讨论的，第一互连区可以位于第一芯片的角落，使得当第一互连区位于互连装置上时，第一互连区的一个或多个边缘与第二芯片的第二互连区的一个或多个边缘对齐。根据一些配置，四个芯片使用位于芯片的角落处的互连区来连接到互连装置。包括至少一个互连区的芯片也可以使用其他布局进行设置，诸如但不限于风轮布局。
互连装置用作将多个芯片连接到一起的“桥”(例如，无源或有源)。有源互连装置包括用于增强信号的有源电路，而无源互连装置不包括用于增强信号的有源电路。在一些配置中，互连装置允许芯片的(多个)互连区使用直接键合互连
Figure BDA0003418262990000031
Figure BDA0003418262990000032
技术被键合到互连装置。与倒装芯片连接相比，使用DBI的间距可以小很多，但是与倒装芯片相比，键合对准可能更困难。
Figure BDA0003418262990000033
是允许芯片利用极其精细间距的3D电互连进行键合的低温混合直接键合技术。在一些示例中，DBI对准和键合过程可以在没有使用粘合剂的情况下在室温下执行。
在一些配置中，互连可以被称为“直接键合的原生互连”，该互连是在管芯的原生导体和第二管芯的导体之间直接形成的金属到金属键合，由此舍弃针对标准接口的开销和复杂性的需要。管芯的原生导体是具有对管芯的原始信号或原生信号的电接入的电导体，出于与其他管芯进行接口的目的，在对信号没有显著修改的情况下，在特定管芯的核心功能逻辑级处可操作。在没有放大或修改原生信号的情况下，用于将来自管芯的核心侧的这种原生信号进行传导的原生互连可以提供通过两个或多个跨管芯边界而设置的连续电路，除非需要适应来自不同制造工艺的管芯。从信号的观点，在没有原生信号的修改或原生信号的修改可忽略的情况下，一个管芯的IP核的原生信号经由直接键合的原生互连被直接传递到其他管芯，从而舍弃标准接口和联合施加的输入/输出协议。例如，原生互连(nativeinterconnects)在2019年12月31日发布的题为“Direct-Bonded Native Interconnectsand Active Base Die”的美国专利10,522,352中进行描述，该专利通过引用被整体并入本文，该原生互连可以根据一些配置被利用。
在加工期间，具有嵌入式金属键合焊盘(通常为铜或镍)的介电表面(诸如二氧化硅和碳氮化硅(silicon carbide nitride))可以被抛光，以实现最小的表面粗糙度。同时，金属键合焊盘可以略微中凹或凹陷。可以使用标准化学机械抛光(CMP)工具实现抛光和中凹。在一些示例中，然后可以通过常规等离子体蚀刻工具施加基于氮的化学物质。准备好的芯片然后可以被简单地对准并且被放置在一起，从而在准备好的表面之间自发形成强化学键。
在适度的批量退火后，传导性键合焊盘彼此扩展以利用晶粒生长形成具有跨键合界面的同质金属互连。同时，氧化物之间的化学键合显著加强，在不使用底部填充(under-fill)的情况下确保高可靠性。该过程利用了工业标准的晶片键合设备。混合键合也可以通过允许互连在键合表面处发生来减低针对穿过硅通孔(TSV)的需要，从而提高电学性能。在一些示例中，可以不利用底部填充同时仍提供极好的热学性能、可靠性和气密性。关于上述各种技术和过程的附加细节将在下面参考图1至图8进行呈现。
在下面的详细描述中，参考构成其部分的附图，并且附图以说明的方式示出示例。本文的附图不是按比例绘制的。相同的附图标记在若干附图(在本文中称为“图”)中表示相同的元件。
图1是描述了说明性嵌入式管芯1A、1B、1C、1D、1E、1F、1G和1H作为有源或无源桥的示意图100。如图所示，载体包括用作有源或无源桥(被示出作为实心填充的正方形)的多个管芯1A、1B、1C、1D、1E、1F、1G和1H。在一些配置中，在载体上的器件可以使用一种或多种技术来电耦合。例如，载体上的器件中的一个或多个器件可以经由阵列作为倒装芯片间距处的通路等来连接。通常，倒装芯片连接是一种利用已被沉积在芯片焊盘上的焊料凸块来将半导体器件(诸如IC芯片)与其他电路系统互连的技术。利用该工艺的间距通常是150μm或更大。其他技术也可以被利用以将不同芯片耦合，诸如嵌入式多管芯互连桥(EMIB)，其以布线层使用将一个芯片连接到另一芯片的硅。然而，常规的EMIB无法像DBI那样处理非常精细的间距。如上面简要讨论的，使用本文中所描述的技术，间距可以小于10μm。根据一些示例，管芯可以以晶片或面板形式被嵌入。。
DBI键合可以被利用于集成电路组装件中的精细间距键合，并且可以被应用于将管芯键合到互连区。参见例如美国专利No.7,485,968，其全部内容通过引用并入本文。DBI键合技术也已在晶片到晶片方法中被证明可以降低间距，这些方法在拾取和放置(pick-and-place，P&P)操作(拾取和放置表面安装技术机器，Pick&Place surface-mounttechnology machines)中没有该单独的管芯间距限制。利用DBI技术、凸块下金属化(underbump metalization，UBM)、底部填充和微凸块利用DBI金属化层来代替。管芯级处的键合在室温下开始，然后在低温下进行批量退火。在一些情况下也可以使用
Figure BDA0003418262990000051
直接键合(Ziptronix,Inc.,an Xperi公司,圣何塞,加利福尼亚)。
有源桥外部的区域(包括区域102A、102B、102C、102D、102E、102F、102G和102H(被示出作为单色方形外部的虚线图案区域))形成作为在桥1A、1B、1C、1D、1E、1F、1G和1H周围的中介层(interposer)。填充图案的点表示在管芯上用于信号的穿过贯通孔。区域102A、102B的边缘通常限定了用于将器件分离的切割道。在切割期间，管芯可以被安装在具有粘性衬背上的切割带，该粘性衬背在薄片金属框架上保持管芯。切割带可以具有取决于切割应用的不同特性。在一些示例中，在桥之外的区域中还可以存在再分布图案。
下面的附图示出了用于使用互连装置来连接多个芯片的技术的示例。如下面附图说明，核心级连接可以通过芯片上的互连区延伸到一个或多个其他芯片的一个或多个互连区。这可以导致创建大于单个掩模版的器件。通常，掩模版是使用步进重复系统来将电路图案将电路图案转移到晶片上的光掩模。然而，有时电路需要比可用于步进重复系统中的最大场尺寸更大的面积以用于正确操作。这些电路可以被称作“掩模版受限”。尽管一些即将到来的技术(诸如掩模版的缝合)使创建大于掩模版的电路具有前景，但是这些解决方案可能很昂贵。
图2是描绘了芯片A、B、C和D的说明性布局的示意图200，芯片A、B、C和D包括位于每个芯片的角落的互连区2A、2B、2C和2D，互连区2A、2B、2C和2D被布置在互连装置220上并且耦合到互连装置220。如图所示，互连区2A、2B、2C和2D的放置相对于彼此被相邻布置。虽然互连装置220被图示为在互连区2A、2B、2C和2D之下，但是互连装置220可以在其他配置中位于互连区2A、2B、2C和2D之上。与互连区的对准相比，针对芯片的其他区域的放置容差没有那么严格。
在一些配置中，互连区2A、2B、2C和2D位于芯片A、B、C和D的角落处，使得当位于互连装置上时，一个芯片中还包括互连区的一个角落与包括相邻互连区的一个或多个其他芯片对齐。在当前示例中，芯片A的互连区2A和芯片C的互连区2C处于芯片的底部角落，并且芯片B和芯片D的互连区2B和2D处于芯片的顶部角落。更具体地，互连区2A位于芯片A的右下部分，互连区2B位于芯片B的右上部分，互连区2C位于芯片C的左下部分，并且互连区2D位于芯片D的左上部分。互连区2A、2B、2C和2D均可以使用位于互连区上的互连装置来互连。互连装置220键合到互连区2A、2B、2C和2D中的每个互连区。装置220位于与芯片A、B、C和D所在的平面不同的平面上。
如将在图5中所示(下面所讨论的)，在芯片上可以包括多于一个互连区。在这种情况下，布置互连区可能会更加困难，因为可能存在更严格的容差。在一些配置中，在互连区之外(例如，在图2中所示的实心方块的区域之外)，可以使用电介质通孔或一些其他技术来进行连接。通常，“过孔”是允许在集成电路的不同层之间的传导连接的小开口。许多过孔被称为硅通孔(TSV)，其贯通硅晶片或管芯的垂直层。TSV可以是性能互连技术，用作引线键合和倒装芯片的备选，以创建三维(3D)集成电路。
这些直接贯通可能已经存在于芯片上现有的倒装芯片级间距处。给定芯片上的不同连接可以具有不同的互连特性。例如，贯通连接的尺寸和/或间距可以大于在芯片和互连装置之间制成的连接的尺寸和/或间距。
在一些配置中，键合到互连装置220的芯片可以位于载体(诸如廉价载体)上。在其他示例中，芯片和被键合的互连装置未位于衬底或载体上。通常，满足项目需求的任意载体可以被利用。例如，载体可以被选择，使得载体承受用于氧化物沉积和退火的温度。一些示例材料可以是但不限于塑料、具有蚀刻腔并且被填充有氧化物或其他物质的玻璃、苯并环丁烯(BCB)晶片、在液晶聚合物(LCP)中模制的、其他无机晶片材料(诸如聚酰亚胺(PI)、光敏聚酰亚胺(PBO)等)。
指示符250示出了经放大的透视图，该透视图示出了芯片A，其包括被键合到互连装置220的第一角部的互连区2A。包括互连区2B的芯片B被键合到互连装置220的第二角部。包括互连区2C的芯片C被键合到互连装置220的第三角部。包括互连区2D的芯片D被键合到互连装置220的第四角部。虽然互连装置220被图示在芯片A、B、C和D下方，但是根据一些示例，互连装置220可以被键合到芯片A、B、C和D的顶表面。如上所述，在一些示例中，互连区2A、2B、2C和2D使用DBI技术被键合到互连装置220。在其他示例中，可以使用其他键合技术。如在250中可见，互连装置220可以在不需要衬底的情况下被键合到芯片。
图3是描绘了说明性示例的示意图300，其中多个芯片利用互连装置来创建组合装置，该组合装置形成大于掩模版的组合覆盖区区域。如图所示，每个芯片302A、302B、302C和302D可以接近掩模版的尺寸。在当前示例中，一旦被组装，设备300就相当于多达四个掩模版。使用本文中所描述的技术，装置300可以更小或更大。在一些配置中，可以包括芯片之间的填充。
通过包括互连区，诸如互连区304，即在每个芯片的角落处，核心级连接可以通过一个芯片上的互连区延伸到一个或多个其他芯片的一个或多个互连区。在当前示例中，这导致创建接近4个掩模版的组合装置。
虽然区域304被示出为用于互连区，但是互连区可以在其他位置处，和/或可以不同地形成(例如，矩形、正方形、圆形……)。例如，互连区可以沿着彼此相邻的芯片的边缘，如本文其他图中所示。此外，互连区304可以具有各种尺寸，包括掩模版的尺寸。多个这样的互连区304可以相对于芯片302A、302B等来定位。
图4是描绘了互连装置404上的芯片的风轮布局的示意图400。如图所示，芯片402A、402B、402C和402D是矩形芯片，其中一个芯片的长边在每个布局中相对于另一芯片的短边旋转90度，使得核心布线被包括在掩模拼版(reticule tile)单个角落中(4)。代替如图2所示的将互连区定位在芯片的不同角落上，每个芯片402A、402B、402C和402D包括互连区4，互连区4如其他芯片位于芯片的相同角落处。通过在每次放置中将芯片旋转90度，互连区4彼此对齐。在其他配置中，该技术可以应用于2-管芯、3-管芯、6-管芯或8-管芯配置。例如，在2-管芯格式中，每个管芯具有使用桥的一个边缘。
图5是描绘了包括多个互连区5A和5B以及多个互连装置的芯片502A、502B、502C和502D的布局的示意图500。如图所示，图5示出了多个互连区5A和5B(其可以小于单个互连区)，其可以减小管芯尺寸但是可能更难以定位，因为多个互连区的布置可以利用更高的布局精度。如图所示，单独的芯片502A、502B、502C和502D包括位于芯片不同边缘的第一互连区5A和第二互连区5B。在一些示例中，互连区5A、5B可以是不同的尺寸(例如，互连区5A的尺寸小于互连区5B的尺寸，或一些其他尺寸)。通过在放置期间旋转每个芯片502A、502B、502C和502D，一个芯片的互连区5A与相邻芯片上的互连区5B对准。
图6A和图6B是描绘了每个互连装置的多个芯片的说明性工艺流程600、650的示意图。图1示出了可以使用图6A和图6B的过程而创建的嵌入式管芯的示例。过程600图示了可以用作互连的柱的图案化流程。
如图所示，管芯602包括可以用于高带宽信令的互连区604。在605A所示的示例中，管芯602可以在形成传导柱614之前被放置在载体608上。根据一些示例，载体608是刚性的并且可以在之前或之后被凸起，并且可以具有载体去除后剩余的键合之前的额外金属化/布线，或者能够在载体去除后进行额外的金属化。在一些配置中，可以包括芯片之间的填充。
在其他示例中，例如605B中所示，管芯602可以在形成传导柱614之后放置在载体608上。根据一些配置，代替在载体608上放置管芯602和形成传导柱614，管芯602和传导柱614可以被放置在层616上，诸如再分布层(RDL)层，或经图案化的(多个)金属和介电层，如610A和610B所示。通常，层616可以是包括使管芯的输入/输出(I/O)焊盘在芯片的其他位置中可用的布线的一层或多层(例如，金属)。
在放置管芯602并且在载体608或层616上形成导电柱614之后，它们可以利用低热膨胀系数(CTE)材料(诸如但不限于液晶聚合物(LCP)SiO2、多晶硅(polySi)、金属等)来封装，如620处所示。通常，LCP是一种高性能热塑性材料，具有优异的热机械性能。在625，可以减薄TSV上方的层以暴露柱的顶端，并且在630移除载体608，其示出结构632，包括在未被互连装置占用的区域中的贯通互连。在一些示例中，在键合之前存在于载体上的被图案化的金属和电介质可以保留。
除了说明性的过程之外，还可以利用其他技术。例如，金属化可以被添加到载体上，可以用作对准特征。DBI小芯片可以用于贯通装置，在脱粘后可以具有用于凸块的焊盘。
图6B类似于图6A，但示出了利用预成型的过孔拼块652。在650A中所示的示例中，过孔拼块652可以在放置管芯602之前被预先封装并且被放置在载体608上。在其他示例中，如650B所示，可以在放置过孔拼块652之前将管芯602放置在载体608上。根据一些配置，代替将管芯602和过孔拼块652放置在载体608上，可以将管芯602和过孔拼块652放置在层616上(例如，金属化、图案化、RDL)，如655所示。在将管芯602和过孔拼块652放置在载体608或层616上之后，它们可以利用低热膨胀系数(CTE)材料(诸如但不限于液晶聚合物(LCP)SiO2、多晶硅(polySi)、金属等)来封装，如660所示。在665，过孔拼块652上方的层可以被蚀刻以暴露柱的顶端，并且在670移除载体608，其示出结构672，该结构672包括在未被互连装置占用的区域中的贯通互连。
图7是描绘了说明性2.5D解决方案的示意图700。如图所示，图7描绘了示例高带宽存储器(HBM)710和示例逻辑720。可以使用所图示和描述的技术来将这些器件集成到成本较低的中介层中。随后的凸块可以使用具有热膨胀系数(CTE)材料的间隙填充，热膨胀系数(CTE)材料通常通过封装、蒸发、原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、旋涂、刮涂、压缩模具、转移模具、真空辅助模具等来匹配(例如，<10ppm/℃,<15ppm/℃,…)。此外，可以利用诸如微米柱730的常规互连。如上所述，与其他互连技术相比，互连区712是更精细的间距(例如，诸如2μm至10μm)。
图8是根据本文中所描述的示例的用于利用互连装置来连接多个芯片的说明性技术的流程图。
过程800可以包括：在810，在装置的一个或多个边缘处创建一个或多个互连区。在820，一个或多个互连区的一个或多个边缘与互连装置220对准、定位和键合。如上所述，一个芯片的互连区中的一个或多个互连区与一个或多个其他芯片的一个或多个互连区对准。在830，可以使用载体来为芯片提供支撑。
本文中所描述的逻辑操作(例如，参考图6至8)被多方面地称为操作、结构装置、动作或模块。这些操作、结构装置、动作和模块可以使用不同的技术或程序来实现。还应当理解，与附图所示的并在本文中所描述的相比，可以执行比更多或更少操作。这些操作也可以并行执行，或者以与本文中所描述的那些不同的顺序来执行。
基于前述内容，应当理解，已经描述了用于使用互连装置来连接多个芯片的示例技术。上述主题仅通过说明的方式来提供，不应被解释为限制。此外，所要求保护的主题不限于解决在本公开的任何部分中所指出的任何或所有缺点的实施方式。在不遵循所示出和描述的示例和应用并且不脱离以下权利要求的精神和范围的情况下，可以对这里描述的主题进行各种修改和改变。

Claims (20)

1.一种器件，包括：
互连装置；
第一芯片，包括与所述第一芯片的边缘相邻的第一互连区；以及
第二芯片，包括与所述第二芯片的边缘相邻的第二互连区，
其中所述第一互连区直接键合到所述互连装置的第一部分，并且被设置为与被直接键合到所述互连装置的第二部分的所述第二互连区相邻，使得电连接被创建在所述第一互连区和所述第二互连区之间。
2.根据权利要求1所述的器件，其中所述第一互连区具有小于20微米的间距。
3.根据权利要求1所述的器件，其中所述第一芯片包括第三互连区；以及所述第一互连区位于所述第一芯片的第一边缘，并且所述第三互连区位于所述第一芯片的第二边缘。
4.根据权利要求3所述的器件，还包括第三芯片，所述第三芯片包括与所述第三芯片的边缘相邻的第四互连区，
其中所述第三互连区直接键合到所述互连装置的第三部分，并且被设置为与直接键合到所述互连装置的第四部分的所述第四互连区相邻，使得电连接被创建在所述第三互连区和所述第四互连区之间。
5.根据权利要求1所述的器件，其中所述第一互连区和所述第二互连区具有第一尺寸和第一间距的焊盘，所述器件还包括在所述第一芯片和所述第二芯片上具有第二尺寸和第二间距的焊盘的区域，所述第二尺寸的焊盘大于所述第一尺寸的焊盘，并且所述第二间距大于所述第一间距。
6.根据权利要求5所述的器件，其中所述互连装置被合并在结构中，所述结构包括在未被所述互连装置占用的区域中的贯通互连，所述第二尺寸的焊盘与所述贯通互连耦合。
7.根据权利要求6所述的器件，其中所述结构包括至少一个半导体或电介质区，所述贯通互连包括延伸通过所述半导体或电介质区的过孔。
8.一种器件，包括：
互连装置，包括与第二键合区相邻的第一键合区；
第一芯片，包括具有小于9微米的间距的第一互连区，所述第一互连区键合到所述第一键合区；以及
第二芯片，包括具有小于9微米的间距的第二互连区，所述第二互连区键合到所述第二键合区，其中电连接被创建在所述第一互连区和所述第二互连区之间。
9.根据权利要求8所述的器件，其中所述第一互连区位于所述第一芯片的第一角落，并且所述第二互连区位于所述第二芯片的第二角落。
10.根据权利要求8所述的器件，其中所述第一芯片包括与所述第一芯片的边缘相邻的第三互连区，并且所述第二芯片包括与所述第二芯片的第二边缘相邻的第四互连区。
11.根据权利要求8所述的器件，其中所述第一芯片在所述第一取向上位于所述互连装置上，以及所述第二芯片在第二取向上位于所述互连装置上，所述第二芯片相对于所述第一芯片旋转，使得所述第一互连区与所述第二互连区相邻。
12.根据权利要求8所述的器件，其中所述第一互连区和所述第二互连区具有第一尺寸和第一间距的焊盘，所述器件还包括在所述第一芯片和所述第二芯片上具有第二尺寸和第二间距的焊盘的区域，所述第二尺寸的焊盘大于所述第一尺寸的焊盘，并且所述第二间距大于所述第一间距。
13.根据权利要求12所述的器件，其中所述互连装置被合并在结构中，所述结构包括在未被所述互连装置占用的区域中的贯通互连，所述第二尺寸的焊盘与所述贯通互连耦合。
14.根据权利要求12所述的器件，其中所述电连接包括原生互连。
15.一种方法，包括：
创建第一芯片，所述第一芯片包括与所述第一芯片的第一边缘相邻的第一互连区；以及
创建第二芯片，所述第二芯片包括与所述第二芯片的第二边缘相邻的第二互连区；
将所述第一互连区与互连装置的第一部分直接键合；以及
将所述第二互连区与所述互连装置的第二部分直接键合，使得电连接被创建在所述第一互连区和所述第二互连区之间，其中所述互连装置的所述第一部分与所述互连装置的所述第二部分相邻。
16.根据权利要求15所述的方法，其中创建所述第一芯片包括：创建所述第一互连区以具有小于20微米的间距。
17.根据权利要求15所述的方法，其中创建所述第一芯片包括：在所述第一芯片的第一边缘上设置所述第一互连区，并且在所述第一芯片的第三边缘上设置所述第一芯片的第三互连区。
18.根据权利要求15所述的方法，其中所述第一芯片的创建包括：
创建具有第一尺寸和第一间距的第一焊盘；以及
创建具有第二尺寸和第二间距的第二焊盘，
所述第二尺寸的所述第二焊盘大于所述第一尺寸的所述第一焊盘，并且所述第二间距大于所述第一间距。
19.根据权利要求18所述的方法，还包括：将所述互连装置合并在结构内，所述结构包括在未被所述互连装置占用的区域中的贯通互连，所述第二尺寸的所述第二焊盘与所述贯通互连耦合。
20.根据权利要求19所述的方法，还包括：在所述结构中创建过孔，所述过孔延伸通过至少一个半导体或电介质区域。
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