CN115117033A - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

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Publication number
CN115117033A
CN115117033A CN202210083522.7A CN202210083522A CN115117033A CN 115117033 A CN115117033 A CN 115117033A CN 202210083522 A CN202210083522 A CN 202210083522A CN 115117033 A CN115117033 A CN 115117033A
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Prior art keywords
die
interposer
dielectric layer
integrated circuit
connections
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CN202210083522.7A
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陈宪伟
陈明发
陈英儒
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115117033A publication Critical patent/CN115117033A/zh
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Abstract

形成集成电路封装件的方法包括将第一管芯附接至中介层。该中介层包括位于中介层的顶侧上的第一管芯连接件和第二管芯连接件以及覆盖第一管芯连接件的至少一个侧壁和第二管芯连接件的至少一个侧壁的第一介电层。该第一管芯耦接至第一管芯连接件和第一介电层，并且第二管芯连接件由第一管芯暴露。该方法还包括使第一介电层凹进以暴露第二管芯连接件的至少一个侧壁并将第二管芯附接至中介层，第二管芯耦接至第二管芯连接件。本申请的实施例还涉及集成电路封装件。

Description

集成电路封装件及其形成方法
技术领域
本申请的实施例涉及集成电路封装件及其形成方法。
背景技术
由于集成电路(IC)的发展，半导体工业由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进而经历了持续的快速增长。在大多数情况下，集成密度的这些改进来自最小部件尺寸的反复减小，这允许将更多组件集成到给定区域。
这些集成改进本质上是二维的，因为集成组件占据的区域位于半导体晶圆的表面上。集成电路的密度的增加和对应的区域减小通常已超出将集成电路芯片直接接合至衬底上的能力范围。中介层已被用于将球接触区域从芯片的区域再分布至中介层的更大区域。此外，中介层允许包括多个芯片的三维封装件。还开发了其他封装件以并入有三维方面。
发明内容
本申请的一些实施例提供了一种形成集成电路封装件的方法，包括：将逻辑管芯附接至中介层的顶侧，所述中介层包括位于所述中介层的所述顶侧上的第一管芯连接件和第二管芯连接件以及覆盖所述第一管芯连接件的至少一个侧壁和所述第二管芯连接件的至少一个侧壁的第一介电层，所述逻辑管芯耦接至所述第一管芯连接件和所述第一介电层，所述第二管芯连接件由所述逻辑管芯暴露；使所述第一介电层凹进，所述凹进暴露所述第二管芯连接件的所述至少一个侧壁；以及将存储器件附接至所述中介层的所述顶侧，所述存储器件耦接至所述第二管芯连接件。
本申请的另一些实施例提供了一种形成集成电路封装件的方法，包括：将处理器器件放置在中介层上；在所述处理器器件的第一管芯连接件与所述中介层的第二管芯连接件之间形成金属对金属接合，并在所述处理器器件的第一介电层与所述处理器的第二介电层之间形成电介质对电介质接合；通过去除所述第二介电层的由所述处理器器件暴露的顶部部分来暴露第三管芯连接件的侧壁；将存储器件安装在所述中介层上，所述安装所述存储器件包括使所述第三管芯连接件上的第一导电连接件回流以覆盖所述第三管芯连接件的顶面和暴露的侧壁；以及在所述存储器件与所述中介层之间形成底部填充物。
本申请的又一些实施例提供了一种集成电路封装件，包括：中介层，所述中介层包括：第一介电层；第一管芯连接件，所述第一管芯连接件的侧壁由所述第一介电层覆盖；以及第二管芯连接件，所述第二管芯连接件的顶部部分在所述第一介电层之上延伸，所述第二管芯连接件的顶面与所述第一管芯连接件的顶面共面；逻辑器件，位于所述中介层上，所述逻辑器件包括第三管芯连接件，所述第三管芯连接件通过金属对金属接合来接合至所述第一管芯连接件；以及存储器件，位于所述中介层上，所述存储器件利用导电连接件耦接至所述中介层，所述导电连接件覆盖所述第二管芯连接件的所述顶部部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的集成电路器件的截面图。
图2A至图2F是根据一些实施例的用于形成存储器立方体的工艺期间的中间步骤的截面图。
图3A至图3D是根据一些实施例的用于形成HBM器件的工艺期间的中间步骤的截面图。
图4至图11C是根据一些实施例的用于形成集成电路封装件的工艺期间的中间步骤的截面图。
图12至图14C是根据一些其他实施例的用于形成集成电路封装件的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，两个器件(诸如例如逻辑管芯和存储器件)接合至中介层。在将逻辑管芯接合至中介层上的介电层中的接合焊盘之后，将介电层的剩余暴露部分凹进，以暴露从凹进的介电层延伸的接合焊盘的较大比例的表面区域。这为随后使用例如倒装芯片接合来接合至中介层的存储器件提供更大的接合区域，从而增强接合强度，并增加中介层与存储器件之间的间隙。这种增加的间隙为填充在存储器件与中介层之间的底部填充物提供更大的工艺窗口，从而提高接合的可靠性。可在接合焊盘的暴露表面区域上方形成诸如例如化学镀镍/化学镀钯(ENEP)层的覆盖层，这可减少在存储器件与中介层之间的焊点中形成的金属间化合物(IMC)的量。
图1是根据一些实施例的集成电路器件10的截面图。集成电路器件10可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)单元、静态随机存取存储器(SRAM)单元等)、电源管理管芯(例如，电源管理集成电路(PMIC)单元)、射频(RF))管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或其组合。集成电路器件10形成在晶圆(未示出)中，该晶圆包括不同的器件区。在一些实施例中，多个晶圆将被堆叠以形成晶圆堆叠件，该晶圆堆叠件在后续处理中被分割以形成多个管芯堆叠件。在一些实施例中，晶圆被分割以形成多个集成电路器件10，该等集成电路器件在后续处理中堆叠以形成多个管芯堆叠件。可根据适用的制造工艺来处理集成电路器件10以形成集成电路。例如，集成电路器件10可包括半导体衬底12、互连结构14、导电通孔16、管芯连接件22和介电层24。
半导体衬底12可以是诸如掺杂或非掺杂硅，或绝缘体上半导体(SOI)衬底的有源层。半导体衬底12可包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。也可使用其他衬底，诸如多层或梯度衬底。半导体衬底12具有有源表面(例如，在图1中面向上的表面)，有时被称为正面；以及非有源表面(例如，在图1中面向下的表面)，有时被称为背面。
器件可形成在半导体衬底12的有源表面处。器件可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器等。无源表面可能不含器件。层间电介质(ILD)位于半导体衬底12的有源表面上方。ILD包围并可能覆盖器件。ILD可以包括由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、非掺杂硅酸盐玻璃(USG)等材料形成的一个或多个介电层。
互连结构14在半导体衬底12的有源表面上方。互连结构14将半导体衬底12的有源表面处的器件互连以形成集成电路。互连结构14可通过例如介电层中的金属化图案形成。金属化图案包括形成在一个或多个介电层中的金属线和通孔。互连结构14的金属化图案电耦接至半导体衬底12的有源表面处的器件。
导电通孔16形成为延伸至互连结构14和/或半导体衬底12中。导电通孔16电耦接至互连结构14的金属化图案。作为形成导电通孔16的实例，可通过例如蚀刻、铣削、激光技术、其组合等在互连结构14和/或半导体衬底12中形成凹槽。可在凹槽中形成薄介电材料，诸如通过使用氧化技术。阻挡层18可诸如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合和/或类似方法共形地沉积在开口中。阻挡层18可由氧化物、氮化物或氮氧化物形成，诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、其组合等。导电材料20可沉积在阻挡层18上方和开口中。导电材料20可通过电化学镀工艺、CVD、PVD、其组合等形成。导电材料的实例是铜、钨、铝、银、金、其组合等。通过例如化学机械抛光(CMP)从互连结构14和/或半导体衬底12的表面去除过量的导电材料20和阻挡层18。阻挡层18和导电材料20的剩余部分形成导电通孔16。
在所示出的实施例中，导电通孔16尚未在集成电路器件10的背面处暴露。相反，导电通孔16被掩埋在半导体衬底12中。如下文将更详细讨论，在后续处理中，导电通孔16将在集成电路器件10的背面处暴露。在暴露之后，导电通孔16可被称为贯穿硅通孔或贯穿衬底通孔(TSV)。
管芯连接件22位于集成电路器件10的正面处。管芯连接件22可以是制成至外部连接的导电柱、焊盘等。管芯连接件22在互连结构14中和/或上方。管芯连接件22可由诸如铜、钛、铝等或其组合等的金属形成，并可通过例如镀等形成。
介电层24位于集成电路器件10的正面处。介电层24位于互连结构14中和/或上。介电层24横向密封管芯连接件22，并且介电层24与集成电路器件10的侧壁横向共末端(在工艺变化内)。介电层24可以是诸如氧化硅、PSG、BSG、BPSG等的氧化物；诸如氮化硅等的氮化物；诸如聚苯并噁唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)基聚合物等的聚合物；等或其组合。介电层24可例如通过旋涂、层压、化学气相沉积(CVD)等形成。在一些实施例中，介电层24在管芯连接件22之后形成，并且可掩埋管芯连接件22，使得介电层24的顶面在管芯连接件22的顶面之上。在一些实施例中，管芯连接件22在介电层24之后形成，诸如通过镶嵌工艺，例如单镶嵌、双镶嵌等。在形成之后，管芯连接件22和介电层24可使用例如CMP工艺、回蚀刻工艺等或其组合来平坦化。在平坦化之后，管芯连接件22的顶面与介电层24的顶面共面(在工艺变化内)并且在集成电路器件10的正面处暴露。在另一实施例中，管芯连接件22在介电层24之后形成，诸如通过镀工艺，并且是凸起的连接件(例如，微凸块)，使得管芯连接件22的顶面延伸至介电层24的顶面之上。
图2A至图2F是根据一些实施例的用于形成存储器立方体50的工艺期间的中间步骤的截面图。如下文将更详细地讨论，图2A至图2F示出通过在载体衬底52上堆叠包括第一集成电路器件的多个晶圆来形成存储器立方体50的工艺。第一集成电路器件可各自具有与上面参考图1讨论的集成电路器件10类似的结构，并且在实施例中可以是存储器件。示出在载体衬底52的一个器件区52A中堆叠晶圆以形成存储器立方体50，但应当了解，载体衬底52可具有任何数量的器件区，并且存储器立方体50可形成在每个器件区中。存储器立方体50通过晶圆上晶圆(WoW)堆叠以自上而下(或反向)的方式形成，其中，提供用于存储器立方体50的顶层的晶圆，并且用于存储器的底层的晶圆立方体50随后堆叠在顶晶圆上。晶圆堆叠件被分割以形成多个存储器立方体50。存储器立方体50在形成之后被测试以减少或防止已知坏的存储器立方体50的后续处理。
随后，存储器立方体50可用于形成高带宽存储(HBM)器件。具体地，如下文将更详细地讨论，存储器立方体50可进一步堆叠在第二集成电路器件上以形成HBM器件。第二集成电路器件可具有与上面参考图1讨论的集成电路器件10类似的结构，并且在实施例中可以是逻辑器件。
在图2A中，提供载体衬底52，并且在载体衬底52上形成释放层54。载体衬底52可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底52可以是晶圆，使得可在载体衬底52上同时形成多个存储器立方体50。
释放层54可由聚合物基材料形成，该材料可与载体衬底52一起从将在后续步骤中形成的上面的结构去除。在一些实施例中，释放层54是在加热时失去其粘合属性的环氧基热释放材料，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层54可以是紫外(UV)胶，其在暴露于UV光时其失去粘合属性。释放层54可以液体形式分配并固化，可以是层压到载体衬底52上的层压膜，或者可以是类似物。释放层54的顶面可以是水平的并且可具有高平面度。
晶圆56A堆叠在载体衬底52上。晶圆56A包括多个集成电路器件，诸如器件区52A中的存储器件10A。存储器件10A将在后续处理中被分割以包括在存储器立方体50中。存储器件10A包括半导体衬底12A、互连结构14A、导电通孔16A和介电层24A，但在该处理步骤中不包括介电层24A中的管芯连接件。晶圆56A面朝下堆叠在载体衬底52上，使得介电层24A的主表面面对/接触载体衬底52。如下文将更详细地讨论，存储器立方体50在分割之后附接至另一集成电路器件。可回流连接件用于将存储器立方体50连接至另一集成电路器件。在一些实施例中，管芯连接件可形成在介电层24A中(见下文，图2E)。在晶圆堆叠完成后形成管芯连接件，以防止在晶圆堆叠工艺期间损坏管芯连接件。
在图2B中，晶圆56A被减薄。减薄可通过CMP工艺、研磨工艺、回蚀刻工艺等或其组合进行，并且对半导体衬底12A的非有源表面执行。减薄暴露导电通孔16A。在减薄之后，导电通孔16A的表面与半导体衬底12A的非有源表面是共面的(在工艺变化内)。如此，导电通孔16A在存储器件10A的背面处暴露。
在图2C中，晶圆56B堆叠在载体衬底52上方。具体地，晶圆56B的正面附接至晶圆56A的背面。晶圆56B包括多个集成电路器件，诸如器件区52A中的存储器件10B。存储器件10B将在后续处理中被分割以包括在存储器立方体50中。存储器件10B包括半导体衬底12B、互连结构14B、导电通孔16B、管芯连接件22B和介电层24B。
晶圆56A与晶圆56B背对面接合，例如，通过混合接合以背对面的方式直接接合，使得晶圆56A的背面接合至晶圆56B的正面。具体地，在晶圆56A与晶圆56B之间形成电介质对电介质接合和金属对金属接合。在所示出的实施例中，介电层58和管芯连接件60形成在晶圆56A的背面处并用于混合接合。
介电层58形成在晶圆56A的背面处，诸如半导体衬底12A上。介电层58与集成电路器件10的侧壁横向共末端(在工艺变化内)。介电层58可以是诸如氧化硅、PSG、BSG、BPSG等的氧化物；诸如氮化硅等的氮化物；诸如聚苯并噁唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)基聚合物等的聚合物；等或其组合。介电层58可例如通过旋涂、层压、化学气相沉积(CVD)等形成。在一些实施例中(下面更详细地讨论)，在形成介电层58之前使半导体衬底12A凹进，使得介电层58围绕导电通孔16A。
管芯连接件60形成在晶圆56A的背面处，并与导电通孔16A物理接触。管芯连接件60可以是制成至外部连接的导电柱、焊盘等。管芯连接件60可由诸如铜、铝等的金属形成，并可通过例如镀等形成。管芯连接件60通过导电通孔16A电连接至存储器件10A的集成电路。在形成之后，使用例如CMP工艺、回蚀刻工艺等或其组合来平坦化介电层58和管芯连接件60。在平坦化之后，管芯连接件60的顶面与介电层58的顶面共面(在工艺变化内)并且在晶圆56A的背面处暴露。
介电层58通过电介质对电介质接合而接合至介电层24B，而无需使用任何粘合材料(例如，管芯粘结膜)，且管芯连接件60通过金属对金属接合而接合至管芯连接件22B，而不使用任何共晶材料(例如，焊料)。接合可包括预接合和退火。在预接合期间，施加小的压力以将晶圆56B压靠在晶圆56A上。预接合在低温下进行，诸如室温，诸如15℃至30℃的温度范围内的温度，并且在预接合之后，介电层24B与介电层58彼此接合。然后在后续退火步骤中提高接合强度，其中，介电层24B和介电层58在诸如介于140℃至280℃范围内的温度等高温下退火。在退火之后，形成接合介电层24B与介电层58的接合，诸如熔合接合。例如，接合可以是介电层58的材料与介电层24B的材料之间的共价接合。管芯连接件22B和管芯连接件60以一一对应的方式彼此连接。管芯连接件22B与管芯连接件60可在预接合之后物理接触，或者可在退火期间膨胀以形成物理接触。此外，在退火期间，管芯连接件22B的材料与管芯连接件60的材料(例如，铜)混合，从而也形成金属对金属接合。因此，在晶圆56A与晶圆56B之间产生的接合是混合接合，该混合接合包括电介质对电介质接合和金属对金属接合。
在另一实施例中，省略管芯连接件60。介电层58通过电介质对电介质接合而接合至介电层24B，而无需使用任何粘合材料(例如，管芯粘结膜)，并且导电通孔16A通过金属对金属接合而接合至管芯连接件22B，而不使用任何共晶材料(例如，焊料)。
在又一实施例中，省略介电层58和管芯连接件60。半导体衬底12A可通过电介质对电介质接合而接合至介电层24B，而无需使用任何粘合材料(例如，管芯粘结膜)，并且导电通孔16A可通过金属对金属接合而接合至管芯连接件22B，而不使用任何共晶材料(例如，焊料)。例如，可在半导体衬底12A的非有源表面上形成诸如原生氧化物、热氧化物等的氧化物，并且可将该氧化物用于电介质对电介质接合。
在图2D中，重复上述步骤，使得晶圆56C、56D、56E、56F、56G、56H堆叠在载体衬底52上方。晶圆56C、56D、56E、56F、56G、56H各自包括多个集成电路器件，诸如分别包括器件区52A中的存储器件10C、10D、10E、10F、10G、10H。存储器件10C、10D、10E、10F、10G、10H将在后续处理中被分割以包括在存储器立方体50中。晶圆56C、56D、56E、56F、56G、56H中的每个通过混合接合以背对面的方式分别直接接合至晶圆56B、56C、56D、56E、56F、56G。最后堆叠的晶圆，例如晶圆56H，可不被减薄，使得晶圆56H的导电通孔16H保持电绝缘。
在图2E中，执行载体衬底剥离以将载体衬底52从晶圆堆叠件(例如，晶圆56A)分离(或“脱粘”)。根据一些实施例，脱粘包括将诸如激光或UV光等光投射在释放层54上，以使得释放层54在光的热量下分解，并且可去除载体衬底52。去除载体衬底52暴露存储器立方体50的上部存储器件(例如，存储器件10A)的主表面。然后将晶圆堆叠件翻转并放置在胶带(未示出)上方。
然后，例如在晶圆56A的正面处，形成用于存储器立方体50的顶层的管芯连接件22A。管芯连接件22A用于随后将存储器立方体连接至另一器件，诸如晶圆102(见下文，图3C)。管芯连接件22A可由与如上文关于图2C所述的管芯连接件60类似的材料并通过类似的方法形成。管芯连接件60通过导电通孔16A电连接至存储器件10A的集成电路。在形成之后，使用例如CMP工艺、回蚀刻工艺等或其组合来平坦化介电层24A和管芯连接件22A。在平坦化之后，管芯连接件22A的顶面与介电层24A的顶面共面(在工艺变化内)并且在晶圆56A的正面处暴露。
在图2F中，沿着例如器件区52A与相邻的器件区之间的划线区执行分割工艺。分割可通过锯切、激光切割等进行。可在形成管芯连接件22A之前或之后执行分割工艺。分割将器件区52A与相邻的器件区分离。所得的分割的存储器立方体50来自器件区52A。存储器立方体50的存储器件在分割之后横向共末端(在工艺变化内)。
应当了解，存储器立方体50可包括任何数量的层。在所示出的实施例中，存储器立方体50包括八个层。在另一实施例中，存储器立方体50包括多于或少于八个层，诸如两个层、四个层、十六个层、三十二个层等。
在完成存储器立方体50的形成之后(例如，在形成管芯连接件22A和分割存储器立方体50之后)，通过使用探针62测试所得存储器立方体50。探针62物理和电连接至管芯连接件22A。管芯连接件22A用于测试存储器立方体50，使得仅已知良好的存储器立方体用于进一步处理。测试可包括测试存储器件10A、10B、10C、10D、10E、10F、10G、10H的功能性，或可包括对于已知的开路或短路的可基于存储器件的设计预计的测试。在测试期间，可以以菊花链的方式测试存储器立方体50的所有存储器件。
图3A至图3D是根据一些实施例的用于形成HBM器件100的工艺期间的中间步骤的截面图。如下文将更详细讨论，图3A至图3D示出通过在第二集成电路器件(例如，逻辑器件10L，见图3A)上堆叠存储器立方体50来形成HBM器件100的工艺。第二集成电路器件是裸管芯，该裸管芯可形成在晶圆102中。示出在晶圆102的一个器件区102A中形成HBM器件100，但应当了解，晶圆102可具有任何数量的器件区，并且可在每个器件区中形成HBM器件100。
在图3A中，获得晶圆102。晶圆102包括器件区102A中的逻辑器件10L。逻辑器件10L将在后续处理中被分割以包括在HBM器件100中。逻辑器件10L可以是用于存储器立方体50的存储器件的接口器件、缓冲器件、控制器器件等。在一些实施例中，逻辑器件10L为HBM器件100提供输入/输出(I/O)接口。逻辑器件10L包括半导体衬底12L、互连结构14L、导电通孔16L、管芯连接件22L和介电层24L。
管芯连接件22L用于连接至其他器件，诸如可实现HBM器件100的集成电路封装件中的器件。在一些实施例中，管芯连接件22L是适合与可回流连接件一起使用的导电凸块，诸如延伸穿过介电层24L的微凸块。管芯连接件22A可具有基本垂直的侧壁(在工艺变化内)。在所示出的实施例中，管芯连接件22L形成为穿过介电层24L以耦接互连结构14L的金属化图案。作为形成管芯连接件22L的实例，在介电层24L中形成开口，并且在介电层24L上方和开口中形成晶种层。在一些实施例中，晶种层是金属层，该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可使用例如PVD等来形成晶种层。然后，在晶种层上形成光刻胶并对其图案化。可以通过旋涂等形成光刻胶，并且可以将其暴露于光以用于图案化。光刻胶的图案对应于管芯连接件22L。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可通过诸如电镀或化学镀等的镀形成。导电材料可包括金属，诸如铜、镍、钛、钨、铝等。然后，去除光刻胶和晶种层上未形成导电材料的部分。可通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。在去除光刻胶之后，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻，去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成管芯连接件22L。
在图3B中，晶圆102被减薄。减薄可通过CMP工艺、研磨工艺、回蚀刻工艺等或其组合进行，并且对半导体衬底12L的非有源表面执行。减薄暴露导电通孔16L。在减薄之后，导电通孔16L的表面与半导体衬底12L的非有源表面是共面的(在工艺变化内)。如此，导电通孔16L在逻辑器件10L的背面处暴露。
然后在晶圆102上方，例如在逻辑器件10L的背面处，形成介电层104。介电层104可由与关于图2C描述的介电层58类似的材料并通过类似的方法形成。然后形成延伸穿过介电层104的管芯连接件106。管芯连接件106可由与关于图2E描述的管芯连接件22A类似的材料并通过类似的方法形成。例如，管芯连接件106可以是适合用于使用金属对金属接合而不使用任何共晶材料(例如，焊料)的导电柱、焊盘等。管芯连接件106物理连接至导电通孔16L，并且通过导电通孔16L电连接至逻辑器件10L的集成电路。
在图3C中，存储器立方体50附接至晶圆102，例如，附接至逻辑器件10L的背面。晶圆102与存储器立方体50背对面接合，例如，通过混合接合以背对面的方式直接接合，使得晶圆102的背面接合存储器立方体50的正面。具体地，在晶圆102的介电层104与存储器立方体50的介电层24A之间形成电介质对电介质接合，并且在晶圆102的管芯连接件106与存储器立方体50的管芯连接件22A之间形成金属对金属接合。晶圆102与存储器立方体50的混合接合可使用与上文针对图2C的晶圆56A和晶圆56B的混合接合所描述的类似的方法来执行。
在图3D中，密封剂112形成在各个部件上和周围。在形成之后，密封剂112密封存储器立方体50并与介电层104的顶面和存储器立方体50的每个存储器件接触。密封剂112可以是模塑料、环氧树脂等。密封剂112可通过压缩成型、传递成型等来施加，并且可形成在晶圆102上方使得存储器立方体50被掩埋或覆盖。密封剂112可以液体或半液体形式施加，然后随后固化。可选地对密封剂112执行平坦化工艺以暴露存储器立方体50。在平坦化工艺之后，存储器立方体50的顶面与密封剂112的顶面共面(在工艺变化内)。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如如果存储器立方体50已经暴露，则可省略平坦化。
然后沿着划线区(例如，在器件区102A周围)执行分割工艺。分割可通过锯切、激光切割等进行。分割工艺将器件区102A(包括逻辑器件10L)与相邻器件区分离以形成包括逻辑器件10L的HBM器件100。分割的逻辑器件10L比存储器立方体50的每个存储器件具有更大的宽度。在分割之后，逻辑器件10L与密封剂112横向共末端(在工艺变化内)。
导电连接件114形成在管芯连接件22L上。导电连接件114可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍、化学镀钯浸金(ENEPIG)形成的凸块等。导电连接件114可包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，通过蒸发、电镀、印刷、焊料转印、焊放置等首先形成焊料层来形成导电连接件114。一旦在结构上形成焊料层，就可执行回流以便将材料成形为期望的凸块形状。在另一实施例中，导电连接件114包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可通过镀工艺形成。导电连接件114可在分割工艺之前或之后形成。导电连接件114将用于外部连接(下文进一步讨论)。
提供如图3D所示的示例性电子器件(HBM器件100)仅用于说明目的，以进一步解释所公开实施例的应用，并且不意味着以任何方式限制所公开的实施例。随后，HBM器件100用于形成集成电路封装件。具体地，如下文将更详细地讨论，HBM器件100封装在诸如系统级封装件(SiP)等的三维集成电路(3DIC)封装件中。3DIC封装件的实例包括晶圆上芯片(CoW)封装件、衬底上晶圆上芯片(CoWoS)封装件、集成扇出(InFO)封装件等，尽管应当了解，实施例可应用于其他3DIC封装件。
图4至图11C是根据一些实施例的用于形成集成电路封装件的工艺期间的中间步骤的截面图。如下文将更详细讨论，图4至图10示出将HBM器件100封装至诸如CoW封装件的集成电路封装件300(见图9)中的工艺。然后将集成电路封装件300安装至封装衬底400(见图11A)以形成另一封装件，诸如CoWoS封装件。通过在晶圆302上堆叠HBM器件100和第三集成电路器件来形成集成电路封装件300。第三集成电路器件可具有与上面参考图1讨论的集成电路器件10类似的结构，并且在实施例中可以是逻辑器件或处理器器件。示出在晶圆302的一个封装区302A中形成集成电路封装件，但应当了解，晶圆302可具有任何数量的器件区，并且HBM器件100可堆叠在每个器件区中。
在图4中，获得晶圆302。晶圆302包括封装区302A中的中介层304。中介层304将在后续处理中被分割以包括在集成电路封装件300中。中介层304包括半导体衬底306、互连结构308、导电通孔310、介电层311和管芯连接件312，它们可分别类似于上面参考图1讨论的集成电路器件10的半导体衬底12、互连结构14、导电通孔16、介电层24和管芯连接件22，不同之处在于半导体衬底306可能不含有源/无源器件。管芯连接件312可以是诸如铜、钛、铝等或其组合的金属。管芯连接件312可具有介于1μm至10μm的范围内的间距P1，这可允许与随后附接的逻辑器件的精细间距混合接合(参见下文，图5A)。
在图5A中，诸如处理器器件10P的逻辑管芯附接至晶圆302的正面，例如，附接至中介层304的互连结构308。图5B示出如图5A所示的区500的视图。处理器器件10P可以是处理单元，诸如CPU、GPU、SoC等。在一些实施例中，处理器器件10P包括半导体衬底12P、导电部件20P、半导体衬底12P的正面上的互连结构14P、导电焊盘18P、导电通孔22P、介电层24P和管芯连接件26P。在一些实施例中，处理器器件10P不含TSV。导电部件20P可以是例如连接至半导体衬底12P中的逻辑电路的导电线或其他顶部金属部件。导电焊盘18P可以是例如导电部件20P上的铝焊盘，该铝焊盘可用于通过互连结构14P进行外部连接或用于连接至探针62(参见上文，图2F)以用于进行测试来确定处理器器件10P是否是已知良品管芯。互连结构14P中的导电通孔22P可将导电焊盘18P连接至管芯连接件26P。在一些实施例中，多层导电通孔和/或导电线可通过互连结构14P将导电焊盘18P连接至管芯连接件26P。介电层24P可由与关于图1描述的介电层24类似的材料并通过类似的方法形成。管芯连接件26P可由与上文关于图1描述的管芯连接件22类似的材料(诸如铜、钛、铝等或其组合)并通过类似的方法形成。
处理器器件10P与中介层304面对面接合，例如通过混合接合以面对面的方式直接接合，使得处理器器件10P的正面接合至中介层304的正面。具体地，在介电层24P与介电层311之间形成电介质对电介质接合，并且在管芯连接件26L与管芯连接件312之间形成金属对金属接合。混合接合可通过与上面关于图2C描述的晶圆56A与晶圆56B的接合类似的方法来执行。管芯连接件26L与管芯连接件312之间的金属对金属的接合可以是Cu-Cu接合、Ti-Ti接合、Al-Al接合、Cu-Ti接合、Cu-Al接合、Ti-Al接合或其组合。
图5C示出导电通孔22P直接形成在导电部件20P上的实施例。导电焊盘18P可耦接至其他导电部件20P并可在测试工艺期间用于连接至探针62(参见上文，图2F)以确定处理器器件10P在形成互连结构之前是否是已知良品管芯14P。
在图6A中，介电层311的暴露部分通过自对准工艺凹进，使用附接的处理器器件10P作为用于使介电层311凹进的掩模。使介电层311凹进会暴露管芯连接件312的未附接至处理器器件10P的更大表面区域，并加宽中介层304与随后附接的存储器件(诸如HBM器件100(参见下文，图7A和图7B))之间的间隙，这可提供用于形成焊点和底部填充物的足够的工艺窗口，以增强中介层304与HBM器件100之间的接合强度。作为凹进的实例，可例如使用等离子体蚀刻来使介电层311凹进，该离子蚀刻利用来自包括CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2、He等或其组合的一种或多种蚀刻剂的等离子体。然而，可以可选地、结合地或顺序地使用其他去除方法，诸如使用蚀刻剂诸如HF或H2的湿蚀刻、使用诸如NH3/NF3蚀刻剂的干蚀刻、化学氧化物去除或干化学清洁。通过使用处理器器件10P以覆盖介电层311的用于与处理器器件10P接合的部分，凹进工艺是自对准的。
图6B示出如图6A所示的区1000的视图，该图示出凹进之后的介电层311和管芯连接件312。在一些实施例中，管芯连接件312具有介于5μm至10μm的范围内的高度H1，并且介电层311凹进至管芯连接件312的顶面下方介于5μm至10μm的范围内的高度H2。高度H2介于5μm至10μm的范围内可能有利于暴露管芯连接件312的侧壁的一部分以提高中介层304与随后附接的HBM器件100之间的接合强度。高度H2小于5μm可能无法充分暴露管芯连接件312的侧壁，从而导致中介层304与随后附接的HBM器件100之间的接合强度较差。高度H2大于10μm可能导致过多的管芯连接件312位于介电层311之上，从而增加管芯连接件312与中介层304分离的可能性。
H1与H2之比介于1至3的范围内可能有利于暴露一定比例的管芯连接件312的侧壁，从而提高中介层304与随后附接的HBM器件100之间的接合强度。H1与H2之比小于1可能导致过大比例的管芯连接件312位于介电层311之上，从而增加管芯连接件312与中介层304分离的可能性。H1与H2之比大于3可能暴露过小比例的管芯连接件312的侧壁，从而导致中介层304与随后附接的HBM器件100之间的接合强度较差。
在图7A和图7B中，HBM器件100附接至晶圆302，例如，附接至中介层304的互连结构308。通过利用倒装芯片接合工艺回流导电连接件114，可将HBM器件100附接至晶圆302的管芯连接件312。在一些实施例中，回流的导电连接件114覆盖管芯连接件312的顶面和侧壁并与介电层311的顶面物理接触。使介电层311凹进(参见上文，图6A和图6B)允许导电连接件114覆盖管芯连接件312的更大表面区域，这可增加接合强度。在一些实施例中，如图7C所示，管芯连接件312的下侧壁的相应部分暴露在导电连接件114的相应底面与介电层311的顶面之间。
在图8中，底部填充物316可形成在晶圆302与HBM器件100之间，同时包围导电连接件114。底部填充物316可减少应力并保护产生于可回流连接件114的回流的接头。使介电层311凹进(参见上文，图6A和图6B)允许HBM器件100与中介层304之间有更大的间隙，这可改进底部填充物316的填充工艺并增加接合强度。底部填充物316可在HBM器件100附接之后通过毛细流动工艺形成，或者可在HBM器件100附接之前通过合适的沉积方法形成。底部填充物316的材料可以是液态环氧树脂、可变形凝胶、硅橡胶等或其组合。然而，任何合适的材料都可用于底部填充物316。
在图9中，密封剂318然后形成在各个组件上和周围。在形成之后，密封剂318密封HBM器件100和处理器器件10P，并与底部填充物316接触。密封剂318可由与关于图3D描述的密封剂112类似的材料并通过类似的方法形成。可选地对密封剂318执行平坦化工艺以暴露HBM器件100和/或处理器器件10P。然后将结构翻转并放置在胶带(未示出)上方。
在图10中，晶圆302被减薄。减薄可通过CMP工艺、研磨工艺、回蚀刻工艺等或其组合进行，并且对晶圆302的非有源表面执行。减薄暴露导电通孔310。在减薄之后，导电通孔310的表面与晶圆302的非有源表面是共面的(在工艺变化内)。如此，导电通孔310在中介层304的背面处暴露。
在暴露导电通孔310之后，外部连接件314形成在晶圆302的非有源表面上并连接至导电通孔310。外部连接件314可由与关于图3A描述的管芯连接件22L类似的材料并通过类似的方法形成。导电连接件320形成在外部连接件314上。导电连接件320可由与关于图3D描述的导电连接件114类似的材料并通过类似的方法形成。
接下来，通过沿着例如封装区302A与诸如例如封装区302B的相邻封装区之间的划线区301进行锯切来执行分割工艺。锯切将封装区302A与诸如例如封装区302B的相邻封装区分割。所得的分割的集成电路封装件300分别来自封装区302A和封装区302B。
在图11A中，使用导电连接件320来将诸如来自封装区302A(见上文，图10)的集成电路封装件300安装至封装衬底400。封装衬底400包括衬底核心402和衬底核心402上方的接合焊盘404。衬底芯402可由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可使用复合材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟和其组合等。此外，衬底核心402可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或其组合。在一个可选的实施例中，衬底芯402基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代材料包括双马来酰亚胺三嗪BT树脂或可选地其他PCB材料或薄膜。诸如ABF或其他层压材料的堆积膜可用于衬底芯402。
衬底芯402可包括有源和无源器件(未示出)。诸如晶体管、电容器、电阻器、其组合等广泛多种器件可用于产生用于器件堆叠的设计的结构和功能要求。可使用任何合适方法来形成器件。
衬底芯402还可包括金属化层和通孔(未示出)，其中，接合焊盘404物理和/或电耦接至金属化层和通孔。金属化层可形成在有源和无源器件上方，并且被设计为连接各个器件以形成功能电路。金属化层可由电介质(例如，低k介电材料)与导电材料(例如，铜)的交替层形成，其中，通孔互连导电材料层，并且金属化层可通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底芯402基本上不含有源和无源器件。
在一些实施例中，导电连接件320被回流以将外部连接件314附接至接合焊盘404。导电连接件320将封装衬底400(包括衬底核心402中的金属化层)电耦接和/或物理耦接至集成电路封装件300。在一些实施例中，在衬底核心402上形成阻焊剂。导电连接件320可设置在阻焊剂中的开口中以电和机械耦接至接合焊盘404。阻焊剂可用于保护衬底核心402的区域免受外部损坏。
在一些实施例中，底部填充物406可形成在集成电路封装件300与封装衬底400之间并包围导电连接件320，以减小应力并保护产生于导电连接件320的回流的接头。底部填充物406可在集成电路封装件300附接之后通过毛细流动工艺形成，或者可在集成电路封装件300附接之前通过合适的沉积方法形成。导电连接件320可在它们回流之前具有形成在其上面的环氧树脂助焊剂(未示出)，其中，环氧树脂助焊剂的环氧树脂部分中的至少一些在集成电路封装件300附接至封装衬底400之后保留。此保留的环氧树脂部分可作为底部填充物406。
在一些实施例中，无源器件(例如，表面安装器件(SMD)，未示出)也可附接至集成电路封装件300(例如，外部连接件314)或封装衬底400(例如，接合焊盘404)。例如，无源器件可与导电连接件320接合至集成电路封装件300或封装衬底400的同一表面。无源器件可在将集成电路封装件300安装在封装衬底400上之前附接至集成电路封装件300，或者可在将集成电路封装件300安装至封装衬底400之前或之后附接至封装衬底400。
图11B示出根据一些实施例的如图11A所示的区1000的视图。底部填充物316设置在介电层24L与介电层311之间。导电连接件114耦接至管芯连接件22L的与介电层24L相对的底面并覆盖管芯连接件312的顶面和侧壁。底部填充物316可覆盖导电连接件114的侧壁和管芯连接件22L的侧壁。在一些实施例中，底部填充物316覆盖管芯连接件22L的底面的一部分。在一些实施例中，如图11C所示，管芯连接件312的下侧壁的相应部分被底部填充物316覆盖。
图12至图14C是用于形成集成电路封装件350的工艺期间的中间步骤的截面图。在此实施例中，集成电路封装件350类似于上面参考图7A至图11A描述的集成电路封装件300，其中，相同的参考数字指示使用相同工艺形成的相同元件。集成电路封装件350的实施例及其制造可不同于集成电路封装件300的实施例及其制造，例如，用于将HBM器件100安装在中介层304上的管芯连接件312被覆盖层324覆盖。
图12示出类似于上面图6A中所示的实施例的实施例，在该实施例中在管芯连接件312的暴露表面上形成覆盖层324。覆盖层324可减少在中介层304和后续附接的HBM器件100(见下文，图13A)之间的焊点(诸如导电连接件114)中形成的金属间化合物(IMC)的量，这可降低电阻并提高器件性能。可使用化学镀(E-Less)工艺来形成覆盖层324。作为实例，化学镀工艺可包括化学镍/化学钯(ENEP)工艺、化学镍/化学钯/浸金(ENEPIG)工艺、浸金工艺或其他工艺。例如，也可使用其他化学镀工艺来形成覆盖层324。
在图13A中，HBM器件100附接至晶圆302，例如，附接至中介层304的互连结构308。图13B示出根据一些实施例的如图13A所示的区1002的视图。通过利用倒装芯片接合工艺回流导电连接件114，可将HBM器件100附接至晶圆302的管芯连接件312。在一些实施例中，回流导电连接件114覆盖管芯连接件312的顶面和侧壁上的覆盖层324并与介电层311的顶面物理接触。在一些实施例中，如图13C所示，覆盖层324的相应部分暴露在导电连接件114的相应底面与介电层311的顶面之间。
图14A示出使用导电连接件320来安装在封装衬底400上的集成电路封装件350。使用与用于形成如关于图8至图11A所述的集成电路封装件300类似的方法，集成电路封装件350可由图13A和图13B所示的结构形成。图14B示出根据一些实施例的如图14A所示的区1002的视图。底部填充物316设置在介电层24L与介电层311之间。导电连接件114耦接至管芯连接件22L的与介电层24L相对的底面并覆盖覆盖层324。底部填充物316可覆盖导电连接件114的侧壁和管芯连接件22L的侧壁。在一些实施例中，底部填充物316覆盖管芯连接件22L的底面的一部分。在一些实施例中，如图14C所示，覆盖层324的位于导电连接件114的相应底面与介电层311的顶面之间的相应部分被底部填充物316覆盖。
实施例可实现优点。逻辑管芯接合至中介层上的介电层。然后使介电层的剩余暴露部分凹进，这会暴露从中介层延伸的接合焊盘的侧壁并为随后接合的存储器件提供更大的接合区域。接合焊盘的表面区域增加会增加接合强度并扩大存储器件与中介层之间的间隔。这可通过为存储器件与中介层之间的底部填充物提供更大的工艺窗口来增加接合的可靠性。在一些实施例中，覆盖层形成在接合焊盘的顶面和侧壁上，以减少形成在存储器件与中介层之间的焊点中的金属间化合物(IMC)的量。
根据实施例，方法包括：将逻辑管芯附接至中介层的顶侧，所述中介层包括位于所述中介层的所述顶侧上的第一管芯连接件和第二管芯连接件以及覆盖所述第一管芯连接件的至少一个侧壁和所述第二管芯连接件的至少一个侧壁的第一介电层，所述逻辑管芯耦接至所述第一管芯连接件和所述第一介电层，所述第二管芯连接件由所述逻辑管芯暴露；使所述第一介电层凹进，所述凹进暴露所述第二管芯连接件的所述至少一个侧壁；以及将存储器件附接至所述中介层的所述顶侧，所述存储器件耦接至所述第二管芯连接件。在实施例中，该方法还包括在所述存储器件与所述中介层之间的间隙中形成底部填充物。在实施例中，所述方法还包括：在所述第二管芯连接件的顶面和侧壁上形成覆盖层。在实施例中，形成所述覆盖层包括化学镀镍/化学镀钯工艺。在实施例中，所述方法还包括：用密封剂密封所述存储器件和所述逻辑管芯；以及将所述中介层接合至封装衬底，所述中介层位于所述封装衬底与所述密封剂之间。在实施例中，所述逻辑管芯包括第三管芯连接件和第二介电层，并且其中，将所述逻辑管芯附接至所述中介层的所述顶侧包括所述第一管芯连接件与第三管芯之间的金属对金属接合以及所述第一介电层与所述第二介电层之间的电介质对电介质接合。在实施例中，将所述存储器件附接至所述中介层的顶侧包括倒装芯片接合。
根据另一实施例，方法包括：将处理器器件放置在中介层上；在所述处理器器件的第一管芯连接件与所述中介层的第二管芯连接件之间形成金属对金属接合，并在所述处理器器件的第一介电层与所述处理器的第二介电层之间形成电介质对电介质接合；通过去除所述第二介电层的由所述处理器器件暴露的顶部部分来暴露第三管芯连接件的侧壁；将存储器件安装在所述中介层上，安装所述存储器件包括使所述第三管芯连接件上的第一导电连接件回流以覆盖所述第三管芯连接件的顶面和暴露的侧壁；以及在所述存储器件与所述中介层之间形成底部填充物。在实施例中，所述方法还包括：用密封剂密封所述处理器器件和所述存储器件；形成与所述密封剂相对地位于所述中介层上的多个第二导电连接件；以及将所述处理器器件、所述存储器件与所述中介层的一部分分割以形成集成电路封装件。在实施例中，所述方法还包括在所述第三管芯连接件的暴露的顶面和侧壁上形成覆盖层，所述覆盖层包括镍或钯。在实施例中，所述第三管芯连接件具有第一高度，去除所述第二介电层的所述顶部部分暴露所述第三管芯连接件的具有第二高度的一部分，并且所述第一高度与所述第二高度之比介于1至3的范围内。在实施例中，所述第二高度介于5μm至10μm的范围内。在实施例中，所述金属对金属接合是Cu-Cu接合。在实施例中，所述金属对金属接合是Ti-Ti接合或Al-Al接合。在实施例中，所述金属对金属接合是Cu-Ti接合、Cu-Al接合或Ti-Al接合。
根据又一实施例，集成电路封装件包括：中介层，所述中介层包括：第一介电层；第一管芯连接件，所述第一管芯连接件的侧壁由所述第一介电层覆盖；以及第二管芯连接件，所述第二管芯连接件的顶部部分在所述第一介电层之上延伸，所述第二管芯连接件的顶面与所述第一管芯连接件的顶面共面；逻辑器件，位于所述中介层上，所述逻辑器件包括第三管芯连接件，所述第三管芯连接件通过金属对金属接合来接合至所述第一管芯连接件；以及存储器件，位于所述中介层上，所述存储器件利用导电连接件耦接至所述中介层，所述导电连接件覆盖所述第二管芯连接件的所述顶部部分。在实施例中，所述集成电路封装件还包括位于所述第二管芯连接件的所述顶部部分上方的覆盖层，所述导电连接件覆盖所述覆盖层。在实施例中，所述覆盖层包括镍或钯。在实施例中，所述集成电路封装件还包括设置在所述中介层与所述存储器件之间的底部填充物。在实施例中，所述第一介电层包括：第一部分，所述第一部分接合至所述逻辑器件的第二介电层；以及第二部分，所述第二部分比所述第一部分低5μm至10μm的范围内的高度。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路封装件的方法，包括：
将逻辑管芯附接至中介层的顶侧，所述中介层包括位于所述中介层的所述顶侧上的第一管芯连接件和第二管芯连接件以及覆盖所述第一管芯连接件的至少一个侧壁和所述第二管芯连接件的至少一个侧壁的第一介电层，所述逻辑管芯耦接至所述第一管芯连接件和所述第一介电层，所述第二管芯连接件由所述逻辑管芯暴露；
使所述第一介电层凹进，所述凹进暴露所述第二管芯连接件的所述至少一个侧壁；以及
将存储器件附接至所述中介层的所述顶侧，所述存储器件耦接至所述第二管芯连接件。
2.根据权利要求1所述的方法，还包括在所述存储器件与所述中介层之间的间隙中形成底部填充物。
3.根据权利要求1所述的方法，还包括在所述第二管芯连接件的顶面和侧壁上形成覆盖层。
4.根据权利要求3所述的方法，其中，形成所述覆盖层包括化学镀镍/化学镀钯工艺。
5.根据权利要求1所述的方法，还包括：
用密封剂密封所述存储器件和所述逻辑管芯；以及
将所述中介层接合至封装衬底，所述中介层位于所述封装衬底与所述密封剂之间。
6.根据权利要求1所述的方法，其中，所述逻辑管芯包括第三管芯连接件和第二介电层，并且其中，将所述逻辑管芯附接至所述中介层的所述顶侧包括所述第一管芯连接件与第三管芯之间的金属对金属接合以及所述第一介电层与所述第二介电层之间的电介质对电介质接合。
7.根据权利要求1所述的方法，其中，将所述存储器件附接至所述中介层的顶侧包括倒装芯片接合。
8.一种形成集成电路封装件的方法，包括：
将处理器器件放置在中介层上；
在所述处理器器件的第一管芯连接件与所述中介层的第二管芯连接件之间形成金属对金属接合，并在所述处理器器件的第一介电层与所述处理器的第二介电层之间形成电介质对电介质接合；
通过去除所述第二介电层的由所述处理器器件暴露的顶部部分来暴露第三管芯连接件的侧壁；
将存储器件安装在所述中介层上，所述安装所述存储器件包括使所述第三管芯连接件上的第一导电连接件回流以覆盖所述第三管芯连接件的顶面和暴露的侧壁；以及
在所述存储器件与所述中介层之间形成底部填充物。
9.根据权利要求8所述的方法，还包括：
用密封剂密封所述处理器器件和所述存储器件；
形成与所述密封剂相对地位于所述中介层上的多个第二导电连接件；以及
将所述处理器器件、所述存储器件与所述中介层的一部分分割以形成集成电路封装件。
10.一种集成电路封装件，包括：
中介层，所述中介层包括：
第一介电层；
第一管芯连接件，所述第一管芯连接件的侧壁由所述第一介电层覆盖；以及
第二管芯连接件，所述第二管芯连接件的顶部部分在所述第一介电层之上延伸，所述第二管芯连接件的顶面与所述第一管芯连接件的顶面共面；
逻辑器件，位于所述中介层上，所述逻辑器件包括第三管芯连接件，所述第三管芯连接件通过金属对金属接合来接合至所述第一管芯连接件；以及
存储器件，位于所述中介层上，所述存储器件利用导电连接件耦接至所述中介层，所述导电连接件覆盖所述第二管芯连接件的所述顶部部分。
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