TWI639095B - 製造具有一或更多層的積體電路之方法及相應的積體電路 - Google Patents

製造具有一或更多層的積體電路之方法及相應的積體電路 Download PDF

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Publication number
TWI639095B
TWI639095B TW103116991A TW103116991A TWI639095B TW I639095 B TWI639095 B TW I639095B TW 103116991 A TW103116991 A TW 103116991A TW 103116991 A TW103116991 A TW 103116991A TW I639095 B TWI639095 B TW I639095B
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TW
Taiwan
Prior art keywords
integrated circuit
layout design
layers
changed
circuit
Prior art date
Application number
TW103116991A
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English (en)
Chinese (zh)
Other versions
TW201504832A (zh
Inventor
Gregory Munson Yeric
葉立克格瑞格利莫森
Original Assignee
Arm Limited
Arm股份有限公司
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Publication date
Application filed by Arm Limited, Arm股份有限公司 filed Critical Arm Limited
Publication of TW201504832A publication Critical patent/TW201504832A/zh
Application granted granted Critical
Publication of TWI639095B publication Critical patent/TWI639095B/zh

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70383Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041Photolithographic processes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18Manufacturability analysis or optimisation for manufacturability

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electron Beam Exposure (AREA)
TW103116991A 2013-07-17 2014-05-14 製造具有一或更多層的積體電路之方法及相應的積體電路 TWI639095B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/944,129 2013-07-17
US13/944,129 US9672316B2 (en) 2013-07-17 2013-07-17 Integrated circuit manufacture using direct write lithography

Publications (2)

Publication Number Publication Date
TW201504832A TW201504832A (zh) 2015-02-01
TWI639095B true TWI639095B (zh) 2018-10-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW103116991A TWI639095B (zh) 2013-07-17 2014-05-14 製造具有一或更多層的積體電路之方法及相應的積體電路

Country Status (13)

Country Link
US (2) US9672316B2 (https=)
EP (1) EP3022605B1 (https=)
JP (1) JP2016531424A (https=)
KR (2) KR20160034300A (https=)
CN (1) CN105378565B (https=)
AU (1) AU2014291840B2 (https=)
BR (1) BR112016000222B1 (https=)
CA (1) CA2917723C (https=)
IL (1) IL243151B (https=)
MY (1) MY174370A (https=)
SG (1) SG11201600093PA (https=)
TW (1) TWI639095B (https=)
WO (1) WO2015008021A1 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105939837B (zh) * 2014-01-16 2019-05-10 惠普发展公司,有限责任合伙企业 对用于增材制造系统的切片数据进行处理
JP6896055B2 (ja) 2016-07-19 2021-06-30 エーエスエムエル ネザーランズ ビー.ブイ. リソグラフィステップにおける基板に施されるべきパターンの組み合わせの決定
US10714427B2 (en) 2016-09-08 2020-07-14 Asml Netherlands B.V. Secure chips with serial numbers
NL2019502B1 (en) 2016-09-08 2018-08-31 Mapper Lithography Ip Bv Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
US20180068047A1 (en) 2016-09-08 2018-03-08 Mapper Lithography Ip B.V. Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
US10418324B2 (en) 2016-10-27 2019-09-17 Asml Netherlands B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
EP3821794B1 (en) * 2016-12-16 2023-02-15 St. Jude Medical International Holding S.à r.l. Wireless force sensor
CN116666358A (zh) * 2016-12-23 2023-08-29 Asml荷兰有限公司 具有序列号的安全芯片
WO2018117275A1 (en) 2016-12-23 2018-06-28 Mapper Lithography Ip B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
NL2018368B1 (en) * 2017-02-13 2018-09-04 Mapper Lithography Ip Bv Data generation for fabricating unique chips using a charged particle multi-beamlet lithography system
US10423751B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package floating metal checks
US10423752B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package metal shadowing checks
CN110308621B (zh) * 2019-06-20 2021-09-17 合肥芯碁微电子装备股份有限公司 一种激光直写成像设备内层基板的对准定位方法
US11890678B2 (en) 2021-10-25 2024-02-06 Honeywell Federal Manufacturing & Technologies, Llc Systems and methods for abrasive oxide removal in additive manufacturing processes
CN117192908B (zh) * 2023-08-22 2024-04-09 安徽国芯智能装备有限公司 一种直写式光刻机涨缩一致的补偿方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200705229A (en) 2005-04-04 2007-02-01 Ibm Method of adding fabrication monitors to integrated circuit chips
TW200935265A (en) 2007-10-09 2009-08-16 Dcg Systems Inc Apparatus and method for integrated circuit design for circuit edit

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63274156A (ja) * 1987-05-02 1988-11-11 Hitachi Ltd 半導体集積回路装置の製造方法
US5512397A (en) 1988-05-16 1996-04-30 Leedy; Glenn J. Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits
US5103557A (en) * 1988-05-16 1992-04-14 Leedy Glenn J Making and testing an integrated circuit using high density probe points
US4924589A (en) 1988-05-16 1990-05-15 Leedy Glenn J Method of making and testing an integrated circuit
JPH0338862A (ja) * 1989-07-05 1991-02-19 Ricoh Co Ltd 半導体集積回路装置の電源調節方法
DE69322667D1 (de) * 1992-02-18 1999-02-04 Elm Technology Corp Lithographie nach Bedarf für integrierte Schaltungen
JPH08272480A (ja) * 1995-03-28 1996-10-18 Matsushita Electric Ind Co Ltd 遅延調整手段付き半導体集積回路とその遅延調整方式
US5989752A (en) 1996-05-29 1999-11-23 Chiu; Tzu-Yin Reconfigurable mask
JPH10112504A (ja) * 1996-10-04 1998-04-28 Hitachi Ltd 配線ディレイ調整回路、半導体集積回路、及び配線ディレイ調整方法
US6065113A (en) * 1997-03-07 2000-05-16 Texas Instruments Incorporated Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register
KR100859825B1 (ko) 2000-01-20 2008-09-23 자비탄 세미콘덕터, 인코포레이티드 개별화된 하드웨어
JP3555859B2 (ja) * 2000-03-27 2004-08-18 広島日本電気株式会社 半導体生産システム及び半導体装置の生産方法
US7316934B2 (en) * 2000-12-18 2008-01-08 Zavitan Semiconductors, Inc. Personalized hardware
US20030233630A1 (en) * 2001-12-14 2003-12-18 Torbjorn Sandstrom Methods and systems for process control of corner feature embellishment
AU2003290531A1 (en) 2002-10-21 2004-05-13 Nanoink, Inc. Nanometer-scale engineered structures, methods and apparatus for fabrication thereof, and applications to mask repair, enhancement, and fabrication
US7262070B2 (en) 2003-09-29 2007-08-28 Intel Corporation Method to make a weight compensating/tuning layer on a substrate
KR101258671B1 (ko) * 2004-02-20 2013-04-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법, ic 카드, ic 태그, rfid,트랜스폰더, 지폐, 유가증권, 여권, 전자 기기, 가방 및의류
US6962875B1 (en) * 2004-06-11 2005-11-08 International Business Machines Corporation Variable contact method and structure
WO2006019919A2 (en) 2004-07-21 2006-02-23 Kla-Tencor Technologies Corp. Computer-implemented methods for generating input for a simulation program for generating a simulated image of a reticle
GB0427563D0 (en) 2004-12-16 2005-01-19 Plastic Logic Ltd A method of semiconductor patterning
US7307001B2 (en) 2005-01-05 2007-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer repair method using direct-writing
JP4914589B2 (ja) * 2005-08-26 2012-04-11 三菱電機株式会社 半導体製造装置、半導体製造方法および半導体装置
US20070050738A1 (en) * 2005-08-31 2007-03-01 Dittmann Larry E Customer designed interposer
JP2008011323A (ja) * 2006-06-30 2008-01-17 Matsushita Electric Ind Co Ltd 動作速度検出装置
JP2008171977A (ja) * 2007-01-11 2008-07-24 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造
US20090096351A1 (en) * 2007-10-12 2009-04-16 Cabot Corporation Reflective layers for electronic devices
US20090181172A1 (en) 2007-10-15 2009-07-16 Nanoink, Inc. Lithography of nanoparticle based inks
US8229588B2 (en) 2009-03-03 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for tuning advanced process control parameters
JP5549094B2 (ja) * 2009-03-30 2014-07-16 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2010251468A (ja) * 2009-04-14 2010-11-04 Toshiba Corp 半導体集積回路
JP2011077423A (ja) * 2009-10-01 2011-04-14 Tohoku Univ 半導体集積回路および集積回路製造方法および集積回路設計方法
FR2957193B1 (fr) * 2010-03-03 2012-04-20 Soitec Silicon On Insulator Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante
JP2012137986A (ja) * 2010-12-27 2012-07-19 Renesas Electronics Corp 半導体集積回路のレイアウト設計装置、半導体集積回路のレイアウト設計方法及びプログラム
CN102707581A (zh) 2012-05-31 2012-10-03 合肥芯硕半导体有限公司 一种光刻物镜的畸变补偿方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200705229A (en) 2005-04-04 2007-02-01 Ibm Method of adding fabrication monitors to integrated circuit chips
TW200935265A (en) 2007-10-09 2009-08-16 Dcg Systems Inc Apparatus and method for integrated circuit design for circuit edit

Also Published As

Publication number Publication date
KR102386526B1 (ko) 2022-04-14
CA2917723C (en) 2022-04-19
MY174370A (en) 2020-04-13
EP3022605A1 (en) 2016-05-25
US9672316B2 (en) 2017-06-06
AU2014291840A1 (en) 2016-02-18
WO2015008021A1 (en) 2015-01-22
EP3022605B1 (en) 2020-02-19
US20150026650A1 (en) 2015-01-22
KR20160034300A (ko) 2016-03-29
CN105378565A (zh) 2016-03-02
SG11201600093PA (en) 2016-02-26
IL243151B (en) 2019-03-31
CA2917723A1 (en) 2015-01-22
US10303840B2 (en) 2019-05-28
BR112016000222B1 (pt) 2022-05-17
BR112016000222A2 (https=) 2017-07-25
US20170228493A1 (en) 2017-08-10
JP2016531424A (ja) 2016-10-06
AU2014291840B2 (en) 2018-02-08
TW201504832A (zh) 2015-02-01
CN105378565B (zh) 2018-03-27
KR20210037758A (ko) 2021-04-06

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