KR20160034300A - 직접 기록 리소그래피를 이용한 집적회로 제조 - Google Patents

직접 기록 리소그래피를 이용한 집적회로 제조 Download PDF

Info

Publication number
KR20160034300A
KR20160034300A KR1020167001592A KR20167001592A KR20160034300A KR 20160034300 A KR20160034300 A KR 20160034300A KR 1020167001592 A KR1020167001592 A KR 1020167001592A KR 20167001592 A KR20167001592 A KR 20167001592A KR 20160034300 A KR20160034300 A KR 20160034300A
Authority
KR
South Korea
Prior art keywords
integrated circuit
layout design
direct
layers
modified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020167001592A
Other languages
English (en)
Korean (ko)
Inventor
그레고리 문슨 에릭
Original Assignee
에이알엠 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에이알엠 리미티드 filed Critical 에이알엠 리미티드
Priority to KR1020217009431A priority Critical patent/KR102386526B1/ko
Publication of KR20160034300A publication Critical patent/KR20160034300A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70383—Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G06F17/5081—
    • H01L21/0274—
    • H01L22/14—
    • H01L22/20—
    • H01L27/0203—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electron Beam Exposure (AREA)
KR1020167001592A 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조 Ceased KR20160034300A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020217009431A KR102386526B1 (ko) 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/944,129 2013-07-17
US13/944,129 US9672316B2 (en) 2013-07-17 2013-07-17 Integrated circuit manufacture using direct write lithography
PCT/GB2014/051398 WO2015008021A1 (en) 2013-07-17 2014-05-08 Integrated circuit manufacture using direct write lithography

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020217009431A Division KR102386526B1 (ko) 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조

Publications (1)

Publication Number Publication Date
KR20160034300A true KR20160034300A (ko) 2016-03-29

Family

ID=50736119

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020167001592A Ceased KR20160034300A (ko) 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조
KR1020217009431A Active KR102386526B1 (ko) 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020217009431A Active KR102386526B1 (ko) 2013-07-17 2014-05-08 직접 기록 리소그래피를 이용한 집적회로 제조

Country Status (13)

Country Link
US (2) US9672316B2 (https=)
EP (1) EP3022605B1 (https=)
JP (1) JP2016531424A (https=)
KR (2) KR20160034300A (https=)
CN (1) CN105378565B (https=)
AU (1) AU2014291840B2 (https=)
BR (1) BR112016000222B1 (https=)
CA (1) CA2917723C (https=)
IL (1) IL243151B (https=)
MY (1) MY174370A (https=)
SG (1) SG11201600093PA (https=)
TW (1) TWI639095B (https=)
WO (1) WO2015008021A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190100291A (ko) * 2016-12-23 2019-08-28 에이에스엠엘 네델란즈 비.브이. 일련번호를 갖는 보안 칩
US11004800B2 (en) 2016-09-08 2021-05-11 Asml Netherlands B.V. Secure chips with serial numbers

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105939837B (zh) * 2014-01-16 2019-05-10 惠普发展公司，有限责任合伙企业 对用于增材制造系统的切片数据进行处理
JP6896055B2 (ja) 2016-07-19 2021-06-30 エーエスエムエル ネザーランズ ビー．ブイ． リソグラフィステップにおける基板に施されるべきパターンの組み合わせの決定
NL2019502B1 (en) 2016-09-08 2018-08-31 Mapper Lithography Ip Bv Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
US20180068047A1 (en) 2016-09-08 2018-03-08 Mapper Lithography Ip B.V. Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
US10418324B2 (en) 2016-10-27 2019-09-17 Asml Netherlands B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
EP3821794B1 (en) * 2016-12-16 2023-02-15 St. Jude Medical International Holding S.à r.l. Wireless force sensor
WO2018117275A1 (en) 2016-12-23 2018-06-28 Mapper Lithography Ip B.V. Fabricating unique chips using a charged particle multi-beamlet lithography system
NL2018368B1 (en) * 2017-02-13 2018-09-04 Mapper Lithography Ip Bv Data generation for fabricating unique chips using a charged particle multi-beamlet lithography system
US10423751B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package floating metal checks
US10423752B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package metal shadowing checks
CN110308621B (zh) * 2019-06-20 2021-09-17 合肥芯碁微电子装备股份有限公司 一种激光直写成像设备内层基板的对准定位方法
US11890678B2 (en) 2021-10-25 2024-02-06 Honeywell Federal Manufacturing & Technologies, Llc Systems and methods for abrasive oxide removal in additive manufacturing processes
CN117192908B (zh) * 2023-08-22 2024-04-09 安徽国芯智能装备有限公司 一种直写式光刻机涨缩一致的补偿方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63274156A (ja) * 1987-05-02 1988-11-11 Hitachi Ltd 半導体集積回路装置の製造方法
US5512397A (en) 1988-05-16 1996-04-30 Leedy; Glenn J. Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits
US5103557A (en) * 1988-05-16 1992-04-14 Leedy Glenn J Making and testing an integrated circuit using high density probe points
US4924589A (en) 1988-05-16 1990-05-15 Leedy Glenn J Method of making and testing an integrated circuit
JPH0338862A (ja) * 1989-07-05 1991-02-19 Ricoh Co Ltd 半導体集積回路装置の電源調節方法
DE69322667D1 (de) * 1992-02-18 1999-02-04 Elm Technology Corp Lithographie nach Bedarf für integrierte Schaltungen
JPH08272480A (ja) * 1995-03-28 1996-10-18 Matsushita Electric Ind Co Ltd 遅延調整手段付き半導体集積回路とその遅延調整方式
US5989752A (en) 1996-05-29 1999-11-23 Chiu; Tzu-Yin Reconfigurable mask
JPH10112504A (ja) * 1996-10-04 1998-04-28 Hitachi Ltd 配線ディレイ調整回路、半導体集積回路、及び配線ディレイ調整方法
US6065113A (en) * 1997-03-07 2000-05-16 Texas Instruments Incorporated Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register
KR100859825B1 (ko) 2000-01-20 2008-09-23 자비탄 세미콘덕터, 인코포레이티드 개별화된 하드웨어
JP3555859B2 (ja) * 2000-03-27 2004-08-18 広島日本電気株式会社 半導体生産システム及び半導体装置の生産方法
US7316934B2 (en) * 2000-12-18 2008-01-08 Zavitan Semiconductors, Inc. Personalized hardware
US20030233630A1 (en) * 2001-12-14 2003-12-18 Torbjorn Sandstrom Methods and systems for process control of corner feature embellishment
AU2003290531A1 (en) 2002-10-21 2004-05-13 Nanoink, Inc. Nanometer-scale engineered structures, methods and apparatus for fabrication thereof, and applications to mask repair, enhancement, and fabrication
US7262070B2 (en) 2003-09-29 2007-08-28 Intel Corporation Method to make a weight compensating/tuning layer on a substrate
KR101258671B1 (ko) * 2004-02-20 2013-04-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법, ｉｃ 카드, ｉｃ 태그, ｒｆｉｄ,트랜스폰더, 지폐, 유가증권, 여권, 전자 기기, 가방 및의류
US6962875B1 (en) * 2004-06-11 2005-11-08 International Business Machines Corporation Variable contact method and structure
WO2006019919A2 (en) 2004-07-21 2006-02-23 Kla-Tencor Technologies Corp. Computer-implemented methods for generating input for a simulation program for generating a simulated image of a reticle
GB0427563D0 (en) 2004-12-16 2005-01-19 Plastic Logic Ltd A method of semiconductor patterning
US7307001B2 (en) 2005-01-05 2007-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer repair method using direct-writing
US20080028345A1 (en) 2005-02-25 2008-01-31 Credence Systems Corporation Apparatus and method for integrated circuit design for circuit edit
US7240322B2 (en) 2005-04-04 2007-07-03 International Business Machines Corporation Method of adding fabrication monitors to integrated circuit chips
JP4914589B2 (ja) * 2005-08-26 2012-04-11 三菱電機株式会社 半導体製造装置、半導体製造方法および半導体装置
US20070050738A1 (en) * 2005-08-31 2007-03-01 Dittmann Larry E Customer designed interposer
JP2008011323A (ja) * 2006-06-30 2008-01-17 Matsushita Electric Ind Co Ltd 動作速度検出装置
JP2008171977A (ja) * 2007-01-11 2008-07-24 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造
US20090096351A1 (en) * 2007-10-12 2009-04-16 Cabot Corporation Reflective layers for electronic devices
US20090181172A1 (en) 2007-10-15 2009-07-16 Nanoink, Inc. Lithography of nanoparticle based inks
US8229588B2 (en) 2009-03-03 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for tuning advanced process control parameters
JP5549094B2 (ja) * 2009-03-30 2014-07-16 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2010251468A (ja) * 2009-04-14 2010-11-04 Toshiba Corp 半導体集積回路
JP2011077423A (ja) * 2009-10-01 2011-04-14 Tohoku Univ 半導体集積回路および集積回路製造方法および集積回路設計方法
FR2957193B1 (fr) * 2010-03-03 2012-04-20 Soitec Silicon On Insulator Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante
JP2012137986A (ja) * 2010-12-27 2012-07-19 Renesas Electronics Corp 半導体集積回路のレイアウト設計装置、半導体集積回路のレイアウト設計方法及びプログラム
CN102707581A (zh) 2012-05-31 2012-10-03 合肥芯硕半导体有限公司 一种光刻物镜的畸变补偿方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11004800B2 (en) 2016-09-08 2021-05-11 Asml Netherlands B.V. Secure chips with serial numbers
KR20190100291A (ko) * 2016-12-23 2019-08-28 에이에스엠엘 네델란즈 비.브이. 일련번호를 갖는 보안 칩
KR20210063461A (ko) * 2016-12-23 2021-06-01 에이에스엠엘 네델란즈 비.브이. 일련번호를 갖는 보안 칩

Also Published As

Publication number Publication date
TWI639095B (zh) 2018-10-21
KR102386526B1 (ko) 2022-04-14
CA2917723C (en) 2022-04-19
MY174370A (en) 2020-04-13
EP3022605A1 (en) 2016-05-25
US9672316B2 (en) 2017-06-06
AU2014291840A1 (en) 2016-02-18
WO2015008021A1 (en) 2015-01-22
EP3022605B1 (en) 2020-02-19
US20150026650A1 (en) 2015-01-22
CN105378565A (zh) 2016-03-02
SG11201600093PA (en) 2016-02-26
IL243151B (en) 2019-03-31
CA2917723A1 (en) 2015-01-22
US10303840B2 (en) 2019-05-28
BR112016000222B1 (pt) 2022-05-17
BR112016000222A2 (https=) 2017-07-25
US20170228493A1 (en) 2017-08-10
JP2016531424A (ja) 2016-10-06
AU2014291840B2 (en) 2018-02-08
TW201504832A (zh) 2015-02-01
CN105378565B (zh) 2018-03-27
KR20210037758A (ko) 2021-04-06

Similar Documents

Publication Publication Date Title
KR102386526B1 (ko) 직접 기록 리소그래피를 이용한 집적회로 제조
JP5179042B2 (ja) 集積回路最適化方法（性能向上のためのｏｐｃトリミング）
CN107066681B (zh) 集成电路和制造集成电路的计算机实现方法
KR102723633B1 (ko) 회로 구성요소를 규정하는 표준 셀의 레이아웃을 수정하기 위한 컴퓨터 구현 시스템 및 방법
US20080148218A1 (en) Mask data generation method, mask formation method, pattern formation method
CN106997406A (zh) 布局修正方法及系统
CN105488244B (zh) 用于设计半导体装置的方法和系统
CN103838887A (zh) 冗余金属图案形成方法
JP2009152298A (ja) 半導体集積回路の設計装置及び方法
KR101687458B1 (ko) 최적화된 패턴 밀도 균일성을 위한 패턴 밀도-이상치-처리에 의한 집적 회로의 제조 방법
KR102717096B1 (ko) 집적 회로 및 상기 집적 회로의 제조를 위한 컴퓨터 구현 방법
JP2007311500A (ja) 半導体装置の設計方法及びこれを実行するプログラム
US7091614B2 (en) Integrated circuit design for routing an electrical connection
JP2009182237A (ja) 露光条件設定方法、パターン設計方法及び半導体装置の製造方法
US7315054B1 (en) Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit
US7538428B2 (en) Semiconductor device
KR100731109B1 (ko) 오프 그리드를 방지할 수 있는 반도체 소자의 설계 방법
US8533638B2 (en) Post-optical proximity correction photoresist pattern collapse rule
JP2002110913A (ja) 半導体回路のテスト用設計回路パタン
US8638120B2 (en) Programmable gate array as drivers for data ports of spare latches
US20070096309A1 (en) Semiconductor device, method of forming wiring pattern, and method of generating mask wiring data
JP2003216675A (ja) 半導体集積回路のレイアウト設計方法
JP2002353314A (ja) 半導体集積回路の配線方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T13-X000 Administrative time limit extension granted

St.27 status event code: U-3-3-T10-T13-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T13-X000 Administrative time limit extension granted

St.27 status event code: U-3-3-T10-T13-oth-X000

A107 Divisional application of patent
PA0104 Divisional application for international application

St.27 status event code: A-0-1-A10-A18-div-PA0104

St.27 status event code: A-0-1-A10-A16-div-PA0104

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000