TWI590378B - 形成至少一導電元件之方法,形成半導體結構之方法,形成記憶體單元之方法以及相關之半導體結構 - Google Patents
形成至少一導電元件之方法,形成半導體結構之方法,形成記憶體單元之方法以及相關之半導體結構 Download PDFInfo
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- TWI590378B TWI590378B TW103120618A TW103120618A TWI590378B TW I590378 B TWI590378 B TW I590378B TW 103120618 A TW103120618 A TW 103120618A TW 103120618 A TW103120618 A TW 103120618A TW I590378 B TWI590378 B TW I590378B
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- silver
- conductive
- electrode
- forming
- conductive material
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- 239000004065 semiconductor Substances 0.000 title claims description 69
- 238000000034 method Methods 0.000 title description 119
- 239000000463 material Substances 0.000 claims description 240
- 239000004020 conductor Substances 0.000 claims description 113
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- 229910052709 silver Inorganic materials 0.000 claims description 74
- 239000004332 silver Substances 0.000 claims description 74
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- 229910052697 platinum Inorganic materials 0.000 claims description 28
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- 239000010955 niobium Substances 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 1
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- 229910052762 osmium Inorganic materials 0.000 claims 1
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- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H—ELECTRICITY
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53247—Noble-metal alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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Description
本發明之實施例係關於形成半導體裝置之導電元件之方法,且另外係關於包括此等導電元件之半導體結構。
本申請案主張2011年3月17日所申請之「形成至少一導電元件之方法,形成半導體結構之方法,形成記憶體單元之方法以及相關之半導體結構(METHODS OF FORMING AT LEAST ONE CONDUCTIVE ELEMENT,METHODS OF FORMING A SEMICONDUCTOR STRUCTURE,METHODS OF FORMING A MEMORY CELL AND RELATED SEMICONDUCTOR STRUCTURES)」的美國專利申請案第13/050,725號的權利。
積體電路(IC)為數以千計之電子系統中之關鍵組件,大體上包括製造於共同基座或基板上之電組件之互連網路。導電互連件用於電連接諸如電容器或電晶體之半導體裝置,或用於界定諸如電腦記憶體或微處理器之特定IC。導電互連件之品質極大影響了IC之總體可製造性、效能及壽命。因此,用於形成導電互連件之材料日益增強對積體
電路之效能、密度及可靠度之限制的判定。
舉例而言,互連件之電導率對積體電路(IC)之操作速度極為重要。因為鋁(Al)及鋁合金具有低電阻率且容易黏著至層間介電材料(諸如,二氧化矽(SiO2)),所以鋁(Al)及鋁合金已廣泛用作半導體裝置中之互連材料。不幸的是,鋁容易受到腐蝕且對電遷移具有弱抗性,如此便增加因孔隙而形成開路或形成短路的可能性。
為了提高該等導電互連件之效能、可靠度及密度,正研究鋁及鋁合金之替代金屬。為了提高佈線中之電導率,已提議使用銅(Cu)及銅合金來形成導電互連件。然而,銅快速擴散穿過許多習知介電材料而形成不良氧化銅化合物。此外,銅無法良好地黏著至習知介電材料或自身。
銀(Ag)亦被提議作為含鋁導電互連件之替代物且銀(Ag)在用作可程式化記憶體單元之電極(諸如,導電橋式隨機存取記憶體(CBRAM)單元之電極)中之電化學活性材料時日益重要。銀具有極低之電阻率,但歸因於當前可用之沈積技術上之限制,難以在窄的間隙(例如,具有20nm或20nm以下之尺寸之間隙)中沈積。儘管可藉由濺鍍(物理)沈積技術來沈積銀,但此等技術並不適用於以銀填充窄的間隙。此外,歸因於在升高之溫度下之黏著問題及聚結,難以由銀形成互連件。因為銀為抗乾式蝕刻製程的,所以用於形成半導體導電元件(例如,互連件及電極)之習知技術不適用於由銀製成此等導電元件。
在一項實施例中,本發明包括形成至少一導電元件之方法。此方法可包括:在包含由一介電材料之側壁界定之至少一開口的一結構上方形成一第一導電材料;在該第一導電材料上方形成包含銀之一第二導電材料;及將該結構退火以形成包含該第一導電材料及該第二導電材料之至少一部分的一材料。
形成該導電元件之方法亦可包括:在包含由一介電材料之側壁界定之至少一開口的一結構之表面上方形成包含銀之一導電材料;在該導電材料上方形成另一導電材料;及執行一拋光製程以實質上將該導電材料及該另一導電材料中之至少一者再分配至該至少一開口之一未填充區域中。
在另一實施例中,本發明包括一種形成一半導體結構之方法。該方法可包括:移除上覆於一基板上之一介電材料之一部分以在該介電材料中形成至少一開口;在該介電材料及該至少一開口之所曝露表面上方形成一第一導電材料;在該材料上方形成包含銀之一第二導電材料;保持該至少一開口之一部分未填充;及執行一拋光製程以實質上填充該至少一開口之該未填充部分。
在又一實施例中,本發明包括一種形成一記憶體單元之方法。該方法包括:在包含上覆於一第一電極上之至少一開口的一結構之表面上方形成一第一導電材料;在該第一導電材料上方形成一記憶體材料;在該材料上方形成包含銀之一第二導電材料;保持該至少一開口之一部分未填充;及執行一製程以實質上以該第一導電材料及該第二導電材料填充該至少一開口。
形成該記憶體單元之方法亦可包括:在由上覆於一第一電極上之至少一開口曝露之一記憶體材料的表面上方形成包含銀之一第一導電材料;在該第一導電材料上方形成一第二導電材料;保持該至少一開口之一部分未填充;及執行一製程以實質上以該第一導電材料及該第二導電材料填充該至少一開口。
在又一實施例中,本發明包括一種半導體結構。該半導體可包括:一導電結構,其上覆於一電極上;硫族化物材料及氧化物材料中之至少一者,其與該導電結構接觸;及一導電材料,其上覆於該硫族化物材料上,該導電材料包含銀及包含另一材料之至少一區域。
在另一實施例中,本發明包括一記憶體單元。該記憶體單元可包括:一記憶體材料,其上覆於一電極上;及一導電材料,其包含銀及另一材料,該導電材料上覆於該記憶體材料上且安置於至少一開口中。
100‧‧‧半導體結構
102‧‧‧基板
104‧‧‧材料
106‧‧‧開口
108‧‧‧電極材料
110‧‧‧襯墊材料
112‧‧‧導電材料
114‧‧‧材料
116‧‧‧未填充區域
120‧‧‧互連件
200‧‧‧半導體結構
202‧‧‧基板
204‧‧‧材料
206‧‧‧開口
208‧‧‧電極材料
210‧‧‧襯墊材料
212‧‧‧導電材料
214‧‧‧材料
216‧‧‧未填充區域
220‧‧‧互連件
300‧‧‧半導體結構
303‧‧‧導電結構
304‧‧‧介電材料
304A‧‧‧材料
304B‧‧‧材料
304C‧‧‧材料
305‧‧‧層間介電材料
306‧‧‧開口
308‧‧‧第一電極
309‧‧‧記憶體材料
310‧‧‧襯墊材料
311‧‧‧第二電極
312‧‧‧導電材料
316‧‧‧未填充區域
330‧‧‧導電橋式隨機存取記憶體(CBRAM)單元
圖1A至圖1E為根據本發明之實施例的半導體結構之部分橫截面圖且說明一種形成互連件之方法;圖2A至圖2E為根據本發明之實施例的半導體結構之部分橫截面圖且說明另一種形成互連件之方法;圖3A為導電橋式隨機存取記憶體(CBRAM)單元之部分橫截面圖;及圖3B1至圖3D為根據本發明之實施例的半導體結構之部分橫截面圖且說明一種形成圖3A中所展示之CBRAM單元之方法。
揭示形成諸如互連件及電極之導電元件之方法,亦揭示形成包括此等導電元件之半導體結構及記憶體裝置之方法。該導電元件係由銀材料(諸如,銀或銀合金)形成。因為銀以及與其他材料形成之合金及混合物具有低的電阻率,所以該導電元件之電阻率可小於或等於由銅形成之導電元件之電阻率。此外,銀合金或銀混合物之使用可實質上減少或消除在包括此等導電元件之半導體處理之稍後階段進行的熱處理動作期間與銀相關聯之聚結之問題。使用銀、銀合金或銀混合物亦可使窄的開口(諸如,具有小於約20nm之至少一尺寸的開口)能夠得以填充。
如本文中所使用,術語「合金」意謂且包括:複數種材料(例如,金屬或非金屬)的均質混合物或固體溶液,該等材料中之一者的若干原子佔用該等材料中之另一者的若干原子之間的填隙位置。以實
例來說明且並非限制,合金可包括銀與選自鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠之一金屬之混合物。
如本文中所使用,術語「混合物」意謂且包括:藉由混合複數種金屬或一金屬與一非金屬而形成之材料。以實例來說明且並非限制,混合物可包括銀與諸如鎢之一金屬的混合物。
如本文中所使用,術語「襯墊」意謂且包括:上覆於至少一材料之一表面上的任何結構。以實例來說明且並非限制,襯墊可包括安置於另一材料上方之一層材料。
如本文中所使用,術語「黏著材料」意謂且包括:經選擇以促進第一材料黏著至緊鄰該第一材料之第二材料之材料。
如本文中所使用,術語「硫族化物」意謂且包括:包括來自元素週期表之第VIA族(亦標識為第16族)之元素的材料(其包括玻璃或結晶材料)。通常稱作「硫族元素」之第VIA族元素包括硫(S)、硒(Se)、碲(Te)、釙(Po)及氧(O)。硫族化物之實例包括(但不限於)硒化鍺(GeSe)、硫化鍺(GeS)、碲化鍺(GeTe)、硒化銦(InSe)及硒化銻(SbSe)。儘管例示性硫族化物具有每一元素一個原子的化學計量,但硫族化物可具有其他化學計量。
如本文中所使用,術語「再分配」意謂且包括:將一材料敷設或塗抹於一表面各處且將其敷設或塗抹至一結構中之部分填充、加襯墊的或先前未填充的開口(例如,貫孔、渠溝)中,從而以該材料填充或實質上填充該開口。
如本文中所使用,術語「基板」意謂且包括:在上面形成其他材料之基底材料或構造。基板可為半導體基板、支撐結構上之基底半導體層、金屬電極或上面形成有一或多個層、結構或區域的半導體基板。基板可為包含一層半導電材料之習知矽基板或另一塊狀基板。如本文中所使用,術語「塊狀基板」意謂並包括:矽晶圓;以及諸如藍
寶石上矽(「SOS」)基板及玻璃上矽(「SOG」)基板之絕緣體上矽(「SOI」)基板;基底半導體基座上之矽磊晶層;及諸如矽鍺、鍺、砷化鎵、氮化鎵及磷化銦之其他半導體或光電子材料。基板可為摻雜的或未摻雜的。
以下描述提供諸如材料類型及處理條件之特定細節以便提供本發明之實施例之透徹描述。然而,一般熟習此項技術者應理解,可在不使用此等特定細節之情況下實踐本發明之實施例。實情為,本發明之實施例可與工業中所使用之習知半導體製造技術一起實踐。此外,下文中所提供之描述不形成用於製造半導體裝置之完整製程流程。下文中所描述之半導體結構未必形成完整半導體裝置。下文僅詳細描述理解本發明之實施例所必需的彼等製程動作及結構。可藉由習知製造技術來執行由半導體結構形成完整半導體裝置之額外動作。
圖1A至圖1E為說明一種形成互連件之方法之實施例的半導體結構100之簡化的部分橫截面圖。參看圖1A,半導體結構100可包括上覆於基板102上之材料104中之開口106。舉例而言,可由氮化矽(Si3N4)、二氧化矽(SiO2)或氮氧化矽(SiOxNy)形成材料104。可使用諸如化學氣相沈積製程、原子層沈積製程或物理氣相沈積製程之習知沈積製程而在基板102上方形成材料104。
半導體結構100可視情況包括在材料104與基板102之間的電極材料108(以虛線展示)。可由諸如鎢(W)、鉑(Pt)、氮化鈦(TiN)或鎳(Ni)之導電材料形成電極材料108。可使用諸如化學氣相沈積製程或原子層沈積製程之習知沈積製程而在基板102上方形成電極材料108。儘管圖1A至圖1E指示存在電極材料108,但應理解,電極材料108為可選的且材料104可在開口106至少部分地延伸穿過材料104的情況下與基板102直接接觸。
可藉由使用例如積體電路製造技術中已知之習知光微影技術(例
如,遮罩及蝕刻)來移除材料104之一部分而形成開口106。以非限制性實例來說明,開口106可縱向延伸至圖1A之平面中。移除材料104之該部分可曝露材料104之一表面或(若存在)電極材料108之一表面。以實例來說明且並非限制,開口106可具有小於約100nm且更特定言之小於約20nm之寬度W1。開口106之縱橫比可介於約1:1與約20:1之間,且更特定言之,介於約5:1與約10:1之間。圖1A及以下圖式中所展示之元件係出於說明之目的而繪製且不應理解為按比例繪製。
參看圖1B,可在半導體結構100之表面(亦即,材料104及(若存在)電極材料108之所曝露表面)上方形成襯墊材料110。舉例而言,可在開口106內曝露之表面(亦即,材料104之所曝露側壁及(若存在)電極材料108之所曝露表面)及材料104之所曝露之、未凹入表面上方形成襯墊材料110。在存在電極材料108之實施例中,可由促進黏著至電極材料108且使電極材料108中之接觸電阻減小或提供兩種特性之材料之形成襯墊材料110。舉例而言,可由鉑(Pt)、鉭(Ta)、鋁(Al)、錫(Sn)、銅(Cu)、銥(Ir)、鈦(Ti)、鎳(Ni)、鈷(Co)、釕(Ru)及銠(Rh)中之至少一者形成襯墊材料110。可使用諸如化學氣相沈積製程、物理氣相沈積製程或濺鍍製程之習知沈積製程來形成襯墊材料110。以實例來說明且並非限制,襯墊材料110可形成有介於約0.5nm與約20nm之間且更特定言之介於約1nm與約5nm之間的厚度。
參看圖1C,可在襯墊材料110上方形成導電材料112。可使用諸如物理氣相沈積製程或物理沈積製程之習知沈積製程而由銀(Ag)或銀(Ag)合金或銀(Ag)混合物形成導電材料112。習知氣相沈積製程(例如,化學氣相沈積及物理氣相沈積)無法有效地在窄的開口(例如,具有小於或等於20nm之至少一尺寸的開口)中沈積銀。因此,在開口106之至少一尺寸(亦即,寬度W1)小於或等於約20nm之實施例中,可使用濺鍍製程以在開口106內形成導電材料112。以非限制性實例來
說明,可實質上在襯墊材料110之整個所曝露表面上方保形地沈積導電材料112。導電材料112可形成有足以至少部分地填充開口106之剩餘部分的厚度。如圖1C中所展示,在半導體結構100上形成導電材料112之後,可保持開口106之一部分未填充(亦即,未填充區域116)。以實例來說明且並非限制,導電材料112可由銀形成且具有介於約5nm與約30nm之間且更特定言之介於約10nm與約20nm之間的厚度。
可基於材料之所要比率來選擇襯墊材料110及導電材料112之厚度。在襯墊材料110包括鉑且導電材料112包括銀之實施例中,襯墊材料110對導電材料112之比率可小於或等於約1至2。
參看圖1D,在襯墊材料110(以虛線展示)包括與導電材料112形成合金之材料的實施例中,可視情況執行一退火製程以形成襯墊材料110與導電材料112之合金。藉由使襯墊材料110及導電材料112反應,而形成金屬間化合物。舉例而言,導電材料112可包括銀,襯墊材料110可包括諸如鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠之至少一材料,該至少一材料與銀反應以形成合金。以實例來說明且並非限制,該退火製程可包括將半導體結構100曝露至介於約100℃與約500℃之間的溫度,且更特定言之,曝露至約200℃之溫度。在該退火製程期間,可在導電材料112與材料104之間的界面處形成包括合金之材料114(以虛線展示),材料104下伏於導電材料112之剩餘(亦即,未合金化)部分下。合金可包括襯墊材料110與導電材料112之實質上均質之混合物或可為包括具有襯墊材料110對導電材料112之不同比率之區域的異質混合物。在襯墊材料110包括鉑且導電材料112包括銀之實施例中,半導體結構100可曝露至約200℃之溫度以使得鉑及銀組合以形成銀-鉑合金。襯墊材料110可至少實質上完全與導電材料112合金化以形成材料114,或襯墊材料110之一部分可保留在材料114與材料104及電極材料108(若存在)之表面之間的界面處。
在襯墊材料110由不與導電材料112形成合金之材料形成的實施例中,可略過退火製程,且襯墊材料110可保留在導電材料112與材料104及(若存在)電極材料108之間的界面處(如圖1C中所展示)。舉例而言,導電材料112可包括銀且襯墊材料110可包含鉭,且鉭可安置於銀與材料104及(若存在)電極材料108之間。
可使半導體結構100之所曝露表面經受材料移除製程,諸如,呈例如化學機械拋光(CMP)製程或機械拋光製程之形式的所謂的拋光製程,從而形成如圖1E中所展示之互連件120。舉例而言,所使用之製程可用於移除襯墊材料110、導電材料112及(若存在)上覆於材料104上之材料114(圖1D)中之每一者之部分。此外,該製程可用於將導電材料112、襯墊材料110及材料114(若存在)中之至少一者再分配至開口106之未填充區域116(圖1D)中,從而實質上完全填充開口106。在不欲受任何特定理論約束之情況下,據信,可在拋光製程期間將諸如導電材料112以及(視情況)襯墊材料110及材料114之延展性材料機械推動或再分配至空隙(例如,未填充區域116)中,從而填充開口106之未填充區域116。然而,在拋光製程期間施加於延展性材料上之機械應力可使延展性材料被拉出開口106。可藉由保持開口106之一部分未填充且藉由提高導電材料112與下伏材料(亦即,材料104或(若存在)電極材料108)之間的黏著來實質上減小或消除此等機械應力。舉例而言,在導電材料112由展現與下伏區域(例如,電極材料108)之低劣黏著之材料(例如,銀)形成的實施例中,襯墊材料110可實質上提高導電材料112與下伏區域之間的黏著,從而阻止導電材料112因機械應力而自開口106移除。
該拋光製程可為使用習知化學機械拋光設備及漿料執行之化學機械拋光製程,該拋光製程使延展性材料(例如,導電材料112及(視情況)襯墊材料110)能夠再分配至開口106之未填充區域116中以形成互
連件120。此漿料可為例如呈中性或弱鹼性pH值之基於氧化鋁之漿料,該漿料實質上無氧化劑。該拋光製程亦可為使用習知化學機械拋光設備及水(例如,去離子水)代替化學漿料執行之機械拋光製程。在不添加化學蝕刻劑之情況下,將水用作拋光製程中之液體組份可使導電材料112及襯墊材料110(若存在)能夠再分配至開口106之未填充區域中而不實質上移除此等材料。
在形成互連件120之後,可視情況執行另一退火製程。以實例來說明且並非限制,此退火製程可包括將圖1E之半導體結構100曝露至介於約100℃與約500℃之間且更特定言之約200℃的溫度。該退火製程可導致形成如先前論述之互連件120(導電材料112及襯墊材料110)之材料的合金。退火之後,互連件120可包括導電材料112、襯墊材料110及合金之區域或可實質上包括該合金。
為了簡單起見,參看圖1A至圖1E所描述之方法說明一種形成單一互連件120之方法。然而,如一般熟習此項技術者將理解,可使用參看圖1A至圖1E所描述之方法而形成複數個互連件或金屬佈線之一網路(例如,金屬化層)。如一般熟習此項技術者將理解,互連件120可存在於各種半導體裝置中。舉例而言,互連件120可用於電連接主動裝置,諸如,電晶體、電容器等。互連件120可包括電連接此等主動裝置之金屬佈線的網路之一部分。
圖2A至圖2E為說明另一種形成互連件之方法之實施例的半導體結構200之簡化的部分橫截面圖。如圖2A中所展示,可形成半導體結構200,該半導體結構200包括上覆於基板202上之材料204中之開口206。開口206可具有小於約100nm且更特定言之小於約20nm之寬度W2。開口206可曝露材料204或(若存在)可選電極材料208之一表面,可選電極材料208安置於材料204與基板202之間。可使用用於形成圖1A中所展示之半導體結構100的實質上相同之方法而形成圖2A中所展
示之半導體結構200。儘管圖2A至圖2E指示存在電極材料208,但應理解,電極材料208為可選的且材料204可在開口206至少部分地延伸穿過材料204的情況下與基板202直接接觸。
參看圖2B,可在半導體結構200上方(亦即,材料204及(若存在)電極材料208中之每一者之所曝露表面上方)形成導電材料212。可使用諸如化學氣相沈積製程、物理氣相沈積製程或物理沈積製程之習知沈積製程而由銀(Ag)或銀(Ag)合金形成導電材料212。習知氣相沈積製程(例如,化學氣相沈積及物理氣相沈積)無法有效地在窄的開口(例如,具有小於或等於20nm之至少一尺寸的開口)中沈積銀。因此,在開口206之至少一尺寸(亦即,寬度W2)小於或等於約20nm之實施例中,可使用濺鍍製程以在開口206內形成導電材料212。以非限制性實例來說明,可實質上在半導體結構200之整個所曝露表面上方保形地沈積導電材料212。導電材料212可形成有足以至少部分地填充開口206之厚度。在沈積導電材料212之後,可保持開口206之一部分未填充(亦即,未填充區域216)。以實例來說明且並非限制,導電材料212可由銀形成且具有介於約5nm與約30nm之間且更特定言之介於約10nm與約20nm之間的厚度。
參看圖2C,可在導電材料212之表面上方形成襯墊材料210。如將進一步詳細論述,可由促進黏著至可形成於完成之互連件上方之上電極(未圖示)及/或使該上電極中之接觸電阻減小的材料形成襯墊材料210。舉例而言,可由鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠中之至少一者形成襯墊材料210。可使用諸如化學氣相沈積製程、物理氣相沈積製程或濺鍍製程之習知沈積製程而形成襯墊材料210。如圖2C中所展示,在導電材料212上方形成襯墊材料210之後,可保留開口206之未填充區域216之一部分。以實例來說明且並非限制,襯墊材料210可形成有介於約0.5nm與約20nm之間且更特定言之介於約1nm
與約5nm之間的厚度。
可基於材料之所要比率來選擇襯墊材料210及導電材料212之厚度。在襯墊材料210包括鉑且導電材料212包括銀之實施例中,襯墊材料210對導電材料212之比率可小於或等於約1至2。
參看圖2D,在襯墊材料210(以虛線展示)包括與導電材料212形成合金之材料的實施例中,可視情況執行一退火製程以形成導電材料212與襯墊材料210之合金。舉例而言,導電材料212可包括銀,襯墊材料210可包括諸如鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠之至少一材料,該至少一材料與銀反應以形成合金。以實例來說明且並非限制,該退火製程可包括將半導體結構200曝露至介於約100℃與約500℃之間且更特定言之約200℃的溫度。在該退火製程期間,可轉化導電材料212及襯墊材料210之至少一部分以形成包括合金之材料214(以虛線展示)。材料214中之合金可包括襯墊材料210及導電材料212之實質上均質之混合物,或可為包括具有襯墊材料210對導電材料212之不同比率之區域的異質混合物。在襯墊材料210包括鉑且導電材料212包括銀之實施例中,半導體結構200可曝露至約200℃之溫度以使得鉑及銀組合以形成銀-鉑合金。襯墊材料210可至少實質上完全與導電材料212合金化以形成材料214,或襯墊材料210之一部分可保持上覆於材料214上。
在襯墊材料210由不與導電材料212形成合金之材料形成的實施例中,可略過退火製程,且襯墊材料210可保留在導電材料212上方(如圖2C中所展示)。舉例而言,導電材料212可包括銀且襯墊材料210可包含鉭,且鉭可安置於銀上方。
可使半導體結構200之所曝露表面經受材料移除製程,諸如,呈化學機械拋光(CMP)製程或機械拋光製程之形式的所謂的拋光製程,從而形成如圖2E中所展示之互連件220。舉例而言,所使用之製程可
用於移除導電材料212及(若存在)材料214及/或上覆於材料204上之襯墊材料210(圖2D)中之每一者之部分。此外,該拋光製程可用於將導電材料212、材料214及/或襯墊材料210中之至少一者再分配至開口206之未填充區域216(圖2D)中,從而實質上完全填充開口206。在不欲受任何特定理論約束之情況下,據信,可在拋光製程期間將延展性材料(例如,導電材料212以及(視情況)襯墊材料210及/或材料214)機械推動或再分配至空隙(例如,開口206之未填充區域216)中,從而填充開口206之未填充區域216。然而,在拋光製程期間施加於延展性材料上之機械應力可使延展性材料被拉出開口206。可藉由保持開口206之一部分未填充且藉由提高導電材料212與下伏材料(亦即,材料204或(若存在)電極材料208)之間的黏著來實質上減小或消除此等機械應力。如先前參看圖1E所論述,該拋光製程可為化學機械拋光製程或機械拋光製程。
在形成互連件220之後,可視情況執行另一退火製程。以實例來說明且並非限制,該退火製程可包括將半導體結構200曝露至介於約100℃與約500℃之間的溫度,更特定言之,曝露至約200℃之溫度。該退火製程可導致形成如先前論述之導電材料212與襯墊材料210之合金。退火之後,互連件220可包括導電材料212、襯墊材料210及合金之區域或可實質上包括該合金。
為了簡單起見,參看圖2A至圖2E所描述之方法說明一種形成單一互連件220之方法。然而,如一般熟習此項技術者將理解,可使用參看圖2A至圖2E所描述之方法而形成複數個互連件或金屬佈線之一網路(例如,金屬化層)。如一般熟習此項技術者將理解,互連件220可存在於各種半導體裝置中。舉例而言,互連件220可用於電連接主動裝置,諸如,電晶體、電容器等。互連件220可包括電連接此等主動裝置之金屬佈線的網路之一部分。
圖3A係一導電橋式隨機存取記憶體(CBRAM)單元330之一實施例的一簡化部分橫截面圖,其說明一CBRAM裝置之一導電元件(如一電極311),以及圖3B1至圖3D為說明一種形成如圖3A所示之CBRAM單元330之方法的實施例的簡化部分橫截面圖。CBRAM可包括複數個記憶體單元,該複數個記憶體單元中之一者展示於圖3A中。CBRAM單元330可包括記憶體材料309,該記憶體材料309安置於第一電極308與第二電極311之間。舉例而言,如將進一步詳細描述,記憶體材料309可安置於下伏材料之表面上方或開口306之所曝露表面上方。記憶體材料309及第二電極311可上覆於導電結構303上,該導電結構303提供第一電極308與第二電極311之間的電連接。第二電極311可由銀形成。
儘管不欲受任何特定理論約束,但據信,歸因於導電橋之選擇性形成及分解而發生CBRAM單元330之操作,該導電橋藉由銀電遷移至記憶體材料309中而形成。因此,在第二電極311之沈積期間,控制銀離子擴散至記憶體材料309中為重要的。
圖3B至圖3D說明一種形成圖3A中所展示之CBRAM單元330之方法的實施例。如圖3B1中所展示,可形成半導體結構300,該半導體結構300包括介電材料304中之開口306,開口306上覆於層間介電材料305中之導電結構303上,該層間介電材料305上覆於第一電極308上。可由諸如鎢、鉑、氮化鈦(TiN)或鎳之導電材料形成第一電極308。可使用諸如化學氣相沈積製程或原子層沈積製程之習知沈積製程而在基板(未展示)上方形成第一電極308。半導體結構300可包括記憶體材料309,該記憶體材料309上覆於導電結構303及層間介電材料305之表面上。
可由例如氮化矽、二氧化矽或氮氧化矽形成層間介電材料305。可使用諸如化學氣相沈積製程、原子層沈積製程或物理氣相沈積製程
之習知沈積製程而在第一電極308上方形成層間介電材料305。
可由諸如氮化鈦、鎢、氮化鎢、鉭及氮化鉭中之至少一者之導電材料形成導電結構303。可形成導電結構303,使之與第一電極308電連接。可使用習知技術而在層間介電材料305中形成導電結構303,該等習知技術之細節為此項技術中已知且因此本文中未對其進行詳細描述。舉例而言,可使用習知金屬鑲嵌製程以藉由以下步驟在層間介電材料305中形成導電結構303:在層間介電材料305中形成一渠溝;在層間介電材料305上方形成導電材料以填充該渠溝;及執行化學機械拋光(CMP)製程以移除上覆於層間介電材料305上之導電材料之部分。
可由諸如硒化鍺或硫化鍺之硫族化物材料或諸如高k氧化物材料之氧化物材料形成記憶體材料309。適合的高k介電材料之實例包括(但不限於)二氧化矽、氧化鉭、氧化鈦、氧化氮、氧化鋯及氧化鉿。舉例而言,可使用諸如物理氣相沈積製程、化學氣相沈積製程或原子層沈積製程之習知沈積製程而沈積記憶體材料309。
可由例如氮化矽、正矽酸四乙酯(TEOS)、二氧化矽或氮氧化矽形成介電材料304。可使用諸如化學氣相沈積製程、原子層沈積製程或物理氣相沈積製程之習知沈積製程而在層間介電材料305及導電結構303上方形成介電材料304。在一些實施例中,介電材料304可形成為單體結構。在其他實施例中,介電材料304可形成為包括如以虛線所展示之複數個材料304A、材料304B、材料304C的堆疊結構。舉例而言,可由氮化矽形成材料304A及材料304C且可由正矽酸四乙酯形成材料304B。
可藉由使用例如積體電路製造技術中已知之習知光微影技術(例如,遮罩及蝕刻)來移除介電材料304之一部分而在介電材料304中形成開口306。經移除以形成開口306之介電材料304之部分可上覆於導
電結構303上以使得開口306曝露導電結構303之一表面及(視情況)鄰接導電結構303之該表面的層間介電材料305之表面。以實例來說明且並非限制,開口306可具有小於約100nm且更特定言之小於約20nm之寬度W3。
參看圖3B2,在形成介電材料304及在介電材料304中形成開口306之後,可或者在介電材料304之側壁以及導電結構303及層間介電材料305之表面上方形成記憶體材料309。如先前參看圖3B1所論述,可使用諸如物理氣相沈積製程、化學氣相沈積製程或原子層沈積製程之習知沈積製程而由諸如硒化鍺或硫化鍺之硫族化物材料或諸如高k氧化物材料之氧化物材料形成記憶體材料309。
在沈積記憶體材料309之後,可視情況執行一退火製程。以實例來說明且並非限制,該退火製程可包括將半導體結構300曝露至介於約100℃與約500℃之間的溫度,且更特定言之,曝露至約200℃之溫度。
如圖3C中所展示,可在記憶體材料309上方形成包括銀之導電材料312。為了簡單起見,半導體結構300展示有記憶體材料309(以虛線展示),該記憶體材料309安置於開口306中之表面上方及介電材料304之表面上方。然而,如所組態,記憶體材料309亦可安置在層間介電材料305與介電材料304之間,如圖3B1中所展示。
使用諸如物理氣相沈積(PVD)製程或化學氣相沈積(CVD)製程之習知氣相沈積製程形成銀可在形成第二電極311期間導致銀不良擴散至記憶體材料309中。銀之此擴散可導致CBRAM裝置之單元間操作之變化性。因此,可使用習知濺鍍製程而由銀(Ag)或銀合金形成導電材料312。以實例來說明且並非限制,可實質上在記憶體材料309之整個所曝露表面上方保形地沈積導電材料312。導電材料312之厚度可使得開口306之一部分保持未填充(亦即,未填充區域316)。以實例來說明
且並非限制,導電材料312可形成有介於約10nm與約20nm之間的厚度。
參看圖3D,可在導電材料312之表面上方形成襯墊材料310。舉例而言,可由鉑、鉭、鋁(Al)、鉛(Sb)、銅、銥、鈦、鎳、鈷、釕及銠中之至少一者形成襯墊材料310。可使用諸如化學氣相沈積製程、物理氣相沈積製程或濺鍍製程之習知沈積製程來形成襯墊材料310。以實例來說明且並非限制,襯墊材料310可形成有介於約0.5nm與約20nm之間且更特定言之介於約1nm與約5nm之間的厚度。
自不需要之區域移除銀可為複雜的,此係因為當前尚未有相對於其他材料選擇性地移除銀之蝕刻劑。因此,如參看圖3D所描述,藉由使半導體結構300之所曝露表面經受拋光製程,可將材料(亦即,導電材料312及襯墊材料310)自介電材料304之上表面推動或再分配至空隙(例如,開口306之未填充區域316)中。在拋光製程期間,可填充未填充區域316(圖3C及圖3D)以形成圖3A中所展示之第二電極311。視情況,可接著執行一退火製程以形成導電材料312與襯墊材料310之合金。舉例而言,在襯墊材料310包含鉑、鋁(Al)、鉛(Sb)、銅、銥、鈦、鎳、鈷、釕及銠之實施例中,可執行退火製程以形成合金。在沈積導電材料312之前執行退火製程的實施例中,可在此階段略過退火製程。該退火製程可包括將半導體結構300曝露至介於約100℃與約500℃之間且更特定言之約200℃的溫度。以實例來說明且並非限制,可由銀形成導電材料312,可由鉑形成襯墊材料310且可在退火製程期間形成銀-鉑合金。導電材料312及襯墊材料310之大多數合金或實質上全部合金可位於與記憶體材料309之一表面相對的第二電極311之區域中以使得與記憶體材料309接觸或鄰接記憶體材料309之第二電極311之區域實質上包括銀。
在圖3A至圖3D中,在CBRAM單元330中說明形成含銀導電元件
(亦即,第二電極311)之方法之實施例。然而,如一般熟習此項技術者將理解,此等方法亦可用於在眾多半導體結構及裝置中形成其他導電元件。
在上覆於一矽晶圓之二氧化矽材料中形成複數個渠溝。該複數個渠溝各自具有約50nm之深度。使用習知濺鍍製程而在該矽晶圓之表面上方沈積銀。使用習知濺鍍塗佈機執行該濺鍍製程。在該矽晶圓之表面上方濺鍍銀約兩分鐘,在此時間期間,銀之厚度達到約15nm。接著使用濺鍍塗佈機在銀上方形成鉑。在該矽晶圓之表面上方濺鍍鉑約30秒,在此時間期間,鉑之厚度達到約6nm。
使用去離子水及習知拋光墊來對上面有銀及鉑之矽晶圓執行機械拋光製程。在機械拋光製程期間不使用化學漿料。使用約100 RPM之墊轉速來拋光鉑之表面。在機械拋光製程之後,使用掃描電子顯微鏡(SEM)而觀察到:該等渠溝實質上以材料(例如,銀及鉑)填充。
接著使用習知工業烘箱執行退火製程。將該工業烘箱設定至200℃且將上面有銀及鉑之矽晶圓置放於該工業烘箱中約10分鐘。得到確認的是,後退火之銀-鉑合金實質上為平滑的,具有低阻值。
儘管本發明易受到各種修改及具有各種替代形式,但特定實施例已藉由實例在圖式中加以展示且已在本文中加以詳細描述。然而,本發明並不意欲限於所揭示之特定形式。實情為,本發明欲涵蓋落入如藉由隨附申請專利範圍及其法定等效物界定之本發明之範疇內的所有修改、等效物及替代物。
303‧‧‧導電結構
304‧‧‧介電材料
304A‧‧‧材料
304B‧‧‧材料
304C‧‧‧材料
305‧‧‧層間介電材料
306‧‧‧開口
308‧‧‧第一電極
309‧‧‧記憶體材料
311‧‧‧第二電極
330‧‧‧導電橋式隨機存取記憶體(CBRAM)單元
Claims (13)
- 一種半導體結構,其包含:覆於一電極之一導電結構及一層間介電材料;直接覆於該層間介電材料之一介電材料;一硫族化物材料及一氧化物材料中至少一者,其與該介電材料、該導電結構及該層間介電材料直接接觸;及直接覆於該硫族化物材料及該氧化物材料中該至少一者之一導電材料,該導電材料包含銀及鉭以及包含另一材料之至少一區域。
- 如請求項1之半導體結構,其中該導電材料包含覆於該銀之該鉭。
- 如請求項1之半導體結構,其中覆於該電極之該導電結構包含一合金,該合金包含銀及下列金屬之至少一者:鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠。
- 如請求項1或2中任何一項之半導體結構,其中該另一材料包含下列金屬中至少一者:鉑、鉭、鋁、鉛、銅、銥、鈦、鎳、鈷、釕及銠。
- 如請求項1之半導體結構,其中該導電材料之至少一部份包含該銀及該另一材料中至少一者,該另一材料包含鉑。
- 如請求項1或2中任何一項之半導體結構,其中該另一材料包含鉭,該鉭覆於該銀。
- 如請求項1之半導體結構,其進一步包含一襯墊材料,該襯墊材料在該導電結構及該電極之上,該襯墊材料包含下列金屬之至少一者:鉑、鉭、鋁、錫、銅、銥及鈦。
- 一種記憶體單元,其包含: 覆於一電極之一導電結構及一層間介電材料;直接覆於該層間介電材料之一介電材料;覆於且直接與該介電材料、該導電結構及該層間介電材料直接接觸之一記憶體材料;及直接覆於該記憶體材料及置於該介電材料中之至少一開口中之一導電材料,該至少一開口覆於該導電結構及該電極,且該導電材料包含銀及另一材料。
- 如請求項8之記憶體單元,其中該導電材料包含該銀及該另一材料之一合金,該另一材料包含下列金屬之至少一者:鉑、鋁、錫、銅、銥、鈦、鎳、鈷、釕及銠。
- 如請求項8之記憶體單元,其中該導電材料包含該銀及該另一材料之一混合物,該另一材料包含鉭。
- 如請求項8至10中任何一項之記憶體單元,其中該記憶體材料包含一硫族化物材料及一氧化物材料中至少一者。
- 如請求項8至10中任何一項之記憶體單元,其中該導電結構係位於該電極及該導電材料之間。
- 如請求項12之記憶體單元,其中該記憶體材料覆於該導電結構之表面。
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JP5582326B2 (ja) | 2014-09-03 |
TWI446489B (zh) | 2014-07-21 |
JP2014508422A (ja) | 2014-04-03 |
EP2686875B1 (en) | 2016-09-28 |
US20120235106A1 (en) | 2012-09-20 |
TW201438148A (zh) | 2014-10-01 |
EP2686875A2 (en) | 2014-01-22 |
TW201244005A (en) | 2012-11-01 |
US8524599B2 (en) | 2013-09-03 |
WO2012125610A3 (en) | 2012-12-06 |
US10862030B2 (en) | 2020-12-08 |
US20190363253A1 (en) | 2019-11-28 |
WO2012125610A2 (en) | 2012-09-20 |
JP2014222760A (ja) | 2014-11-27 |
US20130320291A1 (en) | 2013-12-05 |
KR101481934B1 (ko) | 2015-01-12 |
CN107275282A (zh) | 2017-10-20 |
US9520558B2 (en) | 2016-12-13 |
KR20130133025A (ko) | 2013-12-05 |
US10411186B2 (en) | 2019-09-10 |
SG193501A1 (en) | 2013-10-30 |
EP2686875A4 (en) | 2014-09-03 |
US20180114901A1 (en) | 2018-04-26 |
CN103503116A (zh) | 2014-01-08 |
US20170092855A1 (en) | 2017-03-30 |
US9865812B2 (en) | 2018-01-09 |
JP5805275B2 (ja) | 2015-11-04 |
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