JP2014508422A - 少なくとも1つの導電性素子を形成する方法、半導体構造を形成する方法、メモリセルおよび関連する半導体構造を形成する方法 - Google Patents
少なくとも1つの導電性素子を形成する方法、半導体構造を形成する方法、メモリセルおよび関連する半導体構造を形成する方法 Download PDFInfo
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- JP2014508422A JP2014508422A JP2013558103A JP2013558103A JP2014508422A JP 2014508422 A JP2014508422 A JP 2014508422A JP 2013558103 A JP2013558103 A JP 2013558103A JP 2013558103 A JP2013558103 A JP 2013558103A JP 2014508422 A JP2014508422 A JP 2014508422A
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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Abstract
【選択図】図3A
Description
本出願は、「METHODS OF FORMING AT LEAST ONE CONDUCTIVE ELEMENT,METHODS OF FORMING A SEMICONDUCTOR STRUCTURE,METHODS OF FORMING A MEMORY CELL AND RELATED SEMICONDUCTOR STRUCTURES」について、2011年3月17日に出願された米国特許出願番号第13/050,725号の出願日の利益を主張する。
さらに、銀合金または混合物の使用は、そのような導電性素子を含む半導体処理の最終段階において行われる銀の熱処理中の凝塊に関する問題を実質的に低減もしくは排除することができる。銀、銀合金、または銀混合物を使用することで、少なくとも1つの寸法が約20nm未満といった充填される微小な開口を形成することも可能である。
<実施例>
実施例1
Claims (20)
- 半導体構造を形成する方法であって、
誘電性材料の側壁によって画定される少なくとも1つの開口を含む構造の上に、第1の導電性材料を形成することと、
前記第1の導電性材料の上に第2の導電性材料を形成することと、
前記構造を焼鈍して、前記第1の導電性材料および前記第2の導電性材料の少なくとも一部を含む材料を形成することと、研磨過程を行って、前記第1の導電性材料および前記第2の導電性材料のうちの少なくとも1つを前記少なくとも1つの開口の非充填領域に実質的に再分配することと、のうちの少なくとも1つを実行することと、
を含む、方法。 - 誘電性材料の側壁によって画定される少なくとも1つの開口を含む構造の上に第1の導電性材料を形成することは、前記誘電性材料の前記側壁およびその間の電極の表面の上に前記第1の導電性材料を形成することを含む、請求項1に記載の方法。
- 誘電性材料の側壁によって画定される少なくとも1つの開口を含む構造の上に第1の導電性材料を形成することは、約20nm未満の少なくとも1つの寸法を有する前記少なくとも1つの開口の上に前記第1の導電性材料を形成することを含む、請求項1に記載の方法。
- 前記第1の導電性材料の上に第2の導電性材料を形成することは、前記少なくとも1つの開口を実質的に充填することなく、前記第1の導電性材料の上に銀を形成することを含む、請求項1に記載の方法。
- 前記構造を焼鈍して、前記第1の導電性材料および前記第2の導電性材料の少なくとも一部を含む材料を形成することは、前記構造を焼鈍して、銀およびタンタルの混合物を含む材料を形成することを含む、請求項1に記載の方法。
- 前記構造を焼鈍して、前記第1の導電性材料および前記第2の導電性材料の少なくとも一部を含む材料を形成することは、前記構造を焼鈍して、銀、ならびに白金、アルミニウム、すず、銅、イリジウム、チタニウム、ニッケル、コバルト、ルテニウム、およびロジウムのうちの少なくとも1つからなる合金を含む材料を形成することを含む、請求項1に記載の方法。
- 前記構造を焼鈍して、前記第1の導電性材料および前記第2の導電性材料の少なくとも一部を含む材料を形成することは、前記構造を約200℃〜約600℃の温度に曝露することを含む、請求項1に記載の方法。
- 研磨過程を行って、前記第1の導電性材料および前記第2の導電性材料のうちの少なくとも1つを前記少なくとも1つの開口の非充填領域に実質的に再分配することは、前記少なくとも1つの開口を前記第1の導電性材料および前記第2の導電性材料のうちの少なくとも1つで実質的に充填することと、前記少なくとも1つの開口に隣接する前記誘電性材料の表面から材料を除去することと、のうちの少なくとも1つ含む、請求項1に記載の方法。
- 研磨過程を行って、前記第1の導電性材料および前記第2の導電性材料のうちの少なくとも1つを前記少なくとも1つの開口の非充填領域に再分配することは、水からなる液体成分を使用して前記研磨過程を行うことを含む、請求項1に記載の方法。
- 前記誘電性材料の側壁によって画定される前記少なくとも1つの開口を含む前記構造の上にメモリ材料を形成することをさらに含む、請求項1に記載の方法。
- 前記構造の上にメモリ材料を形成することは、前記構造の上にカルコゲナイド材料および酸化物材料のうちの少なくとも1つを形成することを含む、請求項10に記載の方法。
- 前記構造の上にメモリ材料を形成することは、前記構造の上に、硫化ゲルマニウム、セレン化ゲルマニウム、酸化ケイ素、酸化タンタル、酸化チタニウム、酸化窒素、酸化ジルコニウム、および酸化ハフニウムのうちの少なくとも1つを形成することを含む、請求項10に記載の方法。
- 誘電性材料の側壁によって画定される少なくとも1つの開口を含む構造の上に第1の導電性材料を形成することは、1:1〜約20:1のアスペクト比を有する前記少なくとも1つの開口を形成することを含む、請求項1に記載の方法。
- 構造の上に第1の導電性材料を形成することは、前記構造の上に銀を含む前記第1の導電性材料を形成することを含む、請求項1に記載の方法。
- 構造の上に第1の導電性材料を形成することは、前記構造の上に、白金、タンタル、アルミニウム、すず、銅、イリジウム、チタニウム、ニッケル、コバルト、ルテニウム、およびロジウムのうちの少なくとも1つを含む前記第1の導電性材料を形成することを含む、請求項1に記載の方法。
- 前記第1の導電性材料の上に第2の導電性材料を形成することは、前記第1の導電性材料の上に銀を含む前記第2の導電性材料を形成することを含む、請求項1に記載の方法。
- 前記第1の導電性材料の上に第2の導電性材料を形成することは、前記第1の導電性材料の上に、白金、タンタル、アルミニウム、すず、銅、イリジウム、チタニウム、ニッケル、コバルト、ルテニウム、およびロジウムのうちの少なくとも1つを含む前記第2の導電性材料を形成することを含む、請求項1に記載の方法。
- 電極の上に重なる導電性構造と、
前記導電性構造と接触しているカルコゲナイド材料および酸化物材料のうちの少なくとも1つと、
カルコゲナイド材料および酸化物材料のうちの前記少なくとも1つの上に重なる導電性材料であって、銀およびタンタル、ならびに別の材料を含む少なくとも1つの領域を含む、導電性材料と、
を含んでいる、半導体構造。 - 前記導電性材料は、前記銀の上に重なるタンタルを含む、請求項18に記載の半導体構造。
- 前記電極の上に重なる前記導電性構造は、銀、ならびに、白金、アルミニウム、すず、銅、イリジウム、チタニウム、ニッケル、コバルト、ルテニウム、およびロジウムのうちの少なくとも1つの合金を含む、請求項18または請求項19に記載の半導体構造。
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US20170092855A1 (en) | 2017-03-30 |
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WO2012125610A3 (en) | 2012-12-06 |
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US10862030B2 (en) | 2020-12-08 |
US20120235106A1 (en) | 2012-09-20 |
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US8524599B2 (en) | 2013-09-03 |
US9520558B2 (en) | 2016-12-13 |
TWI446489B (zh) | 2014-07-21 |
US20190363253A1 (en) | 2019-11-28 |
CN107275282A (zh) | 2017-10-20 |
TW201438148A (zh) | 2014-10-01 |
JP2014222760A (ja) | 2014-11-27 |
WO2012125610A2 (en) | 2012-09-20 |
JP5582326B2 (ja) | 2014-09-03 |
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CN103503116A (zh) | 2014-01-08 |
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