TWI553718B - 半導體裝置及藉由形成保護材料於堆疊在半導體晶圓上之半導體晶粒之間以製造半導體裝置之方法以減少於切割時之缺陷 - Google Patents

半導體裝置及藉由形成保護材料於堆疊在半導體晶圓上之半導體晶粒之間以製造半導體裝置之方法以減少於切割時之缺陷 Download PDF

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TWI553718B
TWI553718B TW099135407A TW99135407A TWI553718B TW I553718 B TWI553718 B TW I553718B TW 099135407 A TW099135407 A TW 099135407A TW 99135407 A TW99135407 A TW 99135407A TW I553718 B TWI553718 B TW I553718B
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semiconductor
wafer
die
protective material
semiconductor wafer
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TW099135407A
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TW201123287A (en
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林宅基
尹慈恩
李成尹
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史達晶片有限公司
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description

半導體裝置及藉由形成保護材料於堆疊在半導體晶圓上之半導體晶粒之間以製造半導體裝置之方法以減少於切割時之缺陷
本發明大體上和半導體裝置有關，且更明確地說，和半導體裝置及形成保護材料於堆疊在半導體晶圓上之半導體晶粒之間之方法以減少於切割時之缺陷有關。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電組件。離散式半導體裝置通常含有一種類型的電組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電組件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的原子結構會使得可藉由施加電場或基礎電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，以便操縱及控制該半導體裝置的傳導性。
一半導體裝置會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基礎電流，該電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中切割個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係生產較小的半導體裝置。較小的裝置通常會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還具有較小的覆蓋面積，這係較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
於一晶粒至晶圓(Die-To-Wafer，D2W)封裝中，複數個半導體晶粒會被鑲嵌至一半導體晶圓的一表面。該晶圓中介於該等被鑲嵌半導體晶粒之間的部分通常不會受到支撐，也就是，在該等被鑲嵌晶粒之間會有一空氣空間。在真空夾持操縱期間可能會在該晶圓中形成晶圓凹凸，尤其是在該晶圓中介於該等被鑲嵌半導體晶粒之間未被支撐的部分中。矽塵與其它污染物會累積在該等被鑲嵌半導體晶粒之間的空氣空間之中並且會黏著至該半導體晶圓的背表面。該半導體晶圓會以一鋸片從該等被鑲嵌半導體晶粒之間的背表面處來切割。該鋸片的裁切作業會在該晶圓中之被切割晶粒的頂端、底部以及側邊處造成碎屑與破裂。對該被切割晶粒的頂端、底部以及側邊所造成的切割破壞可能會導致裝置缺陷與失效。
本發明需要切割晶粒至晶圓封裝但卻不會破壞該被切割的晶粒。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一半導體晶圓，其含有複數個第一半導體晶粒；將複數個第二半導體晶粒鑲嵌至該半導體晶圓的一第一表面；將一第一膠帶放置在該半導體晶圓的一第二表面上，該第二表面和該半導體晶圓的第一表面反向；在該第二半導體晶粒及該半導體晶圓的第一表面上方形成保護材料；移除該第一膠帶；以及將該等第二半導體晶粒之間的半導體晶圓切割成個別的晶粒至晶圓封裝，每一個晶粒至晶圓封裝皆含有堆疊在該第一半導體晶粒上的第二半導體晶粒。該保護材料會在切割期間保護該半導體晶圓。該方法還進一步包含下面步驟：將該晶粒至晶圓封裝鑲嵌至一基板；移除該保護材料；以及將一囊封劑沉積在該晶粒至晶圓封裝與基板的上方。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一半導體晶圓，其含有複數個第一半導體晶粒；將複數個第二半導體晶粒鑲嵌至該半導體晶圓的一第一表面；在該第二半導體晶粒及該半導體晶圓的第一表面上方形成保護材料；以及將該等第二半導體晶粒之間的半導體晶圓切割成個別的晶粒至晶圓封裝，每一個晶粒至晶圓封裝皆含有堆疊在該第一半導體晶粒上的第二半導體晶粒。該保護材料會在切割期間保護該半導體晶圓。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一半導體晶圓；在該半導體晶圓的一第一表面中形成複數條通道；在該半導體晶圓的該第一表面中的該等通道的上方及之間沉積一保護層；以及研磨該半導體晶圓的一第二表面，用以降低該半導體晶圓的厚度，該第二表面和該半導體晶圓的第一表面反向。該保護材料會在研磨期間保護該等通道。
於另一實施例中，本發明係一種藉由一製程所製成的半導體裝置，該製程包括：提供一半導體晶圓，其含有複數個第一半導體晶粒；將複數個第二半導體晶粒鑲嵌至該半導體晶圓的一第一表面；在該第二半導體晶粒及該半導體晶圓的第一表面上方形成保護材料；以及將該等第二半導體晶粒之間的半導體晶圓切割成個別的晶粒至晶圓封裝，每一個晶粒至晶圓封裝皆含有堆疊在該第一半導體晶粒上的第二半導體晶粒。該保護材料會在切割期間保護該半導體晶圓。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或雷同的元件。雖然本文會以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可能併入的替代例、修正例以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電組件和被動式電組件，它們會被電連接而形成功能性電路。主動式電組件(例如電晶體與二極體)能夠控制電流的流動。被動式電組件(例如電容器、電感器、電阻器以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有不同類型和不同摻雜程度的多個區域，它們會在必要時被排列成用以在施加一電場或基礎電流時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件的一部分、被動式組件的一部分或是組件之間的電連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。一圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術，藉由將該材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有磨蝕作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到晶圓的表面。化學藥劑的磨蝕性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生均勻平坦的表面。
後端製造係指將已完成的晶圓裁切或切割成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為切割晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域形成刻痕並且折斷。該晶圓會利用雷射裁切工具或鋸片來進行切割。經過切割之後，個別晶粒便會被鑲嵌至包含接針或接觸觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1圖解一電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上鑲嵌著複數個半導體封裝。電子裝置50可能具有某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係一單機型系統，其會使用該等半導體封裝來實施一或多項電氣功能。或者，電子裝置50亦可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一圖形卡、一網路介面卡或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻電路、離散式裝置或是其它半導體晶粒或電組件。
在圖1中，印刷電路板52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該印刷電路板之上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在印刷電路板52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程或是其它合宜的金屬沉積製程。訊號線路54會在該等半導體封裝、被鑲嵌的組件、以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載板附接至該印刷電路板。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該印刷電路板。
為達解釋目的，圖中在印刷電路板52之上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在印刷電路板52之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載板(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合以及其它電子組件的各種半導體封裝的任何組合皆能夠被連接至印刷電路板52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製成的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而會降低消費者的成本。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在印刷電路板52之上的雙直列封裝64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。接觸觸墊76係由一或多層的導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或是銀(Ag))製成，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在雙直列封裝64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被黏著至一中間載板78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與印刷電路板52之間提供電互連。囊封劑84會被沉積在該封裝的上方，藉由防止濕氣和粒子進入該封裝並污染晶粒74或焊線82而達到環境保護的目的。
圖2b所示的係被鑲嵌在印刷電路板52之上的凸塊晶片載板62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92被鑲嵌在載板90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在印刷電路板52的一表面上方用以防止氧化。接觸觸墊102會被電連接至印刷電路板52中的一或多條導體訊號線路54。多個凸塊104會被形成在凸塊晶片載板62的接觸觸墊98和印刷電路板52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用一覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載板106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層以及介電層。舉例來說，該電路可能包含被形成在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載板106。
球柵陣列60會利用多個凸塊112，以球柵陣列樣式的第二層封裝被電氣性及機械性連接至印刷電路板52。半導體晶粒58會經由凸塊110、訊號線114以及凸塊112被電連接至印刷電路板52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載板106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會提供一條從半導體晶粒58上的主動式裝置至印刷電路板52上的傳導軌的短電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至印刷電路板52，而沒有中間載板106。
圖3a至3j所示的係，配合圖1及2a至2c，用以在堆疊於一半導體晶圓上的半導體晶粒之間形成保護材料的製程，以便在切割期間減少缺陷。在圖3a中，一膠帶122會被放置在晶圓級晶片附接裝置或是晶圓夾具120之中。膠帶122可能係高分子膠黏劑，其係利用旋塗或印刷被沉積並且可藉由光、熱或是雷射來脫除。或者，膠帶122亦可能係熱環氧樹脂、層疊聚合物、高分子合成物或是無機黏接化合物。
一半導體晶圓124會被沉積在膠帶122的上方。半導體晶圓124含有一基礎基板材料，例如，矽、鍺、砷化鎵、磷化銦或是碳化矽，用以達到結構性支撐的目的。複數個半導體晶粒或組件126會被形成在晶圓124上，藉由如上面所述的切割道127來分離。每一個半導體晶粒126都包含一主動表面128，該主動表面128含有類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面128裡面的一或多個電晶體、二極體以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、特定應用積體電路、記憶體或是其它訊號處理電路。半導體晶粒126可能還含有用於射頻訊號處理的整合被動元件(IPD)，例如，電感器、電容器以及電阻器。一典型的射頻系統需要在一或多個半導體封裝中用到多個整合被動元件，以便實施必要的電氣功能。
複數個穿孔會使用雷射鑽鑿或蝕刻製造程(例如，深反應離子蝕刻(Deep Reactive Ion Etching，DRIE))被形成貫穿半導體晶粒126。該等穿孔會利用物理氣相沉積製程、化學氣相沉積製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、W、多晶矽或是其它合宜的導電材料填充，用以形成導體直通矽晶穿孔(Through Silicon Via，TSV)130。複數個凸塊或互連線132會被形成在半導體晶粒126的主動表面128上的直通矽晶穿孔130的上方。圖4a所示的係被形成在半導體晶粒126的主動表面128上的直通矽晶穿孔130的上方的互連線132的進一步細節。複數個凸塊或互連線136會被形成在半導體晶圓124的背表面138上的直通矽晶穿孔130的上方。圖4b所示的係以螺旋排列方式被形成在半導體晶粒126的背表面138上的直通矽晶穿孔130的上方的個別互連線136的進一步細節。
在圖3b中，半導體晶圓124會被鑲嵌至晶圓夾具120中的膠帶122。半導體晶圓124的主動表面128會利用埋置在膠帶122中的凸塊或互連線132來接觸該膠帶。
在圖3c中，半導體晶粒或組件146會使用拾放工具145被鑲嵌至半導體晶圓124的背表面138。於其中一實施例中，拾放工具145係一被附接至半導體晶粒146之背表面147的電腦控制真空夾盤。每一個半導體晶粒146都包含一主動表面148，該主動表面148含有類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面148裡面的一或多個電晶體、二極體以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器、特定應用積體電路、記憶體或是其它訊號處理電路。半導體晶粒146可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器以及電阻器。半導體晶粒146上的凸塊149會對齊互連線136，以便經由互連線132與136及直通矽晶穿孔130將半導體晶粒146上的電路電連接至對應半導體晶粒126上的電路。圖4c所示的係被形成在半導體晶粒146的主動表面148的上方的個別互連線149的進一步細節。
在圖3d中，一底層填充材料150(例如，環氧樹脂、高分子材料、薄膜或是其它非導體材料)會利用滴塗工具152被沉積在半導體晶粒146的下方。
在圖3e中，一塗料或保護材料156會被沉積在半導體晶粒146與半導體晶圓124的上方。保護材料156可水溶並且會在室溫處變乾。於其中一實施例中，保護材料156含有聚乙烯醇和水。保護材料156會藉由滴塗機154及旋塗塗敷機或是其它合宜的塗敷機來沉積。
在圖3f中，圖3a至3e中所述的裝配件會從晶圓夾具120處移除並且利用背表面147與保護材料156被鑲嵌至切晶保護膠帶(dicing tape)158。
在圖3g中，會藉由熱、光或是雷射移除膠帶122，用以露出互連線132。該裝配件會利用鋸片或雷射裁切工具160以2毫米(mm)乘120微米(μm)的間隙來進行切晶作業，用以將晶圓124切割成個別的堆疊半導體晶粒126與146。半導體晶粒126與146為不同尺寸的晶粒。於其中一實施例中，半導體晶粒146為4毫米乘4毫米，而半導體晶粒126為6毫米乘6毫米。保護材料156會支撐半導體晶圓124，以便減少晶圓凹凸。此外，保護材料156還會保護半導體晶圓124，俾使得鋸片160的裁切作業會留下平滑的晶粒邊緣並且會在切割期間減少晶圓碎屑或破裂。保護材料156還會密封半導體晶粒146之間的區域，並且防止污染物堆積在半導體晶圓124上。
在圖3h中，多個晶粒裝配件164(每一者皆含有堆疊半導體晶粒126與146)會從膠帶158處被移除，拾放工具168會接觸互連線132。
在圖3i中，晶粒至晶圓封裝164會被鑲嵌至基板170，互連線132會朝向該基板。晶粒至晶圓封裝164會利用去離子水來清潔，以便移除保護材料156、污染物、碎片以及其它多餘的材料。一底層填充材料172(例如，環氧樹脂、高分子材料、薄膜或是其它非導體材料)會利用該滴塗工具被沉積在半導體晶粒146的下方，如圖3j中所示。在晶粒至晶圓封裝164中，半導體晶粒146會經由直通矽晶穿孔130及互連線132與136被電連接至半導體晶粒126。半導體晶粒126的側邊非常平滑而且沒有缺陷，因為保護材料156會在切割期間保護半導體晶圓124。
圖5所示的係具有晶粒至晶圓封裝176的一替代實施例，其係以和圖3a至3j中所述之製程雷同的方式所製成，具有一底邊增進互連結構178。一絕緣層或鈍化層180會被沉積為由下面所製成的一或多層：二氧化矽(SiO2)；氮化矽(Si3N4)；氮氧化矽(SiON)；五氧化二鉭(Ta2O5)；三氧化二鋁(Al2O3)；或是具有雷同絕緣特性及結構性特性的其它材料。該絕緣層180係利用下面的方法所形成：物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或是熱氧化。一部分的絕緣層180會藉由蝕刻製程被移除。導體層182會使用物理氣相沉積製程、化學氣相沉積製程、濺鍍製程、電解質電鍍製程、無電極電鍍製程或是其它合宜的金屬沉積製程進行圖樣化而以一或多層的方式被形成在該等已移除的絕緣層部分180之中。導體層182可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。一部分的導體層182會被電連接至互連線132。導體層182中的其它部分可能為共電或者會被電隔離，端視該半導體裝置的設計及功能而定。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程(ball drop)或是網印製程被沉積在增進互連結構178的上方並且會被電連接至導體層182。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層182。於其中一實施例中，該凸塊材料會藉由將該凸塊材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊184。於某些應用中，凸塊184會被二次回焊，以便改善和導體層182的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層182。凸塊184代表能夠被形成在導體層182上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、短柱凸塊、微凸塊或是其它電互連線。
一囊封劑或模造化合物188會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、旋塗塗敷機、真空層疊塗敷機或是其它合宜的塗敷機被沉積在半導體晶粒126、半導體晶粒146以及增進互連結構178的上方。於其中一實施例中，囊封劑188係利用一模套來沉積。囊封劑188可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯或是具有適當填充劑的聚合物。囊封劑188係非導體並且會為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
半導體晶粒146會經由直通矽晶穿孔130及互連線132與136被電連接至半導體晶粒126。晶粒至晶圓封裝176會經由增進互連結構178被電連接至外部裝置。半導體晶粒126的側邊非常平滑而且沒有缺陷，因為保護材料156會在切割期間保護半導體晶圓124。
圖6a至6e所示的係，配合圖1及2a至2c，用以在堆疊於一半導體晶圓上的半導體晶粒之間形成保護材料的另一種製程，以便在切割期間減少缺陷。接續圖3d的實施例，一囊封劑或模造化合物190會利用焊膏印刷塗敷機、壓縮模造塗敷機、轉印模造塗敷機、液體囊封劑模造塗敷機、旋塗塗敷機、真空層疊塗敷機或是其它合宜的塗敷機被沉積在半導體晶粒146與半導體晶圓124的上方成為保護材料，如圖6a中所示。囊封劑190可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯或是具有適當填充劑的聚合物。
在圖6b中，圖6a中的裝配件會從晶圓夾具120處移除並且利用囊封劑190被鑲嵌至切晶保護膠帶192。
在圖6c中，會藉由熱、光或是雷射移除膠帶122，用以露出互連線132。該裝配件會利用鋸片或雷射裁切工具194以2毫米乘120微米的間隙來進行切晶作業，用以將晶圓124切割成個別的堆疊半導體晶粒126與146。囊封劑190會支撐半導體晶圓124，以便減少晶圓凹凸。此外，囊封劑190還充當半導體晶圓124上的保護材料，俾使得鋸片194的裁切作業會留下平滑的晶粒邊緣並且會在切割期間減少晶圓碎屑或破裂。囊封劑190還會密封半導體晶粒146之間的區域，並且防止污染物堆積在半導體晶圓124上。
在圖6d中，多個晶粒裝配件196(每一者皆含有堆疊半導體晶粒126與146)會從膠帶192處被移除，拾放工具198會接觸互連線132。
在圖6e中，晶粒至晶圓封裝200會被鑲嵌至基板202，互連線132會朝向該基板。一底層填充材料204(例如，環氧樹脂、高分子材料、薄膜或是其它非導體材料)會利用該滴塗工具被沉積在半導體晶粒146的下方。在晶粒至晶圓封裝200中，半導體晶粒146會經由直通矽晶穿孔130及互連線132與136被電連接至半導體晶粒126。半導體晶粒126的側邊非常平滑而且沒有缺陷，因為囊封劑190會在切割期間保護半導體晶圓124。
於另一實施例中，保護材料會被沉積在形成於一半導體晶圓的一表面中的通道上方，如圖7a至7e中所示。圖7a所示的係被放置在研磨機平台212上的半導體晶圓210。複數條溝槽或通道214會藉由裁切輪218被形成在半導體晶圓210的頂表面216中。溝槽深度為背研磨作業之後的目標晶圓厚度的30%至50%。舉例來說，倘若背研磨作業之後的目標晶圓厚度為25微米的話，那麼，通道深度便為10微米。圖7b所示的係被形成在半導體晶圓210的頂表面216中的通道214的進一步細節。通道214係半導體晶圓210的脆弱點，並且可能會在背研磨作業期間造成晶圓破裂或損毀。
在圖7c中，保護材料220會被沉積在半導體晶圓210的頂表面216上的通道214的上方與之間。保護材料220可水溶並且會在室溫處變乾。於其中一實施例中，保護材料220含有聚乙烯醇和水。保護材料220會藉由滴塗機224及旋塗塗敷機或是其它合宜的塗敷機來沉積。
在圖7d中，半導體晶圓210會被倒置，俾使得保護材料220會被定向成朝向研磨機平台212。研磨機226會移除半導體晶圓的一部分背表面228，約略往下一直到保護材料220。保護材料220會在研磨製程期間防止頂表面216與通道214遭到破壞。
在圖7e中，研磨後的半導體晶圓210會被鑲嵌至切晶保護膠帶230與保護材料220，並且會利用去離子水移除其它多餘的材料。半導體晶圓則會利用鋸片或雷射裁切工具232來切割。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會明白，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．半導體晶粒
60．．．球柵陣列(BGA)
62．．．凸塊晶片載板(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無導線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載板
80．．．導體導線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載板
92．．．膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載板
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．晶圓級晶片附接裝置或晶圓夾具
122．．．膠帶
124．．．半導體晶圓
126．．．半導體晶粒或組件
127．．．切割道
128．．．主動表面
130．．．直通矽晶穿孔(TSV)
132．．．凸塊或互連線
136．．．凸塊或互連線
138．．．背表面
145．．．拾放工具
146．．．半導體晶粒或組件
147．．．背表面
148．．．主動表面
149．．．凸塊
150．．．底層填充材料
152．．．滴塗工具
154．．．滴塗機
156．．．塗料或保護材料
158．．．切晶保護膠帶
160．．．鋸片
164．．．晶粒裝配件
168．．．拾放工具
170．．．基板
172．．．底層填充材料
176．．．晶粒至晶圓封裝
178．．．底邊增進互連結構
180．．．絕緣層或鈍化層
182．．．導體層
184．．．球狀的丸體或凸塊
188．．．囊封劑或模造化合物
190‧‧‧囊封劑或模造化合物
192‧‧‧切晶保護膠帶
194‧‧‧鋸片或雷射裁切工具
196‧‧‧晶粒裝配件
198‧‧‧拾放工具
200‧‧‧晶粒至晶圓封裝
202‧‧‧基板
204‧‧‧底層填充材料
210‧‧‧半導體晶圓
212‧‧‧研磨機平台
214‧‧‧溝槽或通道
216‧‧‧頂表面
218‧‧‧裁切輪
220‧‧‧保護材料
224‧‧‧滴塗機
226‧‧‧研磨機
228‧‧‧背表面
230‧‧‧切晶保護膠帶
232‧‧‧鋸片或雷射裁切工具
圖1所示的係一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c所示的係被鑲嵌至該印刷電路板的代表性半導體封裝的進一步細節；
圖3a至3j所示的係用以在堆疊於一半導體晶圓上的半導體晶粒之間形成保護材料的製程，以便在切割期間減少缺陷；
圖4a至4c所示的係半導體晶粒與晶圓上的互連結構的進一步細節；
圖5所示的係具有增進互連結構的晶粒至晶圓封裝；
圖6a至6e所示的係用以在堆疊於一半導體晶圓上的半導體晶粒之間形成保護材料的另一種製程，以便在切割期間減少缺陷；以及
圖7a至7e所示的係被沉積在形成於一半導體晶圓中的通道上方的保護材料，以便在背研磨期間保護該等通道。
126．．．半導體晶粒或組件
128．．．主動表面
130．．．直通矽晶穿孔(TSV)
132．．．凸塊或互連線
136．．．凸塊或互連線
138．．．背表面
146．．．半導體晶粒或組件
148．．．主動表面
149．．．凸塊
150．．．底層填充材料
172．．．底層填充材料
176．．．晶粒至晶圓封裝
178．．．底邊增進互連結構
180．．．絕緣層或鈍化層
182．．．導體層
184．．．球狀的丸體或凸塊
188．．．囊封劑或模造化合物

Claims (8)

  1. 一種製造半導體裝置的方法，其包括：提供一半導體晶圓，其包含複數個第一半導體晶粒；將複數個第二半導體晶粒鑲嵌至該半導體晶圓的一表面；在該第二半導體晶粒及該半導體晶圓的表面上方形成一保護材料；將該第二半導體晶粒之間的該半導體晶圓切割成個別的晶粒至晶圓封裝，每一個晶粒至晶圓封裝皆含有堆疊在該第一半導體晶粒上的該第二半導體晶粒，該保護材料會在切割期間保護該半導體晶圓；以及在切割之後，自該第二半導體晶粒及該半導體晶圓的表面上方移除該保護材料。
  2. 如申請專利範圍第1項的方法，其進一步包含：在該第一半導體晶粒的上方形成一增進互連結構；以及在該第一半導體晶粒、第二半導體晶粒以及增進互連結構的上方沉積一囊封劑。
  3. 如申請專利範圍第1項的方法，其進一步包含將該晶粒至晶圓封裝鑲嵌至一基板。
  4. 如申請專利範圍第1項的方法，其進一步包含：在該第一半導體晶粒的下方沉積一第一底層填充材料；以及在該第二半導體晶粒的下方沉積一第二底層填充材 料。
  5. 一種製造半導體裝置的方法，其包括：提供一半導體晶圓；在該半導體晶圓的一第一表面中形成複數條通道；在該半導體晶圓的該第一表面中的該等通道的上方及之間沉積一保護材料；研磨該半導體晶圓的一第二表面，用以降低該半導體晶圓的厚度，該第二表面和該半導體晶圓的該第一表面反向，該保護材料會在研磨期間保護該通道；以及自該通道之間移除該保護材料。
  6. 如申請專利範圍第5項的方法，其進一步包含利用去離子水來移除該保護材料。
  7. 如申請專利範圍第5項的方法，其進一步包含在移除該保護材料之前切割該半導體晶圓。
  8. 如申請專利範圍第5項的方法，其中，該保護材料包含聚乙烯醇和水。
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