CN102136457A - 在半导体管芯之间形成保护材料的半导体器件和方法 - Google Patents

在半导体管芯之间形成保护材料的半导体器件和方法 Download PDF

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Publication number
CN102136457A
CN102136457A CN2010105423610A CN201010542361A CN102136457A CN 102136457 A CN102136457 A CN 102136457A CN 2010105423610 A CN2010105423610 A CN 2010105423610A CN 201010542361 A CN201010542361 A CN 201010542361A CN 102136457 A CN102136457 A CN 102136457A
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semiconductor
wafer
semiconductor element
protective material
semiconductor wafer
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CN102136457B (zh
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林宅基
尹慈恩
李成尹
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在半导体管芯之间形成保护材料的半导体器件和方法。半导体晶片包含第一半导体管芯。形成贯穿半导体晶片的TSV。第二半导体管芯安装到半导体晶片的第一表面。第一胶带被施加到半导体晶片的第二表面上。在该第二半导体管芯和晶片的第一表面上形成保护材料。保护材料可以是密封剂或者聚乙烯醇和水。在第二管芯之间将晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一管芯上的第二管芯。所述保护材料在单颗化期间保护该晶片。该管芯到晶片封装可以安装到衬底。可以在管芯到晶片封装上形成内建互连结构。可以去除所述保护材料。可以在第一和第二管芯之下沉积底部填充材料。在管芯到晶片封装上沉积密封剂。

Description

在半导体管芯之间形成保护材料的半导体器件和方法
技术领域
本发明大体上涉及半导体器件，并且更具体地涉及在堆叠在半导体晶片上的半导体管芯之间形成保护材料以在单颗化（singulation）期间减少缺陷的半导体器件和方法。
背景技术
半导体器件普遍存在于现代电子产品中。半导体器件在电部件的数量和密度方面变化。分立半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百到几百万个电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种各样的功能，诸如高速计算、发射和接收电池信号、控制电子器件、把太阳光转换成电力以及为电视显示器创建视觉投影。半导体器件存在于娱乐、通信、功率变换、网络、计算机和消费品中。半导体器件也存在于军事应用、航空、汽车、工业控制器和办公设备中。
半导体器件利用半导体材料的电学属性。半导体材料的原子结构允许通过施加电场或基极电流或者通过掺杂工艺来操纵其电导率。掺杂将杂质引入到半导体材料中以操纵和控制半导体器件的电导率。
半导体器件包含有源和无源电结构。包括双极型和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和电场或基极电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构产生为执行各种电功能所需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺（即前端制造和后端制造）进行制造，每个制造工艺可能涉及几百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地完全相同并且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片中单颗化个别管芯以及封装该管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是产生更小的半导体器件。更小的半导体器件典型地消耗更少的功率，具有更高的性能，并且可以被更高效地生产。另外，更小的半导体器件具有更小的占位面积（footprint），这对于更小的终端产品而言是所期望的。更小的管芯大小可以通过前端工艺的改进（导致管芯具有更小的、更高密度的有源和无源部件）来获得。后端工艺可以通过电互连和封装材料的改进而导致具有更小占位面积的半导体器件。
在管芯到晶片（D2W）封装中，多个半导体管芯安装到半导体晶片的表面。在所安装的半导体管芯之间的晶片的部分典型地未被支撑，即在所安装的管芯之间存在空气空间。在真空卡片处理期间，在晶片中，尤其是在所安装的半导体管芯之间的晶片的未支撑部分中，可能形成晶片凹陷。硅灰尘以及其他污染物积聚在所安装的半导体管芯之间的空气空间中并且接合到半导体晶片的背表面。用锯条从所安装的半导体管芯之间的背表面中单颗化半导体晶片。锯条的切割操纵可能引起从晶片单颗化的管芯的顶部、底部和侧面的碎屑或龟裂。对单颗化的管芯的顶部、底部和侧面的单颗化损坏可能造成器件缺陷和故障。
发明内容
存在对单颗化D2W封装而不损坏被单颗化管芯的需要。因而，在一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：提供包含多个第一半导体管芯的半导体晶片；把多个第二半导体管芯安装到该半导体晶片的第一表面；在与该半导体晶片的第一表面相对的该半导体晶片的第二表面上放置第一胶带；在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料，去除第一胶带；以及将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一半导体管芯上的第二半导体管芯。所述保护材料在单颗化期间保护该半导体晶片。该方法还包括将该管芯到晶片封装安装到衬底、去除所述保护材料以及在所述管芯到晶片封装和衬底上沉积密封剂的步骤。
在另一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：提供包含多个第一半导体管芯的半导体晶片；把多个第二半导体管芯安装到该半导体晶片的第一表面；在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料；以及将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一半导体管芯上的第二半导体管芯。所述保护材料在单颗化期间保护该半导体晶片。
在另一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：提供半导体晶片；在该半导体晶片的第一表面中形成多个沟道；在该半导体晶片的第一表面中的所述沟道之上和之间沉积保护层；以及研磨与该半导体晶片的第一表面相对的该半导体晶片的第二表面以减小该半导体晶片的厚度。所述保护材料在研磨期间保护所述沟道。
在另一个实施例中，本发明是一种由包括以下步骤的工艺制成的半导体器件：提供包含多个第一半导体管芯的半导体晶片；把多个第二半导体管芯安装到该半导体晶片的第一表面；在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料；以及将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一半导体管芯上的第二半导体管芯。所述保护材料在单颗化期间保护该半导体晶片。
附图说明
图1示出具有安装到其表面的不同类型的封装的PCB；
图2a-2c示出安装到PCB的代表性半导体封装的进一步细节；
图3a-3j示出在半导体晶体上堆叠的半导体管芯之间形成保护材料以在单颗化期间减少缺陷的工艺；
图4a-4c示出晶片和半导体管芯上的互连结构的进一步细节；
图5示出具有内建互连结构的D2W封装；
图6a-6e示出在半导体晶体上堆叠的半导体管芯之间形成保护材料以在单颗化期间减少缺陷的另一种工艺；以及
图7a-7e示出为了在后研磨期间保护沟道而在形成在半导体晶片中的沟道上沉积的保护材料。
具体实施方式
本发明是参考附图在以下描述的一个或多个实施例中描述的，其中同样的数字代表相同或类似的元件。虽然本发明是按照用于获得本发明目标的最佳模式描述的，但是本领域的技术人员会明白其旨在覆盖如可以被包括在如以下公开和附图所支持的所附权利要求书及其等价物所定义的发明的精神和范围内的更改、修改和等价物。
一般使用两个复杂的制造工艺来制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的管芯包含有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，诸如晶体管和二极管，具有控制电流流动的能力。无源电部件，诸如电容器、电感器、电阻器和变压器，产生为执行电路功能所需的电压和电流之间的关系。
无源和有源部件通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤而形成在半导体晶片的表面上。掺杂通过诸如离子注入或热扩散之类的技术而把杂质引入到半导体材料中。掺杂工艺修改有源器件中半导体材料的电导率，从而把半导体材料转换成绝缘体、导体或者响应于电场或基极电流而动态改变半导体材料电导率。晶体管包含为使得晶体管能够在电场或基极电流的施加下促进或限制电流流动而需要布置的变化掺杂类型和程度的区域。
有源和无源部件由具有不同电属性的材料层形成。这些层可以通过部分由被沉积的材料类型所确定的各种沉积技术形成。例如，薄膜沉积可以涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀以及化学电镀工艺。每层一般被图案化以形成各部分的有源部件、无源部件或部件之间的电连接。
这些层可以使用光刻来图案化，所述光刻涉及在要图案化的层上沉积光敏材料（例如，光致抗蚀剂）。使用光把图案从光掩模转移到光致抗蚀剂。经受光的光致抗蚀剂图案的部分使用溶剂来去除，暴露要图案化的底层的部分。光致抗蚀剂的其余部分被去除，留下图案化后的层。可选地，一些类型的材料通过把该材料直接沉积到由先前沉积/蚀刻工艺使用诸如化学和电解电镀之类的技术而形成的区域或空隙中进行图案化。
在现有图案上沉积薄膜材料可能扩大底下图案并且产生不均匀的平坦表面。为产生较小且更密集的有源和无源部件而要求均匀的平坦表面。平坦化可以用来从晶片的表面去除材料并且产生均匀的平坦表面。平坦化涉及用抛光垫片对晶片的表面进行抛光。在抛光期间研磨材料和腐蚀性化学制剂被添加到晶片的表面。组合的、磨料的机械作用和化学制剂的腐蚀作用去除任何不规则形貌，导致均匀的平坦表面。
后端制造指的是把完成的晶片切割或单颗化成个别管芯并且然后对管芯进行封装以用于结构支撑和环境隔离。为了单颗化管芯，晶片沿被称作划片街区（saw street）或划线的晶片的非功能区域被刻痕并切断。使用激光切割工具或锯刀来单颗化晶片。在单颗化后，个别管芯被安装到包括用于与其他系统部件互连的管脚或接触垫的封装衬底上。在半导体管芯上形成的接触垫然后连接到封装内的接触垫。电连接可以用焊料凸点、柱形凸点、导电胶或引线接合制成。密封剂或其他模制材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中并且使半导体器件的功能性可用于其他系统部件。
图1示出具有在其表面上安装有多个半导体封装的芯片载体衬底或印刷电路板（PCB）52的电子器件50。电子器件50可以根据应用而具有一种类型的半导体封装或者多种类型的半导体封装。为了说明目的而在图1中示出不同类型的半导体封装。
电子器件50可以是独立式系统，其使用半导体封装来执行一个或多个电功能。可选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是图形卡、网络接口卡或者其他可以插入到计算机中的信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或者其他半导体管芯或电部件。
在图1中，PCB 52提供用于安装在PCB上的半导体封装的结构支撑和电互连的一般衬底。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺来把导电信号迹线54形成在表面上或在各层PCB 52内。信号迹线54提供每个半导体封装、所安装部件以及其他外部系统部件之间的电通信。迹线54也提供到每个半导体封装的电源和地连接。
在一些实施例中，半导体器件具有两个封装等级。一级封装是一种用于把半导体管芯机械且电气地附着到中间载体的技术。二级封装涉及把中间载体机械且电气地附着到PCB。在其他实施例中，半导体器件可以只有一级封装，其中管芯被机械且电气地直接安装到PCB。
为了说明的目的，在PCB 52上示出包括引线接合封装56和倒装芯片58的若干类型的一级封装。另外，示出安装在PCB 52上的包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插式封装（DIP）64、连接盘网格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70和四方扁平封装72的若干类型的二级封装。根据系统要求，配有一级和二级封装方式的任何组合的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以把预制部件合并到电子器件和系统中。因为半导体封装包括复杂的功能性，所以可以使用较廉价的部件和流水线的制造工艺来制造电子器件。所得到的器件不太可能故障并且制造较便宜，导致消费者的更低成本。
图2a-2c示出示例性半导体封装。图2a示出安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，其包含模拟或数字电路，所述模拟或数字电路被实施为形成在管芯内的并且根据管芯的电气设计进行电互连的有源器件、无源器件、导电层和介质层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及其他形成在半导体管芯74的有源区域内的电路元件。接触垫76是一层或多层导电材料，诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag），并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，半导体管芯74使用金硅共晶层或粘合剂材料（诸如热环氧树脂）而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和引线接合82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上以通过防止湿气和颗粒进入封装并且污染管芯74或引线接合82来实现环境保护。
图2b示出安装在PCB 52上的BCC 62的进一步细节。使用底部填充或环氧树脂粘合剂材料92把半导体管芯88安装在载体90上。引线接合94提供接触垫96和98之间的一级封装互连。模制化合物或密封剂100沉积在半导体管芯88和引线接合94上以为器件提供物理支撑和电隔离。使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺来防止氧化，在PCB 52的表面上形成接触垫102。接触垫102电连接到PCB 52中的一条或多条导电信号迹线54。凸点104形成在BCC 62的接触垫98和PCB 52的接触垫102之间。
在图2c中，半导体管芯58通过倒装芯片式一级封装而面朝下地安装到中间载体106。半导体管芯58的有源区域108包含模拟或数字电路，其被实施为根据管芯的电气设计而形成的有源器件、无源器件、导电层和介质层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器和有源区域108内的其他电路元件。半导体管芯58通过凸点110电气且机械地连接到载体106。
BGA 60使用凸点112通过BGA式二级封装而电气且机械地连接到PCB 52。半导体管芯58通过凸点110、信号线114和凸点112而电连接到PCB 52中的导电信号迹线54。模制化合物或封装剂116沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的传导通道的短电传导通路以便减小信号传播距离、降低电容并且改善整体电路性能。在另一个实施例中，半导体管芯58可以在不用中间载体106的情况下使用倒装芯片式一级封装而机械且电气直接连接到PCB 52。
图3a-3j示出针对图1和2a-2c的在半导体晶体上堆叠的半导体管芯之间形成保护材料以在单颗化期间减少缺陷的工艺。在图3a中，胶带122放置在晶片级附着器件或器件夹具120中。胶带122可以是聚合物粘合剂，其是通过旋涂或印刷而沉积的并且可通过光、热或激光释放。可选地，胶带122可以是热环氧树脂、层压聚合物、聚合物复合物或者无机接合化合物。
半导体晶片124被定位在胶带122上。半导体晶片124包含用于结构支撑的基本衬底材料，诸如硅、锗、砷化镓、磷化铟或者碳化硅。多个半导体管芯或部件126形成在由如上面描述的划片街区127分隔的晶片124上。每个半导体晶片126包括有源表面128，其包含被实施为形成在管芯内并根据管芯的电气设计和功能而电互连的有源器件、无源器件、导电层和介质层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管以及其他形成在有源表面128内以实施模拟电路或数字电路（诸如数字信号处理器（DSP）、ASIC、存储器或者其他信号处理电路）的电路元件。半导体管芯126也可以包含用于RF信号处理的IPD、诸如电感器、电容器和电阻器。典型的RF系统要求一个或多个半导体封装中的多个IPD以执行必要的电功能。
使用激光钻孔或蚀刻工艺，诸如深反应离子蚀刻（DRIE），形成贯穿半导体管芯126的多个通孔。这些通孔使用PVD、CVD、电解电镀、化学电镀或者其它合适的金属沉积工艺而被填充有Al、Cu、Sn、Ni、Au、Ag、钛（Ti）、W、多晶硅或者其它合适的导电材料以形成导电的硅直通孔（TSV）130。多个凸起或互连132形成在半导体管芯126的有源表面128上的TSV 130之上。图4a示出形成在半导体管芯126的有源表面128上的TSV 130之上的互连132的进一步细节。多个凸起或互连136形成在半导体晶片124的背表面138上的TSV 130之上。图4b示出以螺旋布置形成在半导体管芯126的背表面138上的TSV 130之上的个别互连136的进一步细节。
在图3b中，半导体晶片124安装到晶片夹具120中的胶带122。半导体晶片124的有源表面128接触胶带122，其中凸起或互连132嵌入在胶带中。
在图3c中，使用拾取与放置工具145把半导体管芯或部件146安装到半导体晶片124的背表面138。在一个实施例中，拾取与放置工具145是附着到半导体管芯146的背表面147的计算机控制的真空卡盘。每个半导体管芯146具有有源表面148，其包含被实施为形成在管芯内并根据管芯的电气设计和功能而电互连的有源器件、无源器件、导电层和介质层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管以及其他形成在有源表面148内以实施模拟电路或数字电路（诸如DSP、ASIC、存储器或者其他信号处理电路）的电路元件。半导体管芯146也可以包含用于RF信号处理的IPD、诸如电感器、电容器和电阻器。半导体管芯146的凸点149与互连136对准以通过互连132和136以及TSV 130把半导体管芯146上的电路电连接到对应半导体管芯124上的电路。图4c示出形成在半导体管芯146的有源表面148上的个别互连149的进一步细节。
在图3d中，诸如环氧树脂、聚合物材料、膜或其它非导电材料之类的底部填充材料150使用配送工具152而沉积在半导体管芯146之下。
在图3e中，涂层或保护材料156沉积在半导体管芯146和半导体晶片124上。保护材料156是水溶性的并且在室温下变干。在一个实施例中，保护材料156包含聚乙烯醇和水。保护材料156通过配送器154以及旋涂或其他合适的敷料器（applicator）进行沉积。
在图3f中，在图3a-3e中描述的组件从晶片夹具120中被去除并且用背表面147和保护材料156被安装到切割胶带158。
在图3g中，通过热、光或激光来去除胶带122以暴露互连132。该组件使用锯条或激光切割工具160以2毫米（mm）×120微米（μm）间隙经历切割操作，从而把晶片124单颗化成个别堆叠的半导体管芯126和146。半导体管芯126和146是不同大小的管芯。在一个实施例中，半导体管芯146为4mm×4mm，而半导体管芯126为6mm×6mm。保护材料156支撑半导体晶片124以减小晶片凹陷（dimpling）。另外，保护材料156保护半导体晶片124以便锯条160的切割操作留下光滑的管芯边缘并且减小单颗化期间的晶片碎屑或龟裂。保护材料156也密封半导体管芯146之间的区域并且防止半导体晶片124上污染物的积聚。
在图3h中，通过拾取与放置工具168接触互连132，从胶带158中去除每个包含堆叠的半导体管芯126和146的管芯组件164。
在图3i中，D2W封装164通过朝向衬底的互连132而安装到衬底170。D2W封装164用去离子水进行清洗以去除保护材料156、污染物、碎片以及其他过剩材料。使用配送工具将底部填充材料172，诸如环氧树脂、聚合物材料、膜或者其他不导电材料，沉积在半导体管芯146之下，如图3j所示。在D2W封装164中，半导体管芯146通过TSV 130以及互连132和136而电连接到半导体管芯126。半导体管芯126的侧面相对光滑且没有缺陷，因为在单颗化期间保护材料156保护半导体晶片124。
图5示出类似于图3a-3j中描述的工艺形成的具有底侧内建互连结构178的D2W封装176的可选实施例。绝缘或钝化层180被沉积为一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或者其他具有类似绝缘和结构属性的材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层180。绝缘层180的一部分通过蚀刻工艺来去除。通过PVD、CVD、溅射、电解电镀、化学电镀或者其他合适的金属沉积工艺，使用图案化将导电层182形成为绝缘层180的去除部分中的一层或多层。导电层182可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。导电层182的一部分电连接到互连132。导电层182的其他部分可以根据半导体器件的设计和功能是电公共的或电隔离的。
使用蒸发、电解电镀、化学电镀、球落（ball drop）或丝网印刷工艺，导电凸点材料沉积在内建互连结构178上并且电连接到导电层182。凸点材料可以是具有任选焊剂（flux）溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或者无铅焊料。凸点材料使用合适的附着或接合工艺而接合导电层182。在一个实施例中，凸点材料通过将材料加热到其熔点之上被回流以形成球形球或凸点184。在一些实施例中，凸点184被二次回流以改善到导电层182的电接触。凸点也可以压缩接合到导电层182。凸点184代表可以形成在导电层182上的一种类型的互连结构。该互连结构也可以使用接合线、柱形凸点、微凸点以及其他电互连。
密封剂或模制化合物188使用膏印刷、压缩模制、转移模制、液封模制、旋涂、真空层压或者其他合适的敷料器而沉积在半导体管芯126、半导体管芯146和内建互连结构178上。在一个实施例中，密封剂188使用模套模具(chase mold)进行沉积。密封剂188可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。密封剂188是不导电的并且环境上保护半导体器件不受外部元件影响。
半导体管芯146通过TSV 130以及互连132和136而电连接到半导体管芯126。D2W封装176通过内建互连结构178而电连接到外部器件。因为在单颗化期间保护材料156保护半导体晶片124，半导体管芯126的侧面相对光滑并且没有缺陷。
图6a-6e示出针对图1和2a-2c的在半导体晶体上堆叠的半导体管芯之间沉积保护材料以在单颗化期间减少缺陷的另一种工艺。从图3d继续该实施例，使用膏印刷、压缩模制、转移模制、液封模制、旋涂、真空层压或者其他合适的敷料器将密封剂或模制化合物190沉积为半导体管芯146和半导体晶片124上的保护材料，如图6a所示。密封剂190可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。
在图6b中，图6a中的组件从晶片夹具120中被去除并且用密封剂190被安装到切割胶带192。
在图6c中，通过热、光或激光来去除胶带122以暴露互连132。该组件使用锯条或激光切割工具194以2 mm×120μm间隙经历切割操作，从而把晶片124单颗化成个别堆叠的半导体管芯126和146。密封剂190支撑半导体晶片124以减小晶片凹陷。另外，密封剂190充当半导体晶片124上的保护材料以便锯条160的切割操作留下光滑的管芯边缘并且减小单颗化期间的晶片碎屑或龟裂。密封剂190也密封半导体管芯146之间的区域并且防止半导体晶片124上污染物的积聚。
在图6d中，通过拾取与放置工具198接触互连132，从胶带192中去除每个包含堆叠的半导体管芯126和146的管芯组件196。
在图6e中，D2W封装200通过朝向衬底的互连132而安装到衬底202。使用配送工具使底部填充材料204，诸如环氧树脂、聚合物材料、膜或者其他不导电材料，沉积在半导体管芯146之下。在D2W封装200中，半导体管芯146通过TSV 130以及互连132和136而电连接到半导体管芯126。因为在单颗化期间保护材料190保护半导体晶片124，半导体管芯126的侧面相对光滑且没有缺陷。
在另一个实施例中，保护材料沉积在形成在半导体晶片的表面中的沟道上，如图7a-7e所示。图7a示出放置在研磨器平台212上的半导体晶片210。多个沟槽或沟道214由切割轮218形成在半导体晶片210的顶表面216中。开槽深度是在后研磨操作之后目标晶片厚度的30-50％。例如，如果在后研磨操作之后目标晶片厚度是25μm，则沟道深度为10μm。图7b示出形成在半导体晶片210的顶表面216中的沟道214的进一步细节。沟道214是半导体晶片210的弱点并且可能在后研磨操作期间导致晶片断裂或损坏。
在图7c中，保护材料220沉积在半导体晶片210的顶表面216中的沟道214之上和之间。保护材料220是水溶性的并且在室温下变干。在一个实施例中，保护材料220包含聚乙烯醇和水。保护材料220通过配送器224以及旋涂或其他合适的敷料器进行沉积。
在图7d中，半导体晶片210被颠倒以便保护材料220被定向成面向研磨器平台212。研磨器226去除半导体晶片的背表面228的一部分，大约下至保护材料220。保护材料220防止在研磨工艺期间对顶表面216和沟道214的损坏。
在图7e中，研磨后的半导体晶片210被安装到切割胶带230并且用去离子水来去除保护材料220和其他过剩材料。半导体晶片用锯条或激光切割工具232进行单颗化。
虽然详细示出了本发明的一个或多个实施例，但是本领域技术人员会明白，可以在不偏离如所附权利要求书所述的本发明的范围的情况下做出对那些实施例的修改和变型。

Claims (25)

1. 一种制作半导体器件的方法，包括：
提供包含多个第一半导体管芯的半导体晶片；
把多个第二半导体管芯安装到该半导体晶片的第一表面；
在与该半导体晶片的第一表面相对的该半导体晶片的第二表面上放置第一胶带；
在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料；
去除该第一胶带；
将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一半导体管芯上的第二半导体管芯，所述保护材料在单颗化期间保护该半导体晶片；
将该管芯到晶片封装安装到衬底；
去除所述保护材料；以及
在所述管芯到晶片封装和衬底上沉积密封剂。
2. 权利要求1的方法，还包括形成贯穿半导体晶片的多个导电通孔。
3. 权利要求1的方法，其中所述保护材料包括聚乙烯醇和水。
4. 权利要求1的方法，还包括在第一半导体管芯之下沉积底部填充材料。
5. 权利要求1的方法，还包括在第二半导体管芯之下沉积底部填充材料。
6. 权利要求1的方法，其中所述衬底包括内建互连结构。
7. 一种制作半导体器件的方法，包括：
提供包含多个第一半导体管芯的半导体晶片；
把多个第二半导体管芯安装到该半导体晶片的第一表面；
在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料；以及
将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第一半导体管芯上的第二半导体管芯，所述保护材料在单颗化期间保护该半导体晶片。
8. 权利要求7的方法，其中所述保护材料包括聚乙烯醇和水。
9. 权利要求7的方法，还包括在单颗化后去除所述保护材料。
10. 权利要求7的方法，其中所述保护材料包括密封剂。
11. 权利要求7的方法，还包括：
在第一半导体管芯上形成内建互连结构；以及
在第一半导体管芯、第二半导体管芯和内建互连结构上沉积密封剂。
12. 权利要求7的方法，还包括把所述管芯到晶片封装安装到衬底。
13. 权利要求7的方法，还包括形成贯穿半导体晶片的多个导电通孔。
14. 权利要求7的方法，还包括
在第一半导体管芯之下沉积第一底部填充材料；以及
在第二半导体管芯之下沉积第二底部填充材料。
15. 一种制作半导体器件的方法，包括：
提供半导体晶片；
在该半导体晶片的第一表面中形成多个沟道；
在该半导体晶片的第一表面中的所述沟道之上和之间沉积保护层；以及
研磨与该半导体晶片的第一表面相对的该半导体晶片的第二表面以减小该半导体晶片的厚度，所述保护材料在研磨期间保护所述沟道。
16. 权利要求15的方法，还包括去除所述保护层。
17. 权利要求15的方法，还包括用去离子水来去除所述保护层。
18. 权利要求16的方法，还包括单颗化该半导体晶片。
19. 权利要求15的方法，其中所述保护材料包括聚乙烯醇和水。
20. 一种由包括以下步骤的工艺制成的半导体器件：
提供包含多个第一半导体管芯的半导体晶片；
把多个第二半导体管芯安装到该半导体晶片的第一表面；
在该第二半导体管芯和该半导体晶片的第一表面上形成保护材料；以及
将第二半导体管芯之间的半导体晶片单颗化成个别管芯到晶片封装，每个管芯到晶片封装包含堆叠在第二半导体管芯上的第二半导体管芯，所述保护材料在单颗化期间保护该半导体晶片。
21. 权利要求20的半导体器件，其中所述保护材料包括聚乙烯醇和水。
22. 权利要求20的半导体器件，还包括在单颗化后去除所述保护材料。
23. 权利要求20的半导体器件，其中所述保护材料包括密封剂。
24. 权利要求20的半导体器件，还包括：
在第一半导体管芯上形成内建互连结构；以及
在第一半导体管芯、第二半导体管芯和内建互连结构上沉积密封剂。
25. 权利要求20的半导体器件，还包括形成贯穿半导体晶片的多个导电通孔。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325703A (zh) * 2012-03-23 2013-09-25 台湾积体电路制造股份有限公司 在封装件形成期间探测芯片
CN105118810A (zh) * 2011-09-27 2015-12-02 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN105513975A (zh) * 2016-01-29 2016-04-20 中国电子科技集团公司第四十四研究所 易扩展的集成式光电耦合器及其制作方法
CN108155153A (zh) * 2016-12-05 2018-06-12 台湾积体电路制造股份有限公司 用于散热的封装结构的制造方法
CN108428662A (zh) * 2017-02-15 2018-08-21 英飞凌科技股份有限公司 在芯片制造期间处置薄晶片
CN110015634A (zh) * 2017-11-30 2019-07-16 英飞凌科技股份有限公司 在前端中在晶片级沉积保护材料以进行早期颗粒和水分保护
CN110462813A (zh) * 2017-02-07 2019-11-15 罗茵尼公司 用于堆叠半导体器件的装置和方法
CN111640739A (zh) * 2020-05-29 2020-09-08 青岛歌尔智能传感器有限公司 光学传感器封装结构和电子设备

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8722462B2 (en) * 2010-03-31 2014-05-13 Infineon Technologies Ag Semiconductor package
KR20160075845A (ko) * 2010-03-31 2016-06-29 에베 그룹 에. 탈너 게엠베하 양면에 칩이 장착되는 웨이퍼를 제작하기 위한 방법
DE102011018295B4 (de) * 2011-04-20 2021-06-24 Austriamicrosystems Ag Verfahren zum Schneiden eines Trägers für elektrische Bauelemente
KR101739945B1 (ko) * 2011-05-02 2017-06-09 삼성전자주식회사 반도체 패키지 및 이를 제조하는 방법
US8518796B2 (en) 2012-01-09 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die connection system and method
US9287204B2 (en) * 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
US8907494B2 (en) 2013-03-14 2014-12-09 International Business Machines Corporation Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
US9553070B2 (en) * 2013-04-30 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299686B1 (en) * 2015-01-16 2016-03-29 International Business Machines Corporation Implementing integrated circuit chip attach in three dimensional stack using vapor deposited solder Cu pillars
US9679785B2 (en) * 2015-07-27 2017-06-13 Semtech Corporation Semiconductor device and method of encapsulating semiconductor die
US10192843B1 (en) * 2017-07-26 2019-01-29 Micron Technology, Inc. Methods of making semiconductor device modules with increased yield
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
KR20210096883A (ko) * 2020-01-29 2021-08-06 삼성전자주식회사 반도체 패키지 제조용 프레임 지그, 프레임 지그를 포함하는 반도체 패키지 제조 장치, 및 프레임 지그를 이용한 반도체 패키지 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US20060205182A1 (en) * 2005-03-10 2006-09-14 Nec Electronics Corporation Method for manufacturing semiconductor device
CN101211793A (zh) * 2006-12-26 2008-07-02 矽品精密工业股份有限公司 芯片级封装结构及其制法
US20080318396A1 (en) * 2007-06-21 2008-12-25 Stats Chippac, Ltd. Grooving Bumped Wafer Pre-Underfill System
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US20060205182A1 (en) * 2005-03-10 2006-09-14 Nec Electronics Corporation Method for manufacturing semiconductor device
CN101211793A (zh) * 2006-12-26 2008-07-02 矽品精密工业股份有限公司 芯片级封装结构及其制法
US20080318396A1 (en) * 2007-06-21 2008-12-25 Stats Chippac, Ltd. Grooving Bumped Wafer Pre-Underfill System
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118810A (zh) * 2011-09-27 2015-12-02 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN103325703A (zh) * 2012-03-23 2013-09-25 台湾积体电路制造股份有限公司 在封装件形成期间探测芯片
CN103325703B (zh) * 2012-03-23 2016-01-20 台湾积体电路制造股份有限公司 在封装件形成期间探测芯片
CN105513975A (zh) * 2016-01-29 2016-04-20 中国电子科技集团公司第四十四研究所 易扩展的集成式光电耦合器及其制作方法
CN108155153A (zh) * 2016-12-05 2018-06-12 台湾积体电路制造股份有限公司 用于散热的封装结构的制造方法
CN108155153B (zh) * 2016-12-05 2022-11-11 台湾积体电路制造股份有限公司 半导体装置、管芯堆叠结构、封装结构及其制造方法
CN110462813A (zh) * 2017-02-07 2019-11-15 罗茵尼公司 用于堆叠半导体器件的装置和方法
US11183478B2 (en) 2017-02-07 2021-11-23 Rohinni, LLC Apparatus and method for transferring semiconductor devices from a substrate and stacking semiconductor devices on each other
CN108428662A (zh) * 2017-02-15 2018-08-21 英飞凌科技股份有限公司 在芯片制造期间处置薄晶片
CN110015634A (zh) * 2017-11-30 2019-07-16 英飞凌科技股份有限公司 在前端中在晶片级沉积保护材料以进行早期颗粒和水分保护
CN110015634B (zh) * 2017-11-30 2024-01-19 英飞凌科技股份有限公司 在前端中在晶片级沉积保护材料以进行早期颗粒和水分保护
CN111640739A (zh) * 2020-05-29 2020-09-08 青岛歌尔智能传感器有限公司 光学传感器封装结构和电子设备

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