TWI538169B - Semiconductor memory device - Google Patents

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device and a method of fabricating the same.

In recent years, most electronic devices such as computers can perform desired operations by using various materials. When the material is held in, for example, a semiconductor memory device (also referred to as a memory) or the like, the material can be used temporarily or permanently.

Semiconductor memory devices also include, in a broad sense, external memory devices (auxiliary memory devices) such as hard disks or flexible disks. However, a semiconductor memory device almost always means a semiconductor memory device such as a CPU (Central Processing Unit).

The two main types of semiconductor memory devices are volatile memory and non-volatile memory. Volatile memory means a semiconductor memory device that loses data when power is turned off. In addition, the non-volatile memory is a semiconductor memory device that continues to hold data even after the power is turned off and can hold the data semi-permanently after writing the data.

Although volatile memory has the potential to lose data, it has the advantage of short access times. In addition, although non-volatile memory can retain data, it has disadvantages of high power consumption. In this manner, the semiconductor memory devices each have their own characteristics, and each of the semiconductor memory devices is used in accordance with the type and use of the material.

A variety of non-volatile memory types, such as unwriteable read-only memory (ROM), flash memory that can perform multiple writes and erases, and electronic erasable programmable read-only memory (EEPROM), etc. Among these, a single write memory that can perform only one write is preferable because it is difficult to tamper with the data and can provide high security of the memory.

An example of a single write memory is an anti-melting memory that applies a voltage to both terminals of an element formed using an amorphous germanium to form a germanide and a short circuit in the terminal. In addition, a rewritable memory such as a flash memory or an EEPROM is used, and a memory area in which erasing is not performed is set, whereby in some examples, rewritable memory is logically used as a write-once memory. (See Patent Document 1).

[reference]

Reference 1: Japanese Published Patent Application No. H7-297293

However, in conventional single write memory, there is a problem that high voltage writing is required. A voltage higher than the voltage used for the read operation must be applied to make a permanent change in the memory element of the single write memory. For example, at the time of writing, a silicide type write-once memory using a germanide as a memory element requires a voltage of 6V to 8V, whereas when using a flash memory or an EEPROM as a write-once memory, 15V is required. Voltage to 18V. Therefore, the generation of such a high potential requires a booster circuit; therefore, the power consumption at the time of writing increases. In order to apply a high voltage to the memory element, it is also necessary to apply a high potential voltage to a peripheral circuit such as a decoder at the time of writing. As a result, in order to increase the withstand voltage so that the peripheral circuit can withstand a high voltage, it is necessary to perform an increase in the channel length, form an LDD region, and the like, thus increasing the number of manufacturing steps and hindering high integration.

In some cases, the germanium type write-once memory becomes a semi-short state with high resistance due to the lack of a write voltage or the like (the high resistance makes it impossible to recognize the data by the read operation as a material to be described later). State of 1). The element that becomes a semi-short-circuit state with high resistance is substantially a defective element.

In addition, the single-write memory of the telluride cannot simultaneously write data into a plurality of memory cells, and it is difficult to write data into many memory components in a short time. Further, in the example of the flash memory or the EEPROM, although the data can be simultaneously written into a plurality of memory cells, the writing time is generally about 100 μs.

In a flash memory or EEPROM that can be used as a write-once memory by the operation of a logic circuit, the failure of the logic circuit may cause rewriting of data stored in a single write memory. In particular, this problem easily occurs when a rewritable memory and a write-once memory system in a semiconductor memory device are formed using a memory cell having the same structure. In addition, failure of the logic circuit may occur due to malicious user operations, and the data in a single write to the memory is tampered with.

In view of the above problems, an object of an embodiment of the present invention is to provide a semiconductor memory device without increasing the cost, in which high voltage is not required for writing, defects are unlikely to occur, writing time is short, and data cannot be rewritten. .

An embodiment of the present invention is a semiconductor memory device including a memory device including a diode-connected first transistor and a gate electrode connected to a source electrode of the diode-connected first transistor and a second transistor of one terminal of the drain electrode. It should be noted that a terminal of the source electrode and the drain electrode of the second transistor and a terminal of the diode-connected first transistor and a terminal of the drain electrode form a parasitic capacitance.

Another embodiment of the present invention is a semiconductor memory device including a memory element including a diode-connected first transistor; and a second transistor having a gate connected to the diode-connected first a terminal of the source electrode and the drain electrode of the transistor; and a capacitor connected to a terminal of the source electrode and the drain electrode of the diode-connected first transistor and a gate of the second transistor.

When the second transistor is turned on, that is, a voltage higher than the threshold voltage is applied to its gate, the state in which the data is written is set. When the second transistor is turned off, that is, a voltage lower than the threshold voltage is applied to its gate, the state of the non-written material is set. A source electrode of the diode-connected first transistor and a terminal of the drain electrode serve as an anode. When the channel region of the diode-connected first transistor is formed using an oxide semiconductor, the off-state current can be reduced to less than or equal to 1×10 ^-19 A/μm, further lower than or equal to 1 ×10 ^-20 A/μm. Therefore, the potential of the gate of the second transistor, which is increased by the writing of the data, or the potential of the gate of the second transistor and the capacitor, which is increased by the writing of the data, are less likely to be connected from the diode. The first transistor leaks and maintains the potential of the gate of the second transistor. In other words, a single write of the material can be maintained.

Therefore, the write voltage can be set to a voltage at which the second transistor can be turned on, that is, higher than or equal to the threshold voltage of the second transistor, and the write voltage can be lowered. It is not necessary to set the boost circuit for the write voltage. The power consumption at the time of writing can be reduced, and it is not necessary to increase the channel length and form the LDD region for higher withstand voltage. Therefore, the size of the memory element can be reduced, and a high degree of integration can be achieved.

Unlike the telluride type write-once memory, the memory element can be formed using a transistor; therefore, write defects can be reduced.

In the semiconductor memory device of one embodiment of the present invention, the write time is determined by the on-state current of the diode-connected first transistor and the capacitance of the capacitor, and even the on-state current of the first transistor is When 10 ^-6 A and the capacitor have a capacitance of 1 pF, the data is written in about 1 μs. In addition, writing data to a plurality of memory elements can be performed simultaneously. Therefore, the write time is greatly reduced.

The memory unit included in the semiconductor memory device of one embodiment of the present invention is a write-once memory; therefore, rewriting of data due to a logic circuit failure does not occur. Further, the rewritable memory can be formed only by modifying the layout of the memory elements in the write-once memory; therefore, a semiconductor memory device combining the rewritable memory and the write-once memory can be formed. Therefore, the security of the retained data in the semiconductor memory device can be improved.

At no additional cost, a semiconductor memory device can be formed in which high voltage is not required for writing, defects are unlikely to occur, writing time is short, and data cannot be rewritten.

Hereinafter, embodiments and examples of the invention will be described with reference to the drawings. It is to be understood that the invention is not to be construed as being limited by the scope of the invention, and the details and details of the invention may be varied in various ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be limited to the description of the embodiments and examples below. When the structure of the present invention is described with reference to the drawings, reference numerals indicating the same components are used in different drawings.

It is to be noted that, in some instances, the thickness of the layers and the regions of the various structures shown in the drawings and the like in the embodiments and examples are exaggerated for the sake of simplicity. Thus, embodiments and examples of the invention are not limited to this scale.

It is to be noted that in order to identify components, words having a serial number such as "first", "second", and "third" are used in the specification, and these words do not numerically limit the components.

Further, in many examples, voltage means a potential difference between a specified potential and a reference potential (eg, ground potential). Therefore, the voltage, potential, and potential difference can be referred to as potential, voltage, and voltage difference, respectively.

It should be noted that both the source electrode and the drain electrode in the transistor are connected to the semiconductor layer. When a voltage is applied to the gate electrode, the current flows according to a potential difference between the source electrode and the drain electrode; therefore, the source electrode and the drain electrode can be interchanged with each other depending on the operation, and sometimes it is difficult to recognize the source from the position thereof. Electrode and drain electrodes. Thus, when describing the structure of the transistor, the names "source electrode" and "dip electrode" are used. Another option is to use the name "one of the source and drain electrodes" and "the other of the source and drain electrodes". Another option is to use the names "first electrode" and "second electrode". It should be noted that there is no particular limitation on the meaning based on such a name.

(Example 1)

In this embodiment, the structure of a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. It should be noted that in this embodiment, an n-channel transistor using electrons as a majority carrier is described; needless to say, a p-channel transistor in which a hole is a majority carrier can be used instead of the n-channel transistor.

Each of Figures 1A and 1B illustrates a memory component of an embodiment of the present invention. The memory element 101 shown in FIG. 1A includes a diode-connected transistor 102, a transistor 103, and a capacitor 104. The gate of the transistor 103 is connected to the first electrode of the capacitor 104 and the first electrode of the transistor 102. The second electrode of the transistor 102 is connected to the gate of the transistor 102. Here, the connection region of the gate of the transistor 103, the first electrode of the capacitor 104, and the first electrode of the transistor 102 is referred to as node A, whereas the second electrode of the transistor 102 and its gate connection are connected. The area is called Node B.

In the memory device described in this embodiment, the first electrode of the diode-connected transistor 102 is used as an anode. The channel region of the diode-connected transistor 102 is formed using an oxide semiconductor. The transistor 102 including the oxide semiconductor in the channel region has a low off state current. The transistor 102 is of a diode connection type, and the gate of the transistor 102 is connected to the second electrode of the transistor 102. Therefore, when the transistor 102 is turned on, current flows from the node B to the node A; however, when the transistor 102 is turned off, the current flowing from the node A to the node B is extremely small.

Here, in the memory element 101, the state in which the potential of the node A is low (that is, the transistor 103 is turned off) is the material 0, and the state in which the potential of the node A is high (that is, the transistor 103 is turned on) is the data 1 .

The diode-connected transistor 102 is turned on, and a voltage higher than a threshold voltage of the transistor 103 is charged in the capacitor 104, that is, a voltage at which the transistor 103 is turned on is applied to the node A, whereby the data 1 can be written to the memory. Body element 101.

On the other hand, after the writing of the material is completed, the transistor 102 is turned off. Even when the potential of the gate of the transistor 102 connected to the node B of its second electrode is lowered, the transistor 102 still has a very low off-state current and is a diode-connected type; therefore, current is less likely to be from the transistor. The first electrode of 102 flows to its second electrode. Therefore, the voltage charged in the node A does not decrease, and the voltage of the node A can be maintained for a long period of time. As a result, the written information (data 1) cannot be rewritten, and in fact the memory element 101 can be operated to write to the memory in a single write. It should be noted that the capacitance of the capacitor 104 is appropriately set according to the required data retention time.

It is to be noted that when a parasitic capacitance is formed in the first electrode or the second electrode of the transistor 103 and the first electrode of the diode-connected transistor 102, the capacitor 104 is not necessarily provided. The memory component at that time includes a diode-connected transistor 102 and a transistor 103, and the gate of the transistor 103 is connected to the first electrode of the transistor 102, as shown in FIG. 1B. Further, the second electrode of the transistor 102 is connected to the gate of the transistor 102.

2A and 2B and FIG. 3 each illustrates an embodiment of a memory cell array each having memory elements of the memory elements of FIG. 1A arranged in a matrix.

2A is a diagram of an embodiment of a NOR memory cell array.

The memory unit 110 includes a memory element 111; a transistor 115 having a gate connected to the word line WL1 for writing, a first electrode connected to the memory element 111, and a second electrode connected thereto for writing a bit line BL1; and a transistor 116 having a gate connected to the word line WL2 for reading, a first electrode connected to the bit line BL2 for reading, and a second electrode connected thereto Memory element 111. The transistor 115 is applied to the selected selection transistor, and the transistor 116 is applied to the selected selection transistor.

The memory element 111 includes a diode-connected transistor 112, a transistor 113, and a capacitor 114. The second electrode of the transistor 112 is connected to its gate and to the first electrode of the transistor 115. The gate of the transistor 113 is connected to the first electrode of the capacitor 114 and the first electrode of the transistor 112. Further, the first electrode of the transistor 113 is connected to the second electrode of the transistor 116, and the second electrode of the transistor 113 has a fixed potential. The second electrode of capacitor 114 also has a fixed potential.

2B is a diagram of an embodiment of a NOR memory cell array different from that of FIG. 2A.

The memory unit 130 includes a memory element 131; and a transistor 135 having a gate connected to the word line WL1 for writing, a first electrode connected to the memory element 131, and a second electrode connected thereto for Write bit line BL1. The transistor 135 acts on the selected transistor of the write.

The memory element 131 includes a diode-connected transistor 132, a transistor 133, and a capacitor 134. The second electrode of the transistor 132 is connected to its gate and to the first electrode of the transistor 135. The gate of the transistor 133 is connected to the first electrode of the capacitor 134 and the first electrode of the transistor 132. The first electrode of the transistor 133 is connected to the bit line BL2 for reading, and the second electrode thereof has a fixed potential. The second electrode of capacitor 134 is connected to word line WL2 for reading.

3 is a diagram of an embodiment of a NAND memory cell array.

The memory unit 120 includes a memory element 121; and the transistor 125 has its gate connected to the word line WL for writing; its first electrode is connected to the memory element 12, and its second electrode is connected to be used for writing Enter the bit line BL. The transistor 125 is applied to the selected transistor of the write.

The memory element 121 includes a diode-connected transistor 122, a transistor 123, and a capacitor 124. The second electrode of the transistor 122 is connected to its gate and to the first electrode of the transistor 125. The gate of transistor 123 is coupled to the first electrode of capacitor 124 and the first electrode of transistor 122. The first electrode of the transistor 123 is connected to the data line DL for reading, and the second electrode of the transistor 123 is connected to the first electrode of the transistor 123 of the next line. The second electrode of capacitor 124 has a fixed potential.

The channel regions of the diode-connected transistors 112, 122, and 132 are each formed using an oxide semiconductor. The transistors 112, 122, and 132, each including an oxide semiconductor in the channel region, have a low off state current. The transistors 112, 122, and 132 are diode-connected, and the gates of the transistors 112, 122, and 132 are connected to the second electrodes of the transistors 112, 122, and 132, respectively. Thus, when transistors 112, 122, and 132 are turned on, current flows from node B to node A; however, when transistors 112, 122, and 132 are turned off, very little current flows from node A to node B.

Each of the channel regions of the transistors 113, 115, 116, 123, 125, 133, and 135 may be formed using any one of an amorphous germanium layer, a microcrystalline germanium layer, a poly germanium layer, and a single crystal germanium layer. An oxide semiconductor can be used to form the channel regions of the transistors 113, 115, 116, 123, 125, 133, and 135 in a manner similar to the manner in which the diode-connected transistors 112, 122, and 132 are formed. One.

In the semiconductor memory device described in this embodiment, the channel region of the diode-connected first transistor is formed using an oxide semiconductor, thereby reducing the off-state current to less than or equal to 1×10 ^-19 A. /μm, further lower than or equal to 1 × 10 ^-20 A / μm. Therefore, the gate and the capacitor of the second transistor which are increased by the writing of the data are less likely to leak from the diode-connected first transistor and the potential of the gate of the second transistor can be maintained. In other words, a single write of the material can be maintained.

The data write voltage can be set to a voltage at which the second transistor can be turned on, that is, greater than or equal to a threshold voltage of the second transistor, and the write voltage can be lowered. It is not necessary to set the boost circuit for the write voltage. The power consumption at the time of writing can be reduced, and it is not necessary to increase the channel length and form the LDD region for higher withstand voltage. Therefore, the size of the memory element can be reduced, and a high degree of integration can be achieved.

The write time of the semiconductor memory device described in this embodiment is determined by the on-state current of the diode-connected first transistor and the capacitance of the capacitor, and the current in the on state of the first transistor is 10 ^-6 A. In the example where the capacitance of the capacitor is 1 pF, the writing of the completed data is about 1 μs. In addition, writing data to a plurality of memory elements can be performed simultaneously. Therefore, the write time is greatly reduced.

The memory cells included in the semiconductor memory device described in this embodiment are single-write memories; therefore, data rewriting due to malfunction of logic circuits does not occur. Therefore, the security of the retained data in the semiconductor memory device can be improved.

It should be noted that the memory cell and the memory cell array described in this embodiment are an embodiment, and the structure is not limited thereto.

(Example 2)

In this embodiment, data writing and reading in the semiconductor memory device explained in Embodiment 1 will be described with reference to the drawings.

The data writing in the NOR memory unit 110 shown in Fig. 2A will be explained with reference to Fig. 4A.

First, a first potential is applied to the bit line BL1 for writing and a word line WL1 for writing, and the written bit line BL1 and the word line WL1 for writing are connected to the write data. The memory unit 110, and the bit line BL2 for reading and the word line WL2 for reading are each set at the ground potential. The first potential is the potential of the open transistors 113 and 115. The first potential is a potential higher than the threshold voltage of each of the transistors 113 and 115, and is 2V here.

When the potential of the word line WL1 for writing is the first potential, the transistor 115 and the diode-connected transistor 112 that are applied to the selected selection transistor are turned on, so that the potential of the node A (ie, The potential of the gate of the capacitor 114 and the transistor 113 is increased to be about the same as the potential of the bit line BL1 for writing; therefore, the transistor 113 is turned on. Through the above steps, data 1 can be written.

It should be noted that as long as the charge of the energized crystal 113 is sufficiently charged in the node A for writing the data 1, a boost circuit for writing data is not required, and the write voltage is applied from the power source to the drive memory unit 110. Logic circuit. The time sufficient to charge the capacitor 104 is sufficient as the writing time; therefore, when the on-state currents of the transistors 112 and 115 are 10 ^-6 A and the capacitance of the capacitor 114 is 1 pF, the data is completed in a very short time of about 1 μs. Write.

After the completion of the data writing, the potential of the bit line BL1 for writing and the potential of the word line WL1 for writing are 0 V as shown in Fig. 4B. Therefore, although the transistor 115 and the diode-connected transistor 112 that are applied to the selected selection transistor are turned off, the off-state current of the transistor 112 formed using the oxide semiconductor is very low; therefore, the node The voltage of A is maintained for a long period of time. In particular, it is preferable that the off-state current of the transistor 112 formed using the oxide semiconductor is lower than or equal to 1 × 10 ^-19 A / μm, and lower than or equal to 1 × 10 ^-20 A / μm. Therefore, when a capacitance of 1 pF is added to the capacitor 114, the data can be held for 20 days to 200 days, and the memory element 111 is charged as a write-once memory. It should be noted that "holding data" herein means that the potential of the capacitor 114 is greater than or equal to 90% of the potential when the data 1 is written, that is, greater than or equal to 1.8V.

Next, the material reading in the memory unit 110 shown in FIG. 2A will be described with reference to FIGS. 5A and 5B. FIG. 5A illustrates a method for reading data 1, and FIG. 5B illustrates a method for reading material 0. At the time of reading the data, the potential of the word line WL2 for reading is changed to turn on the transistor 116 charged to the selected selection transistor, so that the output from the reading circuit 117 is used for reading. The voltage of the bit line BL2 is determined. It should be noted that at the time of reading, the bit line BL1 for writing and the word line WL1 for writing are each set at the ground potential, and the transistors 112 and 115 are turned off.

In the example of reading the material 1, the second potential is applied to the word line WL2 for reading which belongs to the line in which the material is read, and the crystal 116 is normally turned on as shown in Fig. 5A. The third potential of the negative potential is also applied to the word line WL2 for reading which belongs to the line in which the data is not read. The second potential is the potential of the open transistor 116. The second potential is set to be higher than the threshold voltage of the transistor 116, here 2V. In the example of the data 1, the transistor 113 is turned on; therefore, the output from the read circuit 117 is the resistor of the resistor (also referred to as R1) included in the read circuit 117 and the turn-on resistance of the transistor 113. It is determined by comparison with the sum of the on-resistances of the transistors 116. Here, when the resistance of the resistor R1 in the reading circuit is higher than the sum of the on-resistance of the transistor 113 and the on-resistance of the transistor 116, the potential of the node C for reading the bit line BL2 is about 0V. The potential of the node C is inverted by the inverter 118 included in the reading circuit 117 to be output as the material 1.

In the example of reading data 0, the second potential is applied to the word line WL2 for reading, and the crystal 116 is generally turned on as shown in FIG. 5B. In the example of the data 0, the transistor 113 is turned off; therefore, the output from the read circuit 117 is passed through the resistor of the resistor R1 included in the read circuit 117 and the turn-off resistance of the transistor 113 and the transistor 116. The comparison between the sum of the on-resistances is determined. Here, when the resistance of the resistor R1 included in the reading circuit 117 is lower than the sum of the closing resistance of the transistor 113 and the on-resistance of the transistor 116, the bit line for reading is read by the reading circuit 117. The potential of the node C of BL2 is set to be about 2V. The potential is inverted by the inverter 118 included in the reading circuit 117 to be output as the material 0.

It is to be noted that in the memory cell belonging to the row in which the material is not read, the third potential of the negative potential is applied to the word line WL2 for reading. The third potential is to turn off the potential of the transistor 116. The third potential is a negative potential lower than the threshold voltage of the transistor 116, here -2V. The transistor 116 is turned off. Therefore, it is impossible to read the data in the memory unit in which the data is not selected for reading.

Next, the writing and reading of the material in the NOR memory unit 130 shown in FIG. 2B according to Embodiment 1 will be described with reference to the drawings.

First, the writing of the material in the NOR memory unit 130 shown in Fig. 2B will be explained with reference to Fig. 6 .

First, the first potential is applied to the bit line BL1 for writing belonging to the memory unit 130 to be written and the word line WL1 for writing, and the word line WL2 for reading is Set at ground potential. The first potential is the potential of the open transistors 133 and 135. The first potential is a potential higher than the threshold voltage of each of the transistors 133 and 135, and is 2V here.

When the potential for the write word line WL1 and the write bit line BL1 is the first potential, the transistor 135 and the diode-connected transistor 132 are turned on, so that in the node A (ie, The gate of the capacitor 134 and the transistor 133 charges the charge, and the potential is increased to be about the same as the potential of the bit line BL1 for writing; therefore, the transistor 133 is turned on. Through the above steps, data 1 can be written.

After the writing of the material is completed, the potential of the bit line BL1 for writing and the potential of the word line WL1 for writing are 0V. Therefore, although the transistor 135 and the diode-connected transistor 132 charged to the selected transistor are turned off, the off-state current of the transistor 132 formed using the oxide semiconductor is very low; therefore, the node The voltage of A is maintained for a long period of time. As a result, the memory element 131 is charged as a single write memory.

Next, the reading of the material in the memory unit 130 shown in FIG. 2B will be described with reference to FIGS. 7A and 7B. FIG. 7A illustrates a method for reading data 1, and FIG. 7B illustrates a method for reading material 0. At the time of reading the data, the potential of the word line WL2 for reading is changed, and the data is read according to the voltage of the bit line BL2 for reading.

In the example of reading the data 1, the word line WL2 for reading which belongs to the line in which the data is read is set at the ground potential, and the other word line WL2 for reading is set as shown in Fig. 7A. The third potential of the negative potential is shown.

When the material 1 is stored in the memory unit 130 in which the material is read (ie, the first voltage is charged in the capacitor 134 of the memory unit 130), the transistor 133 is turned on, and the bit line BL2 for reading is used. The potential of node C is about 0V. The potential of the node C is inverted by the inverter included in the reading circuit 117 to be output as the material 1.

In the example of reading the data 0, the word line WL2 for reading which belongs to the line in which the data is read is set at the ground potential, and the other word line WL2 for reading is set as shown in Fig. 7B. The third potential of the negative potential is shown.

When the material 0 is stored in the memory unit 130 in which the material is read (i.e., the charge is not charged in the capacitor 134 of the memory unit 130), the transistor 133 is turned off, and is read by the read circuit 117. The potential of the node C of the bit line BL2 is about 2V. The potential is inverted by the inverter included in the reading circuit 117 to be output as data 0.

It is to be noted that the third potential of the negative potential is applied to the word line WL2 for reading in the memory cell belonging to the row in which the data is not read. The potential of the capacitor 134 of the memory cell is the value at which the third potential is added to the potential stored in the node A. Since the third potential is a negative potential, the potential of the capacitor 134 of the memory cell is lowered, and the transistor 133 is turned off regardless of the data written to the memory cell. Therefore, it is impossible to read the data in the memory unit that is not selected for reading.

Next, writing and reading of materials in the NAND memory unit 120 shown in FIG. 3 according to Embodiment 1 will be described with reference to the drawings.

The writing of the material in the NAND memory unit 120 shown in FIG. 3 will be explained with reference to FIG.

First, the first potential is applied to the bit line BL and the word line WL belonging to the memory unit 120 to which data is written. The first potential is the potential of the open transistors 123 and 125. The second electrode of the capacitor 124 that is not connected to the transistors 123 and 125 is at ground potential.

When the potential of the word line WL for writing is the first potential, the transistor 125 and the diode-connected transistor 122 are turned on, so that the potential of the node A (i.e., the gate of the capacitor 124 and the transistor 123) The potential is increased to be about the same as the potential of the bit line BL for writing; therefore, the transistor 123 is turned on. Through the above steps, data 1 can be written.

After the writing of the material is completed, the potential of the bit line BL for writing is 0V. Therefore, although the transistor 125 and the diode-connected transistor 122 that are applied to the selected transistor are turned off, the off-state current of the transistor 122 formed using the oxide semiconductor is very low; therefore, the node The voltage of A is maintained for a long period of time. As a result, the memory element 121 acts as a write-once memory.

Next, the reading of the material in the memory unit 120 shown in FIG. 3 will be described with reference to FIGS. 9A and 9B. FIG. 9A illustrates a method for reading data 1, and FIG. 9B illustrates a method for reading material 0. Reading of the material is performed in such a manner that a voltage is applied to all of the second electrodes of the capacitor 124. All of the second electrodes of capacitor 124 are electrodes of transistor 123 that are not connected to all of the memory cells connected to the specified bit line in capacitor 124 included in memory cell 120 included in region 129. The ground potential is applied to the second electrode of the capacitor 124 of the memory cell belonging to the line from which the data is read, and the fourth potential is applied to the second electrode of the other capacitor 124 of the memory cell included in the region 129, And the output from the read circuit 117 is determined according to the voltage of the bit line BL for reading. The fourth potential is a potential higher than the threshold voltage of the transistor 123, and the fourth potential here is 2V.

In the example of reading the material 1, the charge is stored in the capacitor 124 of the memory cell in which the material is read, and the first potential is applied to the first electrode of the capacitor 124 as shown in Fig. 9A. Therefore, when the second electrode of the capacitor 124 is at the ground potential, the transistor 123 is turned on. Conversely, when a fourth potential is applied to the second electrode of the capacitor 124 of the memory cell that is not read and in the region 129, the potential of the first electrode of the capacitor 124 is increased, whereby the transistor 123 is turned on. As a result, all of the transistors 123 connected to the data line DL are turned on, and the potential of the node C of the data line DL is 0V. The potential of the node C is inverted by the inverter included in the reading circuit 117 to be output as the material 1.

In the example of reading data 0, the first electrode of the capacitor 124 of the memory unit 120 in which the data is read is 0V, as shown in Fig. 9B. Therefore, the transistor 123 of the memory cell in which the data is read is turned off. On the other hand, when the fourth potential is applied to the second electrode of the capacitor 124 of the memory cell in which the data in the region 129 is not read, the potential of the first electrode of the capacitor 124 is increased, whereby the transistor 123 is turned on. As a result, due to the reading circuit 117, the potential of the node C of the data line DL is set to about 2V.

According to this embodiment, a semiconductor memory device can be provided in which high voltage is not required for writing, defects are unlikely to occur, writing time is short, and data cannot be rewritten.

(Example 3)

In this embodiment, an embodiment of the semiconductor memory device described in Embodiments 1 and 2 will be described with reference to the drawings.

FIG. 10A is an example of a semiconductor memory device including the memory cell array described in the first embodiment. The semiconductor memory device 300 includes a memory cell array 301, a row decoder 302, a column decoder 303, and an interface circuit 304. The memory cell array 301 includes a plurality of memory cells 305 arranged in a matrix.

The interface circuit 304 generates signals for driving the row decoder 302 and the column decoder 303 from external signals, and outputs data read from the memory unit 305 to the outside.

Row decoder 302 receives signals from interface circuit 304 for driving memory unit 305 and generates signals for writing or reading to be transmitted to the bit lines. The column decoder 303 receives signals from the interface circuit 304 for driving the memory cells 305 and generates signals for writing or reading to be transferred to the word lines. The memory unit that performs the access in the memory cell array 301 can be uniquely determined by the signal to be input from the row decoder 302 to the bit line and the signal to be input from the column decoder 303 to the word line.

Further, as shown in FIG. 10B, a semiconductor memory device including a memory cell array in which the write-once memory and the rewritable memory described in Embodiment 1 and Embodiment 2 are combined can be formed. The semiconductor memory device 310 shown in FIG. 10B includes a first memory cell array 311, a second memory cell array 312, a row decoder 302, a column decoder 303, and an interface circuit 304. In the first memory cell array 311, the memory cells 313 each having the write-once memory described in the first embodiment and the second embodiment are arranged in a matrix. In the second memory cell array 312, the memory cells 314 each having a rewritable memory element are arranged in a matrix.

The rewritable memory device can be formed by the same processing as the processing of the write-once memory described in the first embodiment and the second embodiment. The structure of the rewritable memory element will be described with reference to FIGS. 11A and 11B.

11A is a diagram of a memory cell and a memory cell array having a NOR-type rewritable memory device. The memory unit 400 includes a memory element 401; a transistor 402 having a gate connected to the word line WL1 for writing, a first electrode connected to the memory element 401, and a second electrode connected thereto for writing a bit line BL1; and a transistor 406 having a gate connected to the word line WL2 for reading, a first electrode connected to the bit line BL2 for reading, and a second electrode connected thereto Memory element 401. The transistor 406 acts on the selected transistor of the read.

The memory element 401 includes a transistor 403 and a capacitor 404. The gate of transistor 403 is coupled to the first electrode of capacitor 404 and the first electrode of transistor 402. Further, the first electrode of the transistor 403 is connected to the second electrode of the transistor 406, and the second electrode of the transistor 403 has a fixed potential. The second electrode of capacitor 404 also has a fixed potential.

The transistor 402 is formed using an oxide semiconductor in a manner similar to the transistor 102 described in the first embodiment. The transistors 403 and 406 can be formed in a manner similar to the mode of the transistor 103 described in the first embodiment.

The writing of the material in the NOR memory unit 400 shown in Fig. 11A will be described with reference to Figs. 12A and 12B. FIG. 12A illustrates a method for writing material 1, and FIG. 12B illustrates a method for writing material 0.

In the example of writing the material 1 as shown in FIG. 12A, the first potential is applied to the bit line BL1 for writing and the word line for writing connected to the memory unit 400 to which the material is written. WL1, and the word line WL2 for reading have a ground potential. The first potential is the potential of the turn-on crystals 402 and 403 and greater than the threshold voltage of each of the transistors 402 and 403, and is 2V here.

When the potential of the word line WL1 for writing is the first potential, the transistor 402 is turned on, and the potential of the node A (i.e., the potential of the gate of the capacitor 404 and the transistor 403) is increased to be used for writing. The potential of the bit line BL1 is about the same potential, whereby the transistor 403 is turned on. With the above steps, data 1 can be written.

In the example of writing data 0 as shown in FIG. 12B, the bit line BL1 for writing connected to the memory cell 400 to which the material is written has a ground potential, and the first potential is applied to the writing for writing. The word line WL1, and the word line WL2 for reading have a ground potential. The first potential is the potential of the open-on crystal 402 and above the threshold voltage of the transistor 402, and here is 2V.

When the potential of the word line WL1 for writing is the first potential, the transistor 402 is turned on, and the potential of the node A (i.e., the potential of the capacitor 404 and the potential of the gate of the transistor 403) is lowered to the ground potential. The potential of the bit line BL1 for writing. As such, transistor 403 is turned off and data 0 can be written. It should be noted that in order to prevent unwanted data reading, the word line WL2 used for reading can have a ground potential and the transistor 406 is turned off during the write cycle.

Next, the reading of the material in the memory unit 400 shown in Fig. 11A will be described with reference to Figs. 13A and 13B. FIG. 13A illustrates a method for reading data 1, and FIG. 13B illustrates a method for reading material 0. When the data is read, the potential of the word line WL2 for reading is changed, the transistor 406 for charging the selected selection transistor is turned on, and the output from the reading circuit 117 is used for reading. The voltage of the bit line BL2 is determined.

In the example of reading the material 1 as shown in Fig. 13A, the second potential is applied to the word line WL2 for reading belonging to the line on which the material is read, and the transistor 406 is turned on. In the example of the material 1, the transistor 403 is turned on; therefore, it is used for reading in a manner similar to the reading method of the NOR type single write memory element shown in FIG. 2A of Embodiment 2. The node C of the bit line BL2 has a ground potential. The potential of the node C is inverted by the inverter included in the reading circuit 117, and is output as the material 1.

In the example of writing the material 0 as shown in Fig. 13B, the second potential is applied to the word line WL2 for reading, and the transistor 406 is turned on. In the example of the material 0, the transistor 403 is turned off; therefore, due to the read circuit 117, the bit line BL2 for reading is set to about 2V. The potential is inverted by the inverter included in the read circuit 117, and is output as data 0.

It should be noted that in the memory cell in which the data of the row is not read, the third potential of the negative potential is applied to the word line WL2 for reading. The third potential is the potential to turn off the transistor 406 and is a negative potential lower than the threshold voltage of the transistor 406, and here is -2V. The transistor 406 is turned off. Therefore, it is impossible to read the data in the memory unit of the read of the unselected material.

Figure 11B is a diagram of a memory cell of a NOR-type rewritable memory element including the memory cell of Figure 11A. The memory cell shown in Fig. 11B has a structure including a transistor 405 between the transistor 402 and a bit line BL1 for writing, as shown in Fig. 11A. In this configuration, the gate connection of the transistor 112 described in Embodiment 1 is changed, and the gate is connected only to the word line WL1 for writing. In other words, with a slight change in writing, the rewritable memory can be substituted for the write-once memory, or the rewritable memory can be replaced by the write-once memory. Since the method for writing data and the method for reading data are the same as those of FIG. 11A, they are omitted.

It is to be noted that, in this embodiment, the write-once memory and the rewritable memory element are of the NOR type; however, the NAND type can be suitably used.

In this way, the write-once memory and the rewritable memory can be placed on the same semiconductor memory device. The rewritable memory system can be formed by the same processing as that of the write-once memory described in Embodiments 1 and 2, and a write-once memory can be used as the write-once memory and Rewritable memory can be used as rewritable memory without having to rely on the operation of logic signals. Therefore, it is possible to provide a semiconductor memory device in which rewriting of data due to malfunction of the logic circuit does not occur in principle.

(Example 4)

In this embodiment, the structure of the semiconductor memory device described in Embodiments 1 to 3 and a method of manufacturing the same will be described with reference to FIGS. 14, 15, and 16A to 16E.

In this embodiment, the configuration of the semiconductor memory device described in Embodiment 1 will be described using a plan view and a cross-sectional view, and the structure can be suitably applied to Embodiment 2 and Embodiment 3.

14 is an embodiment of a plan view of the memory cell 110 in the semiconductor memory device described in the first embodiment, and FIG. 15 is a cross-sectional view taken along line A-B, C-D, and E-F of FIG.

The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2A, the transistor 503 corresponds to the transistor 116 shown in FIG. 2A, and the diode-connected transistor 505 corresponds to the diode shown in FIG. 2A. The body-connected transistor 112, and the transistor 506 correspond to the transistor 115 shown in FIG. 2A. Further, capacitor 504 corresponds to capacitor 114 shown in FIG. 2A.

Although all of the transistors herein are n-channel transistors, it is needless to say that a p-channel transistor can be used. Further, the technical essence of the present invention disclosed herein is to form a channel region of the diode-connected transistor 505 using an oxide semiconductor layer; therefore, the unique structure of the semiconductor memory device is not necessarily limited to the structure described herein.

As shown in FIG. 15, the transistor 502 and the capacitor 504 are disposed over the insulating layer 510 and the insulating layer 512 stacked on the substrate 508; the transistor 505 is disposed on the stacked insulating layer 510, the insulating layer 512, and the insulating layer. 536, an insulating layer 538, and an insulating layer 540.

The semiconductor memory device described in this embodiment includes a transistor 502, a transistor 503 (not shown), a capacitor 504, and a transistor 506 (not shown) at the lower portion, and a diode-connected transistor 505 at the upper portion. It should be noted that the capacitor 504 can be disposed at the upper portion instead of at the lower portion.

The transistor 502 includes a semiconductor layer 519 formed over the insulating layer 512, a gate insulating layer 522 disposed over the semiconductor layer 519, a gate electrode 526 disposed over the gate insulating layer 522, and electrically connected to the semiconductor Wiring 534a and 534b of layer 519. The semiconductor layer 519 is formed with a channel region 514, and a low concentration impurity region 516 and a high concentration impurity region 518 (which are also collectively referred to as impurity regions) to sandwich the channel region 514.

Here, the sidewall insulating layer 530 is disposed on the side surface of the gate electrode 526. In addition, the sidewall insulating layer 530 overlaps with the low concentration impurity region 516.

The capacitor 504 includes a semiconductor layer 502 formed over the insulating layer 512 and having a high concentration impurity region; a gate insulating layer 524 disposed over the semiconductor layer 520; and a capacitor electrode 528 disposed on the gate insulating layer 524 Above; wiring 534c, electrically connected to semiconductor layer 520; and wiring 534b, connected to capacitor electrode 528. Here, the sidewall insulating layer 532 is disposed on the side surface of the capacitor electrode 528.

An insulating layer 536, an insulating layer 538, and an insulating layer 540 are disposed to cover the transistor 502 and the capacitor 504.

The diode-connected transistor 505 includes an oxide semiconductor layer 542 electrically connected to a wiring 534c and a wiring 534d provided over the insulating layer 540, a gate insulating layer 544 covering the wiring 534c, the wiring 534d, and an oxide semiconductor. A layer 542; and a gate electrode 546a are disposed over the gate insulating layer 544 and overlap the oxide semiconductor layer 542. In addition, the gate electrode 546a seals the opening formed in the gate insulating layer 544, and the gate electrode 546a is electrically connected to the wiring 534d to be in a diode-connected type.

An insulating layer 552 and an insulating layer 554 are disposed to cover the transistor 505.

Further, as shown in FIG. 14, the wiring 546b serves as a ground wiring, and the wiring 564b is electrically connected to the wiring 534a of the transistor 502 via an opening formed in the gate insulating layer 544. The capacitor electrode 528 is electrically connected to the wiring 534a; therefore, the capacitor electrode 528 of the capacitor 504 is electrically connected to the wiring 546b.

Via the openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540, the wiring 534a is electrically connected to the high concentration impurity region 518 and the capacitor electrode 528 of the capacitor 504. The wiring 534b is electrically connected to the high concentration impurity region 518 via openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. Via the openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540, the wiring 534c is electrically connected to the semiconductor layer 520 of the high-concentration impurity semiconductor and the gate electrode 526 of the transistor 502 (see FIG. 14).

Further, as shown in FIG. 14, the wiring 534d is electrically connected to the high concentration impurity region of the transistor 506 via the openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540, and is electrically connected to the oxide semiconductor layer of the crystal 505. 542. The wiring 534e is electrically connected to the high concentration impurity region of the transistor 506 via openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. The wiring 534f is electrically connected to the high concentration impurity region of the transistor 503 via openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.

The substrate 208 must have a heat resistance that is at least sufficient to withstand the heat treatment performed later. When a glass substrate is used as the substrate 508, it is preferred to use a glass substrate having a strain point higher than or equal to 730 °C. As the glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or bismuth borate glass is used. It is to be noted that it is preferred to use a glass substrate containing BaO and B ₂ O ₃ such that the amount of BaO is larger than the amount of B ₂ O ₃ .

Instead of the glass substrate, a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate or the like can be used. Alternatively, crystallized glass or the like can be used. Alternatively, a semiconductor substrate such as a germanium wafer whose surface is provided with an insulating layer, or a conductive substrate whose surface is formed of a metal material provided with an insulating layer may be used. Alternatively, a plastic substrate can be used. It should be noted that in the example in which a plastic substrate is used for the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510.

The insulating layer 510 is preferably formed using a nitride insulating layer, and the insulating layer 512 is preferably formed using an oxide insulating layer. As the nitride insulating layer, there are a tantalum nitride layer, a hafnium oxynitride layer, an aluminum nitride layer, and the like. As the oxide insulating layer, there are a ruthenium oxide layer, a ruthenium oxynitride layer, an aluminum oxide layer, and the like.

The semiconductor layer 519 of the transistor 502 of the high-concentration impurity semiconductor and the semiconductor layer 520 of the capacitor 504 may be formed using an amorphous germanium layer, a microcrystalline germanium layer, a polycrystalline germanium layer, or a single crystal germanium layer. It should be noted that, as a transistor in which a single crystal germanium layer is used for a channel region, in addition to a single crystal semiconductor substrate used for a transistor in a channel region, a single crystal germanium layer formed using a channel region can be used. A transistor formed by a so-called insulator-on-wafer (SOI) substrate on an insulating region. Alternatively, the semiconductor layer 519 of the transistor 502 can be formed using an oxide semiconductor layer similar to the oxide semiconductor layer in the diode-connected transistor 505 to be described.

The gate insulating layer 522 and the gate insulating layer 524 may be formed in a single layer or a laminate using a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer, a hafnium oxynitride layer, or an aluminum oxide layer.

Alternatively, the gate insulating layer 522 and the gate insulating layer 524 may be formed using a high-k material such as niobate (HfSiO _x ), nitrogen-added niobate (HfSi _x O _y N _z ) Adding nitrogen yttrium aluminate (HfAl _x O _y N _z ), yttrium oxide, or yttrium oxide to reduce gate leakage current. Alternatively, a stacked structure of one or more of a stacked high-k material and a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer, a hafnium oxynitride layer, an aluminum oxide layer may be used. Each of the gate insulating layer 522 and the gate insulating layer 524 may have a thickness greater than or equal to 10 nm and less than or equal to 300 nm.

The gate electrode 526 and the capacitor electrode 528 may use a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; and a combination of these metal elements Alloys and the like are formed. In addition, one or more metal elements selected from the group consisting of manganese, magnesium, zirconium, and hafnium may be used. In addition, each of the gate electrode 526 and the capacitor electrode 528 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure having an aluminum layer containing germanium; a two layer structure in which a titanium layer is stacked on an aluminum layer; a two layer structure in which a titanium layer is stacked on a titanium nitride layer; and a tungsten layer stacked on a titanium nitride layer The upper two-layer structure; the two-layer structure in which the tungsten layer is stacked on the tantalum nitride layer; and the three-layer structure in which the titanium layer, the aluminum layer, and the titanium layer are stacked in this order. Alternatively, a layer, an alloy layer, or a nitride layer containing aluminum and one or more elements selected from the group consisting of titanium, tantalum, tungsten, molybdenum, chromium, niobium, and tantalum may be used.

Alternatively, the gate electrode 526 and the capacitor electrode 528 may be formed using a light-transmissive conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with cerium oxide. The gate electrode 526 and the capacitor electrode 528 may have a stacked structure having a layer containing the above-described light-transmitting conductive material and a layer containing the above-described metal element.

The sidewall insulating layer 530 and the sidewall insulating layer 532 may be formed using a material similar to the material of the gate insulating layer 522 and the gate insulating layer 524. It should be noted that in order to integrate the transistor and the capacitor, the sidewall insulating layer is not formed in some examples.

The insulating layer 536 and the insulating layer 540 may be formed by a method similar to the method of the gate insulating layer 522 and the gate insulating layer 524. The insulating layer 538 can be formed using an organic resin layer. Examples of the organic resin layer include acrylic acid, epoxy, polyimide, polyamine, polyvinylphenol, and benzocyclobutene. Alternatively, a siloxane polymer can be used.

The wirings 534a to 534f may be formed of a metal element selected from the group consisting of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; and an alloy containing a combination of these metal elements. In addition, one or more metal elements selected from the group consisting of manganese, magnesium, zirconium, and hafnium may be used. In addition, each of the wirings 534a to 534f may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure having an aluminum layer containing germanium; a two layer structure in which a titanium layer is stacked on an aluminum layer; a two layer structure in which a titanium layer is stacked on a titanium nitride layer; and a tungsten layer stacked on a titanium nitride layer The upper two-layer structure; the two-layer structure in which the tungsten layer is stacked on the tantalum nitride layer; and the three-layer structure in which the titanium layer, the aluminum layer, and the titanium layer are stacked in this order. Alternatively, a layer, an alloy layer, or a nitride layer containing aluminum and one or more elements selected from the group consisting of titanium, tantalum, tungsten, molybdenum, chromium, niobium, and tantalum may be used.

Alternatively, the wirings 534a to 534f may be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide-containing Indium tin oxide, indium zinc oxide, or indium tin oxide added with cerium oxide. It is also possible to have a stacked structure having a layer containing the above-mentioned light-transmitting conductive material and a layer containing the above-described metal element.

It is to be noted that the transistor 505 and the transistor 506 may each have a structure similar to that of the transistor 502.

As the oxide semiconductor layer 542, an oxide semiconductor layer using any of the following may be used: a four-component metal oxide such as an In-Sn-Ga-Zn-O-based metal oxide; a three-component metal oxide such as In-Ga-Zn-O-based metal oxide, In-Sn-Zn-O-based metal oxide, In-Al-Zn-O-based metal oxide, Sn-Ga-Zn-O-based metal oxide, Al- Ga-Zn-O-based metal oxide, or Sn-Al-Zn-O-based metal oxide, etc.; or two-component metal oxide such as In-Zn-O-based metal oxide, Sn-Zn-O-based metal oxide A material, an Al—Zn—O-based metal oxide, a Zn—Mg—O-based metal oxide, a Sn—Mg—O-based metal oxide, or an In—Mg—O-based metal oxide. Here, the n-component metal oxide includes an oxide of n kinds of metals. It is to be noted that the oxide semiconductor may contain an element other than the metal oxide of the main component as an impurity, and preferably less than or equal to 1% and less than or equal to 0.1%.

Further, the oxide semiconductor layer 542 can be formed using a three-component metal oxide, and a metal oxide represented by In M _x Zn _Y O _Z ( Y = 0.5 to 5) can be used. Here, M represents one or more elements selected from elements of Group 13 such as gallium (Ga), aluminum (Al), and boron (B). It should be noted that the contents of In, M , Zn, and O can be freely set, and examples include that the M content is zero (ie, X =0). On the other hand, the contents of In and Zn are non-zero. In other words, the above formula includes an In-Ga-Zn-O-based metal oxide, an In-Zn-O-based metal oxide, or the like.

Further, the metal oxide forming the oxide semiconductor layer 542 has an energy band gap of 2 eV or more, 2.5 eV or more, more preferably 3 eV or more.

As the oxide semiconductor layer 542, an oxide semiconductor having an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single crystal structure can be suitably used. Further, an oxide having a crystal whose c-axis is approximately parallel to the direction perpendicular to the surface of the oxide semiconductor can be used.

The oxide semiconductor layer 542 is formed using an i-type or substantially an i-type oxide semiconductor layer. The i-type or substantially i-type oxide semiconductor layer has a carrier density of less than 5 × 10 ¹⁴ /cm ³ , less than 1 × 10 ¹² /cm ^{3 ,} preferably less than or equal to 1 × 10 ¹¹ /cm ^{3 .} it is good. Further, it is preferable that the hydrogen or oxygen which is used as the donor is insufficient and the hydrogen concentration is lower than or equal to 1 × 10 ¹⁶ /cm ³ . It should be noted that the carrier density can be obtained by Hall effect measurement. A lower carrier density can be obtained from measurements measured by capacitance-voltage (CV). The concentration of hydrogen in the oxide semiconductor layer can be measured by a secondary ion mass spectrometer (SIMS).

An i-type or substantially i-type oxide semiconductor layer 542 is used for the channel region of the transistor 505, and the off-state current of the transistor 505 may be lower than or equal to 1 × 10 ^-19 A/μm, further lower than or equal to 1 ×10 ^-20 A/μm. The i-type or substantially i-type oxide semiconductor layer has a wide band gap and electron excitation requires a large amount of thermal energy; therefore, direct recombination and indirect recombination are unlikely to occur. Therefore, in the state where the negative potential is applied to the gate electrode (ie, in the off state), the number of holes of the minority carrier is substantially zero; therefore, direct recombination and indirect recombination are unlikely to occur, and the amount of current is very small. . As a result, in the state where the transistor is in a non-conducting state (also referred to as an OFF state), the circuit can be designed with an oxide semiconductor layer which can be regarded as an insulator. On the other hand, when the transistor is in a conductive state, the current supply capacity of the i-type or substantially i-type oxide semiconductor layer is expected to be higher than the current supply capacity of the semiconductor layer formed of the amorphous germanium. Therefore, in the off state, the transistor 505 functions as a normally off transistor having a very low leakage current, and has excellent switching characteristics.

As the gate insulating layer 544, materials for the gate insulating layer 522 and the gate insulating layer 524 can be suitably used. It is to be noted that, in the example in which the gate insulating layer 544 has a stacked structure, the layer on the side in contact with the oxide semiconductor layer 542 is formed using an oxide insulating layer, whereby oxygen can be supplied to be included in the oxide. The oxygen in the semiconductor layer 542 is insufficient, and the oxide semiconductor layer 542 can be made i-type or substantially i-type oxide semiconductor layer.

The insulating layer 552 and the insulating layer 554 may be formed in a manner similar to the insulating layer 536, the insulating layer 538, or the insulating layer 540.

In this embodiment, the channel region of the diode-connected transistor 505 is formed using an i-type or substantially i-type oxide semiconductor layer; as such, the off-state current can be greatly reduced. Therefore, the voltage applied to the capacitor 504 can be maintained for a long time.

Next, a manufacturing process of the transistor 505 in the semiconductor memory device shown in Fig. 15 will be described with reference to Figs. 16A to 16E. It is to be noted that the known transistor manufacturing process can be suitably utilized for each manufacturing process of the transistor 502, the transistor 503, and the transistor 506.

As shown in FIG. 16A, a wiring 534c and a wiring 534d which serve as a source electrode and a drain electrode of the transistor 505 are formed over the insulating layer 540.

The insulating layer 540 can be formed by a sputtering method, a CVD method, a printing method, a coating method, or the like. Alternatively, a dense high quality insulating layer 540 having a high withstand voltage can be formed by high density plasma enhanced CVD using microwaves (e.g., a frequency of 2.45 GHz). The close contact between the oxide semiconductor layer and the high quality gate insulating layer 540 reduces interface energy states and produces desirable interface characteristics. Furthermore, since the insulating layer 540 formed by high-density plasma enhanced CVD can have a uniform thickness, the insulating layer 540 has excellent step coverage. In addition, the thickness of the insulating layer 540 formed using high-density plasma enhanced CVD can be precisely controlled. It should be noted that the i-type or substantially i-type oxide semiconductor layer is extremely sensitive to the interface energy state or the interface charge; therefore, the use of microwave high-density plasma enhanced CVD to form the insulating layer 540 can reduce the interface energy state and Produces ideal interface properties.

It is to be noted that the substrate 508 is heated when the insulating layer 540 is formed, whereby the amount of hydrogen, water, hydroxide, hydride, and the like included in the insulating layer 540 can be reduced.

In addition, in the example in which the insulating layer 540 is formed by sputtering, it is preferable to form the insulating layer 540 while removing hydrogen, water, hydroxide, hydride, and the like remaining in the processing chamber to reduce inclusion in the insulating layer 540. The amount of hydrogen, water, hydroxide, hydride, and the like. A trapping vacuum pump is used to remove hydrogen, water, hydroxide, hydride, and the like remaining in the processing chamber. Typical examples of trapping vacuum pumps are cryopumps, ion pumps, and titanium sublimation pumps. Alternatively, a turbo pump provided with a condensing trap can be used as the evacuation unit.

The purity of the sputtering gas used when forming the insulating layer 540 is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, 0.1 ppm). Lower or better, whereby the amount of hydrogen, water, hydroxide, hydride, and the like included in the insulating layer 540 can be reduced.

The wiring 534c and the wiring 534d are formed using a sputtering method, an inkjet method, or the like, whereby the number of steps can be reduced. Alternatively, after the conductive layer is formed on the insulating layer 540 by sputtering, CVD, evaporation, or the like, the conductive layer is etched using a mask formed by photolithographic processing as a mask. Thereby, the wiring 534c and the wiring 534d can be formed.

Next, as shown in FIG. 16B, an oxide semiconductor layer 541 is formed over the insulating layer 540, the wiring 534c, and the wiring 534d. The oxide semiconductor layer 541 can be formed by a printing method, an inkjet method, or the like. Alternatively, the oxide semiconductor layer is formed on the insulating layer 540 by sputtering, CVD, coating, pulsed laser evaporation, or the like, and formed by photolithographic processing. The mask etches the oxide semiconductor layer as a mask, whereby the island-type oxide semiconductor layer 541 can be formed.

The carrier density of the oxide semiconductor layer depends on the source gas and the concentration of hydrogen in the target under the deposition conditions and the oxygen concentration therein, the material to be deposited and its composition, heat treatment conditions, and the like. The concentration of hydrogen in the oxide semiconductor layer is lowered, or the concentration of oxygen in the oxide semiconductor layer is increased to reduce oxygen deficiency, whereby the oxide semiconductor layer is made i-type or substantially i-type oxide semiconductor layer. In this embodiment, since the process of making the oxide semiconductor layer i-type or substantially the i-type oxide semiconductor layer is performed later, the oxide semiconductor layer 541 may be an i-type oxide semiconductor layer or an n-type oxide. Semiconductor layer.

It is to be noted that in the example in which the oxide semiconductor layer is formed by sputtering, the substrate is heated, whereby impurities such as hydrogen, water, hydroxide, or hydride included in the oxide semiconductor layer can be reduced. In addition, in the first heat treatment, crystal growth can be promoted.

Further, in the example in which the oxide semiconductor layer is formed by sputtering, the relative density of the metal oxide in the metal oxide target is set to be greater than or equal to 80%, greater than or equal to 95%, preferably greater than or equal to 99.9% is better. Therefore, the impurity concentration in the oxide semiconductor layer can be reduced, and a transistor having excellent electrical characteristics or high reliability can be obtained.

In addition, when the pre-heat treatment is performed before the formation of the oxide semiconductor layer, hydrogen, water, hydroxide, or hydrogenation remaining on the inner wall of the sputtering apparatus, on the surface of the target, or inside the target may be removed. Things and so on. Therefore, impurities such as hydrogen, water, hydroxide, or hydride included in the oxide semiconductor layer can be reduced.

In a manner similar to the manner of the insulating layer 540, a trapping vacuum pump is used to remove hydrogen, water, hydroxide, or hydride remaining in the sputtering apparatus before, during, or after the formation of the oxide semiconductor layer. good. Therefore, hydrogen, water, hydroxide, or hydride or the like is removed, whereby the concentration of hydrogen, water, hydroxide, or hydride or the like included in the oxide semiconductor layer can be reduced.

Next, a first heat treatment is performed to remove impurities such as hydrogen, water, hydroxide, or hydride included in the oxide semiconductor layer. That is, at least one of dehydration or dehydrogenation can be performed. It is to be noted that in the first heat treatment, oxygen deficiency is formed in the oxide semiconductor layer 541.

The temperature of the first heat treatment is preferably higher than or equal to 400 ° C and lower than or equal to 750 ° C, higher than or equal to 400 ° C and lower than the strain point of the substrate. The heat treatment apparatus for the first heat treatment is not limited to a special apparatus, and the apparatus may be provided with means for heating an object to be treated by heat radiation or heat conduction from a heating element such as a resistance heating element. For example, an electric furnace, or a rapid thermal annealing (RTA) device such as a gas rapid thermal annealing (GRTA) device or a lamp rapid thermal annealing (LRTA) may be used as the heat treatment device. The LRTA device is used to heat an object to be treated by radiation (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. device. GRTA equipment is a heat treatment equipment using high temperature gas.

In the first heat treatment, hydrogen, water, hydroxide, hydride or the like is preferably not contained in nitrogen or a rare gas such as helium, neon or argon. Alternatively, the nitrogen introduced into the heat treatment apparatus or the rare gas such as helium, neon or argon may have a purity of 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., The concentration of the impurities is 1 ppm or less, preferably 0.1 ppm or less.

When the temperature is increased in the first heat treatment, the atmosphere in the furnace may be a nitrogen atmosphere, and the atmosphere may be switched to an oxygen atmosphere when cooling is performed. By changing the atmosphere to an oxygen atmosphere after dehydration or dehydrogenation in a nitrogen atmosphere, oxygen can be supplied into the oxide semiconductor layer, so that hydrogen concentration can be reduced and oxygen can be supplied to the oxide semiconductor layer. The oxygen is insufficient; therefore, an i-type or substantially i-type oxide semiconductor layer can be formed.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized into an oxide semiconductor layer including a crystal. For example, in some examples, an oxide semiconductor layer including a crystal having a crystallinity of 90% or more, or 80% or more is formed.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, in some examples, an oxide semiconductor layer having a crystal having a c-axis approximately parallel to a direction perpendicular to the surface is formed in the amorphous oxide semiconductor layer. In the surface part.

Here, the substrate was introduced into an electric furnace, and heat treatment was performed at 450 ° C in an atmosphere of a light gas atmosphere or a rare gas such as a nitrogen atmosphere for one hour.

Next, as shown in FIG. 16C, a gate insulating layer 544 is formed.

The gate insulating layer 544 can be formed in a manner similar to the manner of the insulating layer 540. It is to be noted that when the yttrium oxide layer is formed as the gate insulating layer 544 by sputtering, oxygen can be supplied from the yttrium oxide layer to the oxygen deficiency included in the oxide semiconductor layer 541 and generated by the first heat treatment, The oxygen deficiency which promotes the formation of the donor body can be reduced, and a structure which satisfies the stoichiometric mixture ratio can be formed. As a result, an i-type or substantially i-type oxide semiconductor layer 542 can be formed. The close contact between the oxide semiconductor layer and the high quality insulating layer 540 reduces the interface energy state and produces the desired interface characteristics.

It should be noted that the i-type or substantially i-type oxide semiconductor layer is extremely sensitive to the interface energy state or the interface charge; therefore, the formation of the insulating layer 540 by using high-density plasma enhanced CVD using microwaves can reduce the interface energy. State and produce ideal interface properties.

Then, it is preferred to perform the second heat treatment in a gas atmosphere or an oxygen atmosphere (at a temperature higher than or equal to 200 ° C and lower than or equal to 400 ° C, for example, higher than or equal to 250 ° C and lower than or equal to 350 ° C temperature). The second heat treatment may be performed after the protective insulating layer or the planarized insulating layer is formed over the gate insulating layer 544. By the heat treatment, oxygen can be supplied from the oxide insulating layer of the gate insulating layer 544 to the oxygen deficiency included in the oxide semiconductor layer and generated by the first heat treatment, and oxygen deficiency which promotes formation of the donor body can be reduced, and formation can be formed. A structure that satisfies the stoichiometric mixture ratio. As a result, an i-type or substantially i-type oxide semiconductor layer 542 can be formed.

In this embodiment, the second heat treatment can be performed in a nitrogen atmosphere at 250 ° C for one hour.

Next, as shown in FIG. 16D, after the opening is formed in the gate insulating layer 544, the gate electrode 546a is formed over the gate insulating layer 544 and the wiring 534d. Through the above steps, the gate electrode 546a and the wiring 534d can be formed into a diode-connected transistor. The gate electrode 546a can be formed in a manner similar to the manner of the wiring 534c and the wiring 534d.

Next, as shown in FIG. 16E, an insulating layer 552 and an insulating layer 554 are formed over the gate insulating layer 544 and the gate electrode 546a.

Further, the heat treatment may be performed in air at a temperature higher than or equal to 100 ° C and lower than or equal to 200 ° C for longer than or equal to 1 hour and shorter than or equal to 30 hours. The heat treatment can improve the reliability of the transistor.

It is to be noted that, in FIGS. 16A to 16E, the oxide semiconductor layer 541 is formed after the wiring 534c and the wiring 534d are formed; however, the wiring 534c and the wiring 534d may be formed after the oxide semiconductor layer 541 is formed in the insulating layer 540.

In FIGS. 16A to 16E, a gate electrode 546a may be formed over the insulating layer 540, a gate insulating layer 544 is formed over the gate electrode 546a, and an oxide semiconductor layer 541 is formed over the gate insulating layer 544. And a wiring which serves as a source electrode and a drain electrode is formed on the oxide semiconductor layer 541. In that example, one of the wirings serving as the source electrode and the drain electrode is electrically connected to the wiring 534c. Further, the other of the wirings serving as the source electrode and the drain electrode is electrically connected to the gate electrode 546a.

Through the above steps, a transistor 505 having a channel region including an i-type or substantially i-type oxide semiconductor layer and having a very low off-state current can be formed.

(Example 5)

In this embodiment, an embodiment of an RFID tag including the semiconductor memory device described in Embodiments 1 to 4 will be described with reference to the drawings.

The circuit shown in Figure 17 is an RFID tag. Radio frequency identification (RFID: Non-contact automatic identification technology using radio frequency) has the ability to read stored information without contact, without battery operation, and excellent durability and weather resistance. The reason why the battery is not required to operate is that radio waves (including operation commands, etc.) received by the antenna included in the RFID tag are rectified in the circuit, so that electric power can be generated. In an RFID tag, a memory that can be written or rewritten by a user is frequently set to improve its function.

The RFID tag 1520 includes an antenna circuit 1521 and a signal generating circuit 1522. The signal generating circuit 1522 includes a rectifier circuit 1523, a power supply circuit 1524, a demodulation circuit 1525, an oscillator circuit 1526, a logic circuit 1527, a memory control circuit 1528, a memory circuit 1529, a logic circuit 1530, an amplifier 1531, and a modulation. Circuit 1532. The memory circuit 1529 includes the semiconductor memory device of any of the above embodiments.

The communication signal received by the antenna circuit 1521 is input to the demodulation circuit 1525. The frequency of the received communication signal (i.e., the frequency of the signal transmitted and received between the antenna circuit 1521 and the reader/writer) is, for example, 13.56 MHz, 915 MHz in the UHF (Ultra High Frequency) band, or 2.45 GHz, which is determined according to ISO standards and so on. Needless to say, the frequency of signals transmitted and received between the antenna circuit 1521 and the reader/writer is not limited thereto, and for example, any of the following frequencies may be used: sub-millimeter wave 300 GHz to 3 THz , 30 GHz to 300 GHz for millimeter waves, 3 GHz to 30 GHz for microwaves, 300 MHz to 3 GHz for ultra high frequencies, and 30 MHz to 300 MHz for UHF. In addition, the signals transmitted and received between the antenna circuit 1521 and the reader/writer are signals obtained by modulating the carrier. The carrier system is modulated by analog modulation or digital modulation, and any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum can be used. It is preferred to use amplitude modulation or frequency modulation.

The oscillating signal output from the oscillator circuit 1526 is supplied as a clock signal to the logic circuit 1527. Further, the carrier that has been modulated is demodulated in the demodulation circuit 1525. The demodulated signal is passed to logic circuit 1527 and analyzed. The signal analyzed in logic circuit 1527 is passed to memory control circuit 1528. The memory control circuit 1528 controls the memory circuit 1529, retrieves the data stored in the memory circuit 1529, and transfers the data to the logic circuit 1530. The signal sent to logic circuit 1530 is amplified by amplifier 1531 after being encoded by logic circuit 1530, utilizing the signal amplified by amplifier 1531, and modulation circuit 1532 modulates the carrier. The reader/writer recognizes the signal from the RFIF tag 1520 by the modulated carrier.

The carrier input to the rectifier circuit 1523 is rectified and input to the power supply circuit 1524. The power supply voltage obtained in this manner is supplied from the power supply circuit 1524 to the demodulation circuit 1525, the oscillator circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, and the amplifier 1531. Variable circuit 1532 and so on.

The connection between the signal processing circuit 1522 and the antenna in the antenna circuit 1521 is not particularly limited. For example, the antenna and signal processing circuit 1522 are connected by wire bonding or bumper connections. Alternatively, the signal processing circuit 1522 is formed to have a wafer shape, and a surface thereof is used as an electrode and attached to the antenna. The signal processing circuit 1522 and the antenna can be attached to each other by using an anisotropic conductive film (ACF).

The antenna is stacked on the same substrate as the signal processing circuit 1522 or formed as an external antenna. Needless to say, the antenna is placed above or below the signal processing circuit.

The rectifier circuit 1523 converts the AC signal induced by the carrier received by the antenna circuit 1521 into a DC signal.

The RFID tag 1520 can include a battery 1581 as shown in FIG. When the supply voltage output from the rectifier circuit 1523 is not high enough to operate the signal processing circuit 1522, the battery 1581 also supplies the supply voltage to the various circuits of the signal processing circuit 1522, such as the demodulation circuit 1525, the oscillator circuit 1526, and the logic. Circuit 1527, memory control circuit 1528, memory circuit 1529, logic circuit 1530, amplifier 1531, modulation circuit 1532, and the like.

The remaining voltage output from the supply voltage of the rectifier circuit 1523 can be charged in the battery 1581. When the antenna circuit and the rectifier circuit are disposed in the RFID tag in addition to the antenna circuit 1521 and the rectifier circuit 1523, the energy stored in the battery 1581 can be obtained from a randomly generated battery wave or the like.

The battery is charged with electricity so that the RFID tag can be used continuously. As the battery, a battery formed into a sheet shape can be used. For example, reduction in battery size can be achieved by using a lithium polymer battery including a gel electrolyte, a lithium ion battery, a lithium secondary battery, or the like. Further, a nickel-hydrogen battery, a nickel-cadmium battery, a capacitor having a high capacitance, or the like can be used as the battery.

(Example 6)

In this embodiment, an example of use of the RFID tag 1520 described in Embodiment 5 will be described with reference to the drawings.

The RFID tag 1520 can be used for a wide range of uses, and can be used for setting paper money, coins, securities, bearer bonds, vouchers (driver's license, residence permit, etc.; see FIG. 19A), recording media (DVD software, video tape) Etc.; see Figure 19B), containers for packaging objects (wrapping paper, bottles, etc.; see Figure 19C), vehicles (bicycles, etc.; see Figure 19D), personal belongings (bags, glasses, etc.), food, plants , animals, human bodies, clothes, daily necessities, or products such as electronic devices (liquid crystal display devices, EL display devices, television units, mobile phones, etc.); labels for each product (see Figs. 19E and 19F) and the like.

The RFID tag 1520 is secured to the product by mounting on a printed board, attached to the surface of the product, or embedded in the product. For example, the RFID tag 1520 is incorporated in the paper of the book or the organic resin package to be fixed to each object. Because the RFID tag 1520 can be reduced in size, thickness, and weight, it can be secured to the product without damaging the design of the product. In addition, by being provided with the RFID tag 1520, banknotes, coins, securities, bearer bonds, documents, and the like can have an identification function, and the recognition function can be used to prevent counterfeiting. Further, when the RFID tag of the present invention is attached to a container for packaging an object, a recording medium, personal belongings, food, clothes, daily necessities, electronic devices, and the like, a system such as a detection system can be effectively used. By being provided with the RFID tag 1520, the vehicle can also have a higher security such as preventing theft.

[Example 1]

In this example, the data retention time of the memory elements described in Embodiments 1 to 3 was confirmed by circuit simulation, and the results were explained.

20A to 20C illustrate circuit diagrams for simulation and their results. The circuit shown in Fig. 20A is a memory device according to an embodiment of the present invention, and the circuit includes a diode-connected transistor 601, a transistor 602, and a capacitor 603, and Fig. 20B illustrates a circuit equivalent to the simulation of the circuit. The circuit shown in FIG. 20B includes a resistor 611, a transistor 612, a capacitor 613, a resistor 614, and a resistor 615. The resistor 611 is equivalent to the diode-connected transistor 601 in the off state, and the resistor 614 shows the gate leakage component of the transistor 612, and the resistor 615 shows the leakage component between the electrodes of the capacitor 613.

A simulation is assumed assuming that the initial voltage of node A is 2V immediately after the data is written. As the simulation software, Gateway Version 2.6.12.R manufactured by Simucad Design automation Inc. was used. By assuming that the resistor 611 showing the off-state current of the diode-connected transistor 601, the resistor 614 assumed to show the gate leakage component of the transistor 612, and the leakage between the electrodes assumed to be the display capacitor 613 The resistor 615 of the component, the potential of the node A is monotonically reduced over time. The period up to the point when the potential is lowered and the off state of the transistor 612 cannot be held is the period in which the data can be held. In this example, the period up to the point when the voltage is lowered by 10%, that is, to 1.8V, is defined as the period in which the data 1 can be held, that is, the holding time of the material 1.

Under the conditions 1 and 2, the resistance value of the resistor 611 is regarded as the value of the off-state current of the diode-connected transistor 601 in which the oxide semiconductor layer is formed into the channel region. Under the condition 3, the resistance value of the resistor 611 is the value of the off-state current of the diode-connected transistor 601 in which the oxide semiconductor layer is not formed using the channel region.

Condition 1: 2 × 10 ²⁰ Ω (converted to a closed state current of 10 ^-20 A); Condition 2: 2 × 10 ¹⁹ Ω (converted to a closed state current of 10 ^-19 A); and Condition 3: 2 × 10 ⁹ Ω ( The current is converted to the off state 10 ^-9 A); each of the resistance value of the resistor 614 and the resistance value of the resistor 615 is assumed to be as large as 10 times the resistance value of the resistor 611.

Fig. 20C is a graph of simulation results. Fig. 20C is a diagram in which the horizontal axis represents the elapsed time and the vertical axis represents the voltage of the node A. The retention time of data 1 under condition 3 is 176.3 μs, while the retention time of data 1 under condition 1 is 17.63 × 10 ⁶ s (about 200 days), and the retention time of data 1 under condition 2 is 1.763. ×10 ⁶ s (about 20 days). As a result, it was found that when the channel region of the diode-connected transistor 601 is formed using the oxide semiconductor layer, the material 1 can be maintained for a particularly long period or time.

[Example 2]

In this example, the result obtained by measuring the off-state current of the transistor in which the i-type or substantially i-type oxide semiconductor layer is used for the channel region will be explained.

First, a transistor having an extremely large channel width W 1m is prepared, and a closed state current is measured, considering a very low off state current of an i-type or substantially i-type oxide semiconductor layer used for a transistor of a channel region. . Figure 21 is a graph showing the results obtained by measuring the off-state current of a transistor having a channel width W 1m. In Fig. 21, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. In the example where the drain voltage VD is +1 V or +10 V and the gate voltage VG is in the range of -5 V to -20 V, it is found that the off state current of the transistor is lower than or equal to 1 × 10 ^-12 A. Moreover, it was found that the off-state current of the transistor (width per unit channel (1 μm)) was lower than or equal to 1 aA/μm (1 × 10 ^-18 A/μm).

Next, the result obtained by more accurately measuring the off-state current of the transistor using the i-type or substantially i-type oxide semiconductor layer will be explained. As described above, it was found that the off-state current of the transistor in which the i-type or substantially i-type oxide semiconductor layer is used for the channel region is lower than or equal to 1 × 10 ^-12 A. Here, the result obtained by more accurately measuring the off-state current by using the component for characteristic evaluation (this value is lower than or equal to the detection limit of the measuring device of the above measurement).

First, an element for characteristic evaluation of a method for measuring current will be described with reference to FIG.

Among the components for characteristic evaluation shown in Fig. 22, three measurement systems 800 are connected in parallel. Measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. A transistor in which an i-type or substantially i-type oxide semiconductor layer is used for the channel region is used as each of the transistors 804, 805, and 806.

In measurement system 800, one of the source and drain terminals of transistor 804, one of the terminals of capacitor 802, and one of the source and drain terminals of transistor 805 are connected to a power supply. (to supply V2). One of the source terminal and the 汲 terminal of the transistor 804, one of the source terminal and the 汲 terminal of the transistor 808, the other of the terminals of the capacitor 802, and the gate terminal of the transistor 805 are mutually connection. One of the source and drain terminals of transistor 808, one of the source and drain terminals of transistor 806, and the gate terminal of transistor 806 are coupled to a power source (to supply V1). The other of the source terminal and the 汲 terminal of the transistor 805 and the other of the source terminal and the 汲 terminal of the transistor 806 are connected to each other, and the node serves as an output terminal Vout.

A potential Vext_b2 for controlling the on state and the off state of the transistor 804 is supplied to the gate terminal of the transistor 804. A potential Vext_b1 for controlling the on state and the off state of the transistor 808 is supplied to the gate terminal of the transistor 808. The potential Vout is output from the output terminal.

Next, a method of measuring current by using an element for characteristic evaluation will be explained.

First, it is outlined that the potential difference is applied to measure the initialization period of the off-state current. In the initialization period, the potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and the potential V1 is supplied to the node A, which is the source terminal and the terminal terminal connected to the transistor 804. The other of the nodes (i.e., one of the source and drain terminals connected to the transistor 808, the other of the terminals of the capacitor 802, and the node of the gate terminal of the transistor 805). Here, the potential V1 is set to be high, for example. The transistor 804 is turned off.

Thereafter, the potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808, so that the transistor 808 is turned off. After the transistor 808 is turned off, the potential V1 is set to be low. However, the transistor 804 is off. The potential V2 is the same as the potential V2. In this way, the initialization cycle is completed. When the initialization period is completed, a potential difference is generated between one of the source terminal and the drain terminal of the node A and the transistor 804. Further, a potential difference is generated between the source terminal and the gate terminal of the node A and the transistor 808. Therefore, a small amount of charge flows through the transistor 804 and the transistor 808. That is, a closed state current is generated.

Next, the measurement period of the off-state current will be briefly described. During the measurement period, the potential of one of the source terminal and the 汲 terminal of the transistor 804 (ie, V2) and the potential of the source terminal and the 汲 terminal of the transistor 808 (ie, V1) Is set to low. On the other hand, in the measurement period, the potential of the node A is not fixed (the node A is in the floating state). Therefore, the charge flows through the transistor 804, and the amount of charge stored in the node A changes over time. The potential of the node A changes depending on the amount of charge stored in the node A. In other words, the output potential Vout of the output terminal also changes.

Fig. 23 illustrates details (timing chart) of the relationship between the potentials in the initialization period in which the potential difference is applied and the potential in the next measurement period.

In the initialization period, the potential Vext_b2 is set to the potential of the energization crystal 804 (high potential). Thus, the potential of the node A becomes V2, that is, the low potential (VSS). Thereafter, the potential Vext_b2 is set to turn off the potential of the transistor 804 (low potential), thereby turning off the transistor 804. Next, the potential Vext_b1 is set to the potential of the energization crystal 808 (high potential). Thus, the potential of the node A becomes V1, that is, the high potential (VDD). Thereafter, the potential Vext_b1 is set to turn off the potential of the transistor 808. Therefore, node A becomes a floating state, and the initialization cycle is completed.

In the next measurement cycle, the potential V1 and the potential V2 are individually set to the potential of the charge flow to or from the node A. Here, the potential V1 and the potential V2 are at a low potential (VSS). It should be noted that in the timing of measuring the output potential Vout, the output circuit must be operated; thus, in some examples, V1 is temporarily set to a high potential (VDD). The period in which V1 is high (VDD) is set to be short so that the measurement is not affected.

When the potential difference is generated as described above and the measurement period is started, the amount of charge stored in the node A changes with time, thus changing the potential of the node A. This means that the potential of the gate terminal of the transistor 805 changes; thus, the output potential Vout of the output terminal also changes with time.

A method of calculating the off-state current in accordance with the obtained output potential Vout will be described below.

The relationship between the potential VA of the node A and the output potential Vout is obtained in advance before the off-state current is calculated. With this, the potential VA of the node A can be obtained using the output potential Vout. According to the above relationship, the potential VA of the node A can be expressed as a function of the output potential Vout by the following equation.

[Formula 1]

V _A = F ( Vout )

The charge QA of the node A can be expressed by the following equation by using the potential VA of the node A, the capacitance CA connected to the node A, and the constant (const). Here, the capacitance CA connected to the node A is the sum of the capacitance of the capacitor 802 and other capacitances.

[Formula 2]

Q _A = C _A V _A + const

Since the current IA of the node A is obtained by the differentiation of the electric charge flowing to the node A (or the electric charge flowing from the node A) with respect to time, the current IA of the node A is expressed by the following equation.

In this way, the current IA of the node A can be obtained from the capacitance CA connected to the node A and the output potential Vout of the output terminal.

According to the above method, it is possible to measure the leakage current (off state current) flowing between the source and the drain of the transistor in the off state.

In this embodiment, the channel length L having a height of 10μm and the channel width W 50μm purified oxide semiconductor transistor 804 is manufactured, transistor 805, transistor 806, and transistor 808. In each of the parallel-arranged measurement systems 800, the capacitance values of the capacitors 802a, 802b, and 802c are 100 fF, 1 pF, and 3 pF, respectively.

It should be noted that the measurement according to this example is performed assuming that VDD = 5 V and VSS = 0 V are satisfied. In the measurement period, the potential V1 is basically set to VSS, and is set to VDD only in a period of 100 msec every 10 to 300 seconds, and Vout is measured. In addition, the Δt used to calculate the current I flowing through the element is about 30,000 sec.

Fig. 24 is a graph showing the relationship between the elapsed time Time and the output potential Vout in the current measurement. According to Fig. 24, the potential changes with the passage of time.

Figure 25 is a graph showing the off-state current at room temperature (25 ° C) calculated from the above current measurement. Figure 25 is a graph showing the relationship between the source-drain voltage V and the off-state current I. According to Fig. 25, it was found that the off-state current was about 40 zA/μm under the condition that the source-drain voltage was 4 V. In addition, it was found that the off-state current was lower than or equal to 10 zA/μm under the condition that the source-drain voltage was 3.1 V. It should be noted that 1 zA means 10 ^-21 A.

In addition, FIG. 26 is a graph showing the off-state current in an environment of a temperature of 85 ° C calculated based on the above current measurement. Figure 26 is a graph showing the relationship between the source-drain voltage V and the off-state current I in an environment at a temperature of 85 °C. According to Fig. 26, it was found that the off-state current was lower than or equal to 100 zA/μm under the condition that the source-drain voltage was 3.1 V.

According to this example, it is confirmed that in the transistor in which the i-type or substantially i-type oxide semiconductor layer is used for the channel region, the off-state current can be very low. Furthermore, it has been found that in the diode-connected transistors 102, 112, 122, and 132, the off-state current is also very low, in each of the transistors 102, 112, 122, and 132, as in the embodiments 1 to 3. Generally, an i-type or substantially i-type oxide semiconductor layer is used for the channel region.

The application is based on the Japanese Patent Application Serial No. 2010-019386, the entire entire disclosure of which is hereby incorporated by reference.

101. . . Memory component

102. . . Transistor

103. . . Transistor

104. . . Capacitor

110. . . Memory unit

111. . . Memory component

112. . . Transistor

113. . . Transistor

114. . . Capacitor

115. . . Transistor

116. . . Transistor

117. . . Circuit

118. . . inverter

120. . . Memory unit

121. . . Memory component

122. . . Transistor

123. . . Transistor

124. . . Capacitor

125. . . Transistor

129. . . region

130. . . Memory unit

131. . . Memory component

132. . . Transistor

133. . . Transistor

134. . . Capacitor

135. . . Transistor

300. . . Semiconductor memory device

301. . . Memory cell array

302. . . Row decoder

303. . . Column decoder

304. . . Interface circuit

305. . . Memory unit

310. . . Semiconductor memory device

311. . . Memory cell array

312. . . Memory cell array

313. . . Memory unit

314. . . Memory unit

400. . . Memory unit

401. . . Memory component

402. . . Transistor

403. . . Transistor

404. . . Capacitor

405. . . Transistor

406. . . Transistor

502. . . Transistor

503. . . Transistor

504. . . Capacitor

505. . . Transistor

506. . . Transistor

508. . . Substrate

510. . . Insulation

512. . . Insulation

514. . . Channel area

516. . . Low concentration impurity region

518. . . High concentration impurity zone

519. . . Semiconductor layer

520. . . Semiconductor layer

522. . . Gate insulation

524. . . Gate insulation

526. . . Gate electrode

528. . . Capacitor electrode

530. . . Side wall insulation

532. . . Side wall insulation

534a. . . Wiring

534b. . . Wiring

534c. . . Wiring

534d. . . Wiring

534e. . . Wiring

534f. . . Wiring

536. . . Insulation

538. . . Insulation

540. . . Insulation

541. . . Oxide semiconductor layer

542. . . Oxide semiconductor layer

544. . . Gate insulation

546a. . . Gate electrode

546b. . . Wiring

552. . . Insulation

554. . . Insulation

601. . . Transistor

602. . . Transistor

603. . . Capacitor

611. . . Resistor

612. . . Transistor

613. . . Capacitor

614. . . Resistor

615. . . Resistor

800. . . measuring system

802. . . Capacitor

802a. . . Capacitor

802b. . . Capacitor

802c. . . Capacitor

804. . . Transistor

805. . . Transistor

806. . . Transistor

808. . . Transistor

1520. . . Radio frequency identification tag

1521. . . Antenna circuit

1522. . . Signal processing circuit

1523. . . Rectifier circuit

1524. . . Power supply circuit

1525. . . Demodulation circuit

1526. . . Oscillator circuit

1527. . . Logic circuit

1528. . . Memory control circuit

1529. . . Memory circuit

1530. . . Logic circuit

1531. . . Amplifier

1532. . . Modulation circuit

1581. . . battery

1A and 1B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

2A and 2B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

3 is an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

4A and 4B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

5A and 5B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

6 is an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

7A and 7B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

9A and 9B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

10A and 10B are each a block diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

11A and 11B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

12A and 12B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

13A and 13B are each an equivalent circuit diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

Figure 14 is a top plan view of a semiconductor memory device in accordance with an embodiment of the present invention.

Figure 15 is a cross-sectional view of a semiconductor memory device in accordance with an embodiment of the present invention.

16A through 16E are cross-sectional views showing a method of fabricating a semiconductor memory device in accordance with an embodiment of the present invention.

Figure 17 is a diagram of an RFID tag.

Figure 18 is a diagram of an RFID tag.

19A to 19F are diagrams showing an example of application of an RFID tag.

20A to 20C are diagrams showing an equivalent circuit for simulation and a result thereof.

Fig. 21 is a characteristic diagram of a transistor including an oxide semiconductor.

Fig. 22 is a circuit diagram for evaluating characteristics of a transistor including an oxide semiconductor.

Fig. 23 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor.

Fig. 24 is a characteristic diagram of a transistor including an oxide semiconductor.

Fig. 25 is a characteristic diagram of a transistor including an oxide semiconductor.

Fig. 26 is a characteristic diagram of a transistor including an oxide semiconductor.

101. . . Memory component

102. . . Transistor

103. . . Transistor

104. . . Capacitor

Claims (12)

A semiconductor memory device comprising a memory device including a first transistor and a second transistor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor Wherein the source of the first transistor and the other of the drain are electrically connected to a gate of the second transistor, and wherein the first transistor comprises an oxide semiconductor film. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a NAND (reverse) memory. The semiconductor memory device of claim 1, further comprising a read circuit, wherein one of a source and a drain of the second transistor is electrically connected to the read circuit. A semiconductor memory device comprising: a first wiring; a second wiring; a third wiring; and a memory element including a first transistor, a second transistor, a third transistor, and a capacitor, wherein the first battery a gate of the crystal is electrically connected to one of a source and a drain of the first transistor, wherein the source of the first transistor and the other of the drain a gate connected to the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, wherein a source and a drain of the third transistor One of the electrodes is electrically connected to the gate of the first transistor, wherein the source of the third transistor and the other of the drain are electrically connected to the second wiring, wherein the third A gate of the transistor is electrically connected to the third wiring, wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor, and wherein the first transistor comprises an oxide semiconductor film. A semiconductor memory device according to claim 4, further comprising a fourth wiring, wherein the second electrode of the capacitor is electrically connected to the fourth wiring. A semiconductor memory device comprising: a first wiring; a second wiring; a third wiring; and a memory element including a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, wherein the source of the first transistor and the other of the drain are electrically connected to the The gate of the second transistor, Wherein one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, wherein one of the source and the drain of the second transistor is electrically Connecting to one of a source and a drain of the fourth transistor, wherein the source of the fourth transistor and the other of the drain are electrically connected to the first wiring, wherein the third The source of the transistor and the other of the drain are electrically connected to the second wiring, wherein a gate of the third transistor is electrically connected to the third wiring, and wherein the first transistor comprises An oxide semiconductor film. The semiconductor memory device of claim 1 or 6, wherein the memory device further comprises a capacitor, and wherein the first electrode of the capacitor is electrically connected to the gate of the second transistor. The semiconductor memory device of claim 7, wherein the potential of the second electrode of the capacitor is a fixed potential. The semiconductor memory device according to any one of claims 1 to 4, wherein the oxide semiconductor film has a carrier density of less than 5 × 10 ¹⁴ /cm ³ . A semiconductor memory device according to any one of claims 1, 4, and 6, Wherein the second transistor comprises a semiconductor film, and wherein the material included in the semiconductor film is different from the material included in the oxide semiconductor film. The semiconductor memory device according to any one of claims 1, 4, and 6, wherein the semiconductor memory device is a write-once memory. A semiconductor device comprising the semiconductor memory device according to any one of claims 1, 4, and 6.