JP2008211185A - Memory element and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and inexpensively provide a memory element having a high yield. <P>SOLUTION: The memory element has: at least a first conductive layer 110; a second conductive layer 112; and a memory layer 111 sandwiched by the first conductive layer 110 and the second conductive layer 112. The memory layer 111 is configured of nano-particles 114 composed of a conductive material coated with an organic thin film 113, and formed using a liquid discharging method. More concretely, a composition in which the nano-particles 114 composed of the conductive material coated with the organic thin film are dispersed in a solvent is discharged (jetted) as a liquid droplet, and dried to vaporize the solvent, thereby forming the memory layer 111. Writing into the memory element is executed by the application of a voltage to electrically connect the first conductive layer 110 and the second conductive layer 112 via a conductive portion formed by the fusion of the nano-particles 114 composed of the conductive material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory element and a semiconductor device having the memory element.

  In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data operating by converting an electric wave received by an antenna into electric energy by providing an antenna has been underway. Such a semiconductor device is called a wireless chip (also referred to as an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, or an RFID (Radio Frequency Identification)). Has been introduced.

Many of these semiconductor devices currently in practical use have a circuit (also called an IC (Integrated Circuit) chip) using a semiconductor substrate such as silicon and an antenna. The IC chip includes a memory circuit (also referred to as a memory), a control circuit, and the like. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. However, although a silicon substrate is expensive, these semiconductor devices are required to be manufactured at a low cost. This is because small semiconductor devices such as wireless chips are expected to be demanded as disposable products. Therefore, in recent years, organic thin film transistors (hereinafter also referred to as “organic TFTs”) using organic compounds for control circuits, memory circuits, and the like, organic memories, and the like have been actively developed (see, for example, Patent Document 1).
JP 2002-26277 A

  A memory element that functions as a memory part of an organic memory is formed by providing an organic compound layer between a pair of electrodes, and data writing uses changes in electrical characteristics such as resistance value due to voltage application. Such an organic compound layer is often formed by vapor deposition.

  When the vapor deposition method is used, only a part of the vaporized organic compound is used, so that the material utilization efficiency is poor. In addition, since materials that are not used are vaporized, there is a problem that energy consumption in the manufacturing process is large.

  Moreover, when producing an organic memory by the vapor deposition method using a metal mask, the alignment process of the alignment in a metal mask is needed. For this reason, the yield of the product is lowered due to the alignment problem.

  Accordingly, it is an object of the present invention to provide a memory element that has a high yield and is simple and inexpensive. Another object is to provide a semiconductor device including the memory element.

  In the present invention, the memory element includes at least a first conductive layer, a second conductive layer, and a memory layer sandwiched between the first conductive layer and the second conductive layer. The memory layer is composed of nanoparticles made of a conductive material coated with an organic thin film, and can be formed using a wet method. Typically, there are a droplet discharge method, a printing method, and the like, and it is preferable to form using a droplet discharge method. For example, a composition in which nanoparticles made of a conductive material coated with an organic thin film are dispersed in a solvent is ejected (ejected) as droplets, and the solvent is vaporized by drying to form a memory layer. Therefore, the use efficiency of the material can be increased and a memory element can be easily formed. Further, since the yield increases, a memory element can be provided at a low cost.

  In addition, the organic thin film which coat | covers a nanoparticle corresponds to the dispersing agent which has the function to prevent aggregation of a nanoparticle in the composition (it is also called discharge material) discharged, and to disperse | distribute a particle stably, for example, a nanoparticle It is comprised from the substance, surfactant, etc. which can form a coordination bond with the electroconductive material which has. In addition to the conductive nanoparticles, dispersant, and solvent, the discharge material may contain substances (for example, reducing agents), binders, plasticizers, silane coupling agents, and the like used in the preparation of the nanoparticles. . Therefore, the organic thin film that coats the nanoparticles is composed of at least a dispersant, for example, a substance or a surfactant that can form a coordinate bond with the conductive material of the nanoparticles. You may have the substance used at the time of preparation, a binder, a plasticizer, a silane coupling agent, etc.

  By applying a voltage to such a memory element, electrical characteristics of the memory element are changed, and data is written. The electrical characteristics include, for example, a resistance value, and when written, the first conductive layer and the second conductive layer that form a pair pass through a conductive portion formed by fusion of nanoparticles made of a conductive material. Thus, writing is performed using a change in resistance value that is generated when the first conductive layer and the second conductive layer are short-circuited (also referred to as short-circuit).

  Note that the first conductive layer in the memory element before writing is connected to the second conductive layer through a plurality of insulating films made of an organic thin film and a plurality of conductive layers that are conductive materials of nanoparticles. That is, it can be said that the first conductive layer and the second conductive layer are also connected via a plurality of capacitive elements connected in multiple stages. Therefore, it can also be expressed that writing by applying a voltage is performed by destroying the capacitor. In this case, at least the insulating layer is provided more than the third conductive layer.

  In this specification, the writing voltage is not particularly limited as long as it is a voltage that changes the electrical characteristics of the memory element by applying a voltage between the first conductive layer and the second conductive layer. In this specification, the minimum value of the applied voltage required to significantly change the electrical characteristics of the memory element is referred to as a write voltage. The read voltage is an applied voltage used for reading a difference in electrical characteristics between an unwritten element and a written element, and is not particularly limited as long as the voltage does not change the electrical characteristics of the memory element.

  In addition, the first conductive layer and the second conductive layer may be referred to as electrodes.

  One aspect of the present invention includes a first conductive layer, a second conductive layer, a memory layer sandwiched between the first conductive layer and the second conductive layer, and the memory layer is organic A portion composed of nanoparticles made of a conductive material coated with a thin film (also referred to as a second portion) and a conductive portion formed by fusing the nanoparticles (also referred to as a first portion) And the first conductive layer and the second conductive layer are memory elements electrically connected via the conductive portion.

  In the above structure, an insulating layer or a semiconductor layer may be provided between the memory layer and at least one of the first conductive layer and the second conductive layer.

  Note that the memory layer is formed by using, for example, a droplet discharge method. In addition, the insulating layer and the semiconductor layer may be formed by a droplet discharge method. In that case, the insulating layer is preferably formed using an insulating organic compound.

  One embodiment of the present invention may be a semiconductor device in which a plurality of the memory elements are arranged in a matrix. Note that each of the plurality of memory elements may be connected to a thin film transistor.

  According to the present invention, a memory element and a semiconductor device including the memory element can be manufactured easily and with high yield and excellent performance and reliability. Therefore, a memory element and a semiconductor device that are excellent in performance and reliability can be provided at low cost.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
One structural example of the memory element of the present invention will be described with reference to FIG. The memory element illustrated in FIG. 1 includes a first conductive layer 110, a second conductive layer 112, and a memory layer 111 sandwiched between the first conductive layer 110 and the second conductive layer 112. The layer 111 is composed of nanoparticles 114 made of a conductive material covered with an organic thin film 113. Therefore, the second conductive layer 112 is provided on the first conductive layer 110 through a region where insulating films made of the organic thin film 113 and nanoparticles 114 made of a conductive material are alternately arranged. . In other words, the first conductive layer 110 is connected to the second conductive layer 112 through a plurality of alternately conductive films made of the organic thin film 113 and the conductive material of the nanoparticles 114. Thus, the first conductive layer and the second conductive layer can also be expressed as being connected via a multi-layered capacitor element.

  First, the operation mechanism of the memory element of the present invention will be described with reference to FIG. A cross-sectional view of the memory element before writing is shown in FIG. 2A, and a top view and a cross-sectional view of the memory element after writing are shown in FIGS. 2B and 2C, respectively. The memory layer 111 before voltage application, that is, before writing, is composed of nanoparticles 114 made of a conductive material covered with an organic thin film 113. Therefore, the memory layer 111 does not have conductivity, and the resistance value of the memory element is high. When a voltage is applied between the first conductive layer 110 and the second conductive layer 112 of such a memory element, a minute current flows through the memory layer 111 and Joule heat is generated. The organic thin film 113 is decomposed by the Joule heat, and the nanoparticles 114 made of a conductive material come into contact with each other and are fused. Therefore, the resistance of the memory layer 111 is reduced, and the first conductive layer 110 and the second conductive layer 112 are finally connected to each other through the conductive portion 120 formed by fusion as shown in FIG. Are electrically connected, and the storage element is short-circuited. As described above, the resistance value of the memory element changes before and after voltage application.

  Data is written by utilizing the change in the resistance value of the memory element due to the application of voltage from the above operating mechanism.

  Note that the shape of the conductive portion 120 formed in the memory layer 111 after writing is columnar, conical, or spherical. Of course, the shape is not limited to the above-described shape, and any conductive portion 120 may be used as long as it has a function of electrically connecting the first conductive layer 110 and the second conductive layer 112. In addition, since the cross section is formed by fusing nanoparticles made of a conductive material, it is not necessarily symmetrical and may have an irregular shape. For example, depending on the fusion amount of the nanoparticles, the conductive portion 120 as shown in FIG.

  Further, at least one conductive portion 120 is formed in the memory layer 111, and the location thereof is not particularly limited. In addition, the memory layer 111 includes the first conductive layer 110 and the first conductive layer 110, as long as the first conductive layer 110 and the second conductive layer 112 are not electrically connected as illustrated in FIG. The conductive portion 121 may be electrically connected. Of course, the conductive portion 121 is also formed by fusing nanoparticles made of a conductive material, and the shape and quantity of the conductive portion 121 included in the memory layer 111 are not particularly limited.

  Further, no deformation occurs in the second conductive layer 112 after writing, and a constant distance is maintained between the first conductive layer 110 and the second conductive layer 112 even after writing. Therefore, for example, when another layer is provided on the second conductive layer 112, there is no need to worry about peeling of the other layer.

  FIG. 4 shows an example of a top view of the memory layer 111 before and after writing. Note that the top view in FIG. 4 is a cut surface at a half position in the film thickness direction of the memory layer 111, FIG. 4A shows the memory layer 111 before writing, and FIG. 4B shows writing. This is the later memory layer 111. Note that the memory layer 111 is not limited to FIG. 4, and the nanoparticles 114 and the organic thin film 113 may be abbreviated in the drawing.

  Next, materials that can be used for each layer will be described. For the first conductive layer 110 and the second conductive layer 112 in the memory element of the present invention, a highly conductive metal, alloy, compound, or the like having a single layer or a stacked structure can be used.

  For example, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta) and other metals, or nitrides of metal materials (for example, titanium nitride, tungsten nitride, molybdenum nitride) A metal belonging to Group 1 or 2 of the periodic table, ie, an alkali metal such as lithium (Li) or cesium (Cs), an alkaline earth metal such as magnesium (Mg), calcium (Ca), or strontium (Sr), and An alloy containing any of these (for example, Mg: Ag, Al: Li) or the like can be given. Further, rare earth metals such as europium (Er) and ytterbium (Yb) and alloys containing these may be used. Indium tin oxide (hereinafter referred to as ITO) used as a transparent conductive film, indium tin oxide containing silicon, and indium oxide containing 2 to 20 wt% zinc oxide (ZnO) (abbreviation: abbreviation: IZO) or the like can also be used.

  Note that the first conductive layer 110 is formed by vapor deposition, sputtering, CVD, printing, electroplating, electroless plating, spin coating, or the like.

  The second conductive layer 112 can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, or a spin coating method.

  The memory layer 111 is composed of nanoparticles made of a conductive material covered with an organic thin film. The memory layer 111 is formed using a droplet discharge method. The droplet discharge method is a method of forming a pattern by discharging droplets containing a predetermined substance from pores. Here, a composition in which nanoparticles made of a conductive material coated with an organic thin film are dispersed in a solvent The solvent is vaporized by ejecting (spouting) an object as droplets and drying to form the memory layer 111. The thickness of the memory layer 111 is not particularly limited, but is preferably 1 nm to 250 nm. However, if the film thickness is too thick, the behavior may vary depending on the memory element when a voltage is applied. Therefore, it is necessary to set the voltage appropriately taking this into consideration. Note that in the memory element of the present invention, the write voltage can be reduced as the memory layer 111 is thinned.

  The conductive material forming the nanoparticles includes gold (Au), silver (Ag), platinum (Pt), nickel (Ni), copper (Cu), palladium (Pd), tantalum (Ta), iridium (Ir) Metal elements selected from rhodium (Rh), tungsten (W), aluminum (Al), iron (Fe), zinc (Zn), tin (Sn), titanium (Ti), indium (In), etc. An alloy material containing an element as a main component is used. In addition, a metal sulfide of cadmium (Cd), zinc (Zn), germanium (Ge), silicon (Si), zirconium (Zr), barium (Ba), oxides such as the above metal elements, a kind of halide, or A plurality of types may be mixed. In addition, ITO used as a transparent conductive film, indium tin oxide containing silicon, IZO, or the like can be used as the conductive material.

  In the case where two or more elements or compounds are used for the conductive material, the mixed state is not particularly limited. For example, even if each of them is present uniformly, any one is unevenly distributed in the core portion. May be.

  The particle diameter of the nanoparticles is 1 nm or more and 200 nm or less, preferably 1 nm or more and 100 nm or less, and the particle diameter of the nanoparticles contained in the discharge material is preferably uniform.

  The nanoparticles may be formed using any one of a gas phase method, a liquid phase method, and a solid phase method, and the manufacturing method thereof is not particularly limited.

  Depending on the conductive material constituting the nanoparticles, voids may be generated between the particles when a voltage is applied. This is because the crystal growth of the conductive material progressed very quickly, and the generation of such voids can be suppressed by setting the voltage applied to the memory element low and using an alloy material for the nanoparticles. it can. Therefore, a memory element with higher reliability can be obtained.

  The organic thin film which coat | covers a nanoparticle is corresponded to the dispersing agent which has the function to prevent aggregation of a nanoparticle in a solvent and to disperse | distribute a particle stably. Therefore, the compound forming the organic thin film is composed of a substance, a surfactant, or the like that can form a coordinate bond with the metal element of the conductive material. Here, as a substance which forms a coordinate bond with a metal element, an amino group, a thiol group (—SH), a sulfanediyl group (—S—), a hydroxy group (—OH), an oxy group (—O—) , Carboxyl group (—COOH), cyano group (—CN) and the like, and a substance having a lone electron pair possessed by nitrogen, sulfur, oxygen atom and the like. For example, hydroxyamines such as ethanolamine, amine compounds such as polyethyleneimine and polyvinylpyrrolidone, alcohols such as polyvinyl alcohol, alkanethiols, dithiols, glycols such as ethylene glycol, diethylene glycol and polyethylene glycol, polyacrylic acid Or carboxymethylcellulose can be used. Examples of the surfactant include anionic surfactants such as bis (2-ethylhexyl) sulfosuccinic acid and sodium dodecylbenzenesulfonate, and nonionic surfactants such as alkyl esters of polyalkyl glycol and alkylphenyl ether. , Fluorosurfactants, copolymers having polyethyleneimine and polyethylene oxide, and the like can be used. In addition, since the viscosity of a discharge material will become high when a dispersing agent shall be 30 wt% or more with respect to a nanoparticle, 1.0 wt% or more and 30 wt% or less are preferable.

  Nanoparticles made of a conductive material coated with an organic thin film as described above are dispersed in a solvent and discharged. As the solvent, water or an organic solvent can be used, and the organic solvent may be a water-soluble organic solvent or a water-insoluble organic solvent. For example, water-soluble organic solvents include alcohols such as methanol, ethanol, propanol, butyl alcohol, glycerin, dipropylene glycol, ethylene glycol, ketones such as acetone and methyl ethyl ketone, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol Examples thereof include glycol ethers such as monobutyl ether and diethylene glycol monobutyl ether, water-soluble nitrogen-containing organic compounds such as 2-pyrrolidone and N-methylpyrrolidone, and ethyl acetate. Examples of the water-insoluble organic solvent include alkanes such as octane, nonane and decane, aromatics such as cycloalkane, toluene, xylene, benzene and dichlorobenzene. Of course, these solvents do not necessarily need to be used alone, and a plurality of solvents can be mixed and used as long as phase separation does not occur between the solvents.

  Next, one mode of a droplet discharge apparatus used for the droplet discharge method is shown in FIG. The individual heads 205 and 212 of the droplet discharge means 203 are connected to the control means 207, and can be drawn in a preprogrammed pattern by controlling it with the computer 210. The drawing timing may be performed based on, for example, the marker 211 formed on the substrate 200 provided with the memory element. Alternatively, the edge of the substrate 200 may be used as a reference. This reference is detected by the image pickup means 204, and converted into a digital signal by the image processing means 209 is recognized by the computer 210, a control signal is generated and sent to the control means 207. As the imaging means 204, a charge coupled device (CCD), an image sensor using a complementary metal oxide semiconductor, or the like can be used. Information on the pattern to be formed on the substrate 200 is stored in the storage medium 208. Based on this information, a control signal is sent to the control means 207, and the individual heads 205 of the droplet discharge means 203, The head 212 is individually controlled. The material to be discharged is supplied from the material supply source 213 and the material supply source 214 to the head 205 and the head 212 through piping.

  The inside of the head 205 has a structure having a space filled with a liquid material as indicated by a dotted line 206 and a nozzle that is a discharge port. Although not shown here, the head 212 also has the same internal structure as the head 205. For example, different sizes of nozzles in the head 205 and the head 212 can simultaneously draw different materials with different widths. Of course, it is possible to simultaneously draw the same material with different widths.

  In the case of using a large substrate, the head 205 and the head 212 can be freely scanned in the direction of the arrow in the drawing, and the drawing area can be freely set. Therefore, a plurality of the same patterns can be drawn on one substrate. Further, the stage may be moved to freely set the drawing area. Of course, the head and the stage may be moved simultaneously.

  The viscosity of the material to be discharged is preferably 20 mPa · s or less, so that the material can be smoothly discharged from the nozzle. The surface tension of the material to be discharged is preferably 40 mN / m or less. However, the viscosity and the like of the discharge material may be adjusted as appropriate in accordance with the solvent to be used and the application. For example, the viscosity of the discharge material in which gold or silver nanoparticles are dispersed in a solvent may be set to 5 mPa · s or more and 20 mPa · s or less.

  Using such a droplet discharge device, a discharge material in which nanoparticles made of a conductive material coated with an organic thin film in a solvent are dispersed is discharged to a desired position, and then dried to evaporate the solvent. The drying conditions vary depending on the solvent used. For example, when propanol is used as the solvent, the drying may be performed at 100 degrees for about 5 minutes. Note that the time required for drying may be shortened by heating the substrate provided with the first conductive layer 110 during discharge.

  In addition to the conductive material, the dispersant, and the solvent, the discharge material may include a substance used at the time of producing the nanoparticles, a binder, a plasticizer, a silane coupling agent, and the like. As the binder, a thermosetting resin is used, and examples thereof include organic resins such as polyimide, acrylic, novolac resin, melamine resin, phenol resin, epoxy resin, silicone resin, furan resin, and diallyl phthalate resin. In addition, the binder can suppress generation | occurrence | production of the non-uniform | heterogenous melt | fusion part of nanoparticles by the shrinkage force of a thermosetting resin. In addition, the viscosity of the discharge material can be adjusted with such a resin.

  Therefore, the organic thin film covering the nanoparticles constituting the memory layer 111 includes a dispersant, a solvent, a substance (for example, a reducing agent) used when producing the nanoparticles, a binder, a plasticizer, a silane coupling agent, and the like. May be included. Furthermore, the solvent may remain in the organic thin film. As described above, the organic thin film constituting the memory layer 111 is composed of at least a metal element or a surfactant capable of forming a coordinate bond with the metal element included in the nanoparticle, and further the production of the nanoparticle. You may have the substance used sometimes, a binder, a plasticizer, a silane coupling agent, etc.

  Note that although the case where the memory layer 111 is formed using the droplet discharge method has been described above, the discharge layer may be formed using a printing method such as screen printing by increasing the viscosity of the discharge material. Even with the printing method, the use efficiency of the material can be increased compared with the vapor deposition method or the like, and the memory layer 111 can be easily formed. However, the present invention is not limited to these, and other wet methods can be used.

  The first conductive layer 110 and the second conductive layer 112 may also be formed by a droplet discharge method.

  As described above, the memory element of the present invention can be easily manufactured with high yield. In addition, since the memory element of the present invention cannot erase data from a memory element that has been written once, forgery due to rewriting can be prevented. Therefore, a memory element with excellent performance and reliability can be manufactured at low cost.

  Note that the voltage applied to the memory element of the present invention may be higher than that of the second conductive layer 112 in the first conductive layer 110, or may be higher than that of the first conductive layer 110. A higher voltage may be applied to 112.

  In addition, the configuration of the memory element is not limited to that shown in FIG. A memory element illustrated in FIG. 6A includes a first conductive layer 110, a layer 300, a memory layer 111, and a second conductive layer 112. The layer 300 and the memory layer 111 each include a first conductive layer. The memory layer 111 is formed on and in contact with the layer 300. The memory layer 111 is sandwiched between the layer 110 and the second conductive layer 112. Note that there is no particular limitation on the thickness of the layer 300, but it is preferably 0.1 nm or more and 50 nm or less.

The layer 300 is an insulating layer and can be formed using an insulating inorganic or organic compound. For example, as an inorganic compound, lithium oxide (Li ₂ O), sodium oxide (Na ₂ O), potassium oxide (K ₂ O), rubidium oxide (Rb ₂ O), beryllium oxide (BeO), magnesium oxide (MgO), Oxides such as calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), lithium fluoride (LiF), sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), Fluoride such as beryllium fluoride (BeF ₂ ), magnesium fluoride (MgF ₂ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (BaF ₂ ), and other insulating materials Examples thereof include nitrides, chlorides, bromides, iodides, carbonates, sulfates and nitrates. As the organic compound having insulating properties, polyimide, acrylic polymer, polyamide, benzocyclobutene resin, polyester, novolac resin, melamine resin, phenol resin, epoxy resin, silicone resin, furan resin, diallyl phthalate resin, or the like is used. be able to. In addition, a so-called siloxane material in which a main chain is formed by a bond of silicon and oxygen may be used.

  By providing an insulating layer as shown in FIG. 6A, leakage current that flows to an unwritten element when a read voltage is applied can be further reduced. Therefore, power consumption during reading can be reduced.

  Note that the write voltage in the memory element of the present invention can be reduced by making the memory layer 111 thinner as described above. However, although it is possible to reduce the writing voltage if the film is thinned, the leakage current at the time of reading increases if the film is too thin. In such a case, it is particularly effective to provide an insulating layer.

  This insulating layer can be formed using a vapor deposition method, a sputtering method, a CVD method, a printing method, a spin coating method, a sol-gel method, a droplet discharge method, or the like. Among these, it is preferable to form the organic compound having an insulating property by a droplet discharge method. In this case, the insulating layer is formed by discharging a composition obtained by dissolving the organic compound or a reactant thereof in an organic solvent to a desired position and removing the solvent. Therefore, when the insulating layer is formed, the organic solvent used for forming the insulating layer and the solvent that causes phase separation are selected as the solvent of the composition used for forming the memory layer 111. Even if not completely removed, the composition for forming the memory layer 111 can be discharged. Therefore, it is not necessary to separately provide a drying step for removing the solvent in order to form the insulating layer. For example, it is sufficient to heat the substrate provided with the first conductive layer 110 when forming the insulating layer. Further, it can be performed in combination with drying performed when forming the memory layer 111 in a later step. In addition, an insulating layer formed by a droplet discharge method using an organic compound having an insulating property has a low density and is bulky. Therefore, compared with an insulating layer formed using another method or another insulating material, Leakage current flowing in an unwritten element at the time of reading can be reduced with almost no increase in write voltage due to the provision of 300.

  Alternatively, the layer 300 may be a semiconductor layer, such as molybdenum oxide, tin oxide, bismuth oxide, silicon film, vanadium oxide, nickel oxide, zinc oxide, silicon germanium, gallium arsenide, gallium nitride, indium oxide, indium phosphide. , Indium nitride, cadmium sulfide, cadmium telluride, and a strontium titanate film.

  The semiconductor layer can also be formed using a droplet discharge method or a printing method. As other formation methods, an evaporation method, an electron beam, a sputtering method, a CVD method, a spin coating method, a sol-gel method, or the like may be used.

  The structure of the memory element is not limited to FIG. 6A, and the layer 300 may be provided in contact with the second conductive layer 112 as illustrated in FIG. 6B. Further, as illustrated in FIG. 6C, two layers of the layer 300 may be provided so as to be in contact with the first conductive layer 110 and the second conductive layer 112.

  As described above, by providing an insulating layer or a semiconductor layer in contact with at least one of the first conductive layer and the second conductive layer, leakage current flowing through an unwritten element at the time of reading can be reduced. Therefore, power consumption can be reduced.

(Embodiment 2)
In this embodiment mode, a semiconductor device having a memory element of the present invention, typically a memory device, will be described with reference to the drawings. Here, a case where the structure of the storage device is a passive matrix type is shown.

  One structural example of the semiconductor device described in this embodiment is illustrated in FIG. The semiconductor device 400 includes a memory cell array 411 in which memory elements 401 are provided in a matrix, decoders 412 and 413, a selector 414, and a read / write circuit 415. Note that the structure of the semiconductor device 400 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included.

  Note that the decoders 412, 413, the selector 414, the read / write circuit 415, the interface, and the like may be formed over the substrate in the same manner as the memory element, or may be externally attached as an IC chip.

  The memory element 401 includes a first conductive layer connected to the word line Wy (1 ≦ y ≦ n), a second conductive layer connected to the bit line Bx (1 ≦ x ≦ m), A memory layer sandwiched between the conductive layer and the second conductive layer;

  An example of a top view and a cross-sectional view of the memory cell array 411 is illustrated in FIG. Note that FIG. 8A is a top view of part of the memory cell array 411. FIG.

  In the memory cell array 411, memory elements 401 are provided in a matrix. The memory element 401 includes a first conductive layer 510 extending in a first direction (A-B) and a memory layer extending in a second direction (C-D) perpendicular to the first direction on the substrate. And a second conductive layer 512. Note that a partition wall (insulating layer) 520 extending in the second direction is provided between each of the plurality of memory layers and the second conductive layer 512. The memory elements adjacent to each other in the direction 1 (AB) are separated. Note that each layer used for the memory element 401 can be formed using the substance described in Embodiment 1. In FIG. 8A, an insulating layer functioning as a protective film provided to cover the partition wall (insulating layer) 520 and the second conductive layer 512 is omitted.

  Note that the first conductive layer 510 in this embodiment corresponds to the first conductive layer 110 in Embodiment 1, and the memory layer corresponds to the memory layer 111. The second conductive layer 512 corresponds to the second conductive layer 112 in Embodiment 1. Components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  An example of a cross-sectional structure between A and B in FIG. 8A is shown in FIG. 8B, and an example of a cross-sectional structure between C and D is shown in FIG. As the substrate 521 provided with the memory element 401, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, paper made of a fibrous material, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. A film (made of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like) can also be used.

  Further, a thin film transistor (TFT) may be provided over an insulating substrate and the memory element 401 may be provided thereover, or a field effect on the substrate using a semiconductor substrate such as Si or an SOI substrate instead of the substrate. A transistor (FET) may be formed and the memory element 401 may be provided thereover. Alternatively, the memory element 401 may be provided by bonding a thin film transistor or a field effect transistor. In this case, the memory element 401 and the thin film transistor or the field effect transistor can be provided in separate steps and then attached by using a conductive film, an anisotropic conductive adhesive, or the like.

  8B and 8C, first, a first conductive layer 110 is formed over a substrate 521 by vapor deposition, sputtering, CVD, printing, electroplating, electroless plating, or droplet discharge. It is formed using a method or the like. Next, a partition wall (insulating layer) 520 is formed by a sputtering method, a CVD method, a printing method, a droplet discharge method, a spin coating method, an evaporation method, or the like. Note that the partition wall (insulating layer) 520 has a heat resistance such as an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, acrylic acid, methacrylic acid, or a derivative thereof, or polyimide, aromatic polyamide, or polybenzimidazole. A functional polymer or a siloxane resin may be used. In addition, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, melamine resins, and urethane resins may be used, and benzocyclobutene, parylene, and fluorinated arylene. An organic material such as ether or polyimide, a composition containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. Further, in the cross section between A and B, that is, the cross section of the partition wall (insulating layer) 520 illustrated in FIG. 8B, the side surface of the partition wall (insulating layer) 520 is 10 degrees or more with respect to the surface of the first conductive layer 110. It is preferable to have an inclination angle of less than 60 degrees, preferably 25 degrees or more and 45 degrees or less. Furthermore, it is preferable that it is curved. With such a shape, when the memory layer 111 is formed using a droplet discharge method, the discharge material can be prevented from being unnecessarily spread from a desired position. Next, as described above, the memory layer 111 is formed over the first conductive layer 110 by a droplet discharge method. Further, the second conductive layer 112 is formed over the memory layer 111 by an evaporation method, a sputtering method, a CVD method, a printing method, a droplet discharge method, or the like. Then, an insulating layer 522 functioning as a protective film is provided so as to cover the partition wall (insulating layer) 520 and the second conductive layer 112. Note that silicon oxide, silicon nitride, silicon oxynitride, or the like can be used for the protective film, so that entry of moisture, oxygen, or the like can be prevented.

  In the cross section taken along the line C-D, that is, the cross section of the first conductive layer 110 shown in FIG. 8C, the side surface of the first conductive layer 110 is substantially perpendicular to the surface of the substrate 521 or 90 degrees or more. Preferably it has a slope of less than degrees. Further, the first conductive layer 110 may have a shape in which the radius of curvature continuously changes. Note that “substantially vertical” means 90 ° (± 1 °). With such a shape, coverage of the memory layer 111 and the second conductive layer 112 stacked on the first conductive layer 110 can be improved.

  Note that since the discharge material for forming the memory layer 111 is in a liquid state, it is greatly affected by the surface state of the formation region. Therefore, the partition wall (insulating layer) 520 may be processed to control wettability. The wettability of a solid surface is affected by the surface chemical properties and the physical surface shape (surface roughness). In the present invention, the process for controlling the wettability of the surface is to form regions having different wettability with respect to the discharge material in the adhesion region of the liquid discharge material. Note that regions having different wettability are regions having a difference in wettability with respect to the discharged material, that is, different contact angles of the discharged material. The region where the contact angle of the discharged material is large is a region with lower wettability (hereinafter also referred to as a low wettability region), and the region with a small contact angle is a region with high wettability (hereinafter also referred to as a high wettability region). It is. When the contact angle is large, the liquid discharge material does not spread on the surface of the region, and when the contact angle is small, the discharge material spreads. As described above, in the regions having different wettability, the surface energy is also different, the surface energy in the region having low wettability is small, and the surface energy in the region having high wettability is large.

  Note that the difference in wettability is a relative relationship between the two regions. Here, a desired formation region is formed by forming a low wettability region over a partition wall (insulating layer) 520 which is a formation region of the memory layer 111. And regions having different wettability can be formed. As a method for selectively forming a low wettability region, a mask layer is formed, and a layer made of a low wettability material is selectively formed using the mask layer. A surface that selectively reduces wettability. It can be formed using a processing method or the like.

  For example, as a method for changing and controlling the wettability of the surface, there is a method of changing the wettability by decomposing the surface material by the energy of light irradiation, modifying the surface of the region. As a substance having low wettability, a substance containing a fluorocarbon group (fluorocarbon chain) or a substance containing a silane coupling agent can be used. Since the silane coupling agent can form a monomolecular film, the modification can be performed efficiently and the wettability can be changed in a short time. The silane coupling agent can be used not only having a fluorocarbon chain but also having an alkyl group because it exhibits low wettability by arranging it on a substrate. Moreover, you may use a titanate coupling agent and an aluminate coupling agent as a substance with low wettability.

  Since the liquid discharge material moves to a higher wettability, it is possible to form a pattern at a more accurate position. In addition, the utilization efficiency of the material can be improved.

  9A, a rectifying element may be provided between the first conductive layer 110 and the substrate 521 in the memory element 401. Examples of rectifying elements include Schottky barrier type, PIN type, and PN type diodes, and diode-connected transistors. Here, a diode 611 including the third conductive layer 612 and the semiconductor layer 613 is provided below and in contact with the first conductive layer 110. Note that the diodes 611 corresponding to the memory elements are separated by an interlayer insulating film 614. Alternatively, the rectifying element may be provided on the side opposite to the memory layer 111 in contact with the second conductive layer 112.

  Further, in the case where there is a concern about the influence of an electric field between adjacent memory elements in the second direction (C-D), as illustrated in FIG. 9B, the first conductive layer 110 between the memory elements. A partition wall (insulating layer) 621 may be provided. This not only prevents the influence of an electric field between adjacent memory elements, but also prevents the memory layer 111 from being generated due to a step of the first conductive layer 110 when the memory layer 111 is provided to cover the first conductive layer 110. Step breakage can be prevented.

  Note that in the cross section of the partition wall (insulating layer) 621 illustrated in FIG. 9B, the side surface of the partition wall (insulating layer) 621 is greater than or equal to 10 degrees and less than 60 degrees, preferably 25 with respect to the surface of the first conductive layer 110. It preferably has an inclination angle of not less than 45 degrees and not more than 45 degrees. Furthermore, it is preferable that it is curved. After the partition wall (insulating layer) 621 is thus provided, the memory layer 111 and the second conductive layer 112 are formed so as to cover the first conductive layer 110 and the partition wall (insulating layer) 621. In addition to the above structure, the memory layer 111 may be formed only over the first conductive layer 110 as illustrated in FIG. In this case, it is preferable to perform a process for controlling wettability on the partition wall (insulating layer) 621 to form a low wettability region.

  Next, a data writing operation to the memory element will be described. Here, a case where data writing is performed by electrical action, typically, application of voltage will be described with reference to FIG. Note that writing is performed by changing the electrical characteristics of the memory element, but the initial state of the memory element (the state where no electrical action is applied) is the data “0”, and the state where the electrical characteristic is changed is the data “ 1 ”.

  When writing data “1” to the memory element 401, first, the memory element 401 is selected by the decoders 412, 413 and the selector 414. Specifically, the decoder 413 applies a predetermined potential V2 to the word line W3 connected to the storage element 401. In addition, the bit line B 3 connected to the memory element 401 is connected to the read / write circuit 415 by the decoder 412 and the selector 414. Then, the write potential V1 is output from the read / write circuit 415 to the bit line B3. In this manner, the voltage Vw (Vw = V1−V2) is applied between the first conductive layer and the second conductive layer included in the memory element 401. By appropriately selecting the voltage Vw, the memory layer provided between the conductive layers is physically or electrically changed, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. For example, the first conductive layer and the second conductive layer may be short-circuited. The voltage Vw may be, for example, 5 V or more and 15 V or less, or −15 V or more and −5 V or less.

  Note that control is performed so that data “1” is not written to the memory element connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. In addition, it is preferable to apply the same potential as that of the second conductive layer to the non-selected word lines.

  On the other hand, when data “0” is written to the memory element 401, it is not necessary to apply an electrical action to the memory element 401. In the circuit operation, for example, as in the case of writing “1”, the memory element 401 is selected by the decoders 412 and 413 and the selector 414, but the output potential from the read / write circuit 415 to the bit line B3 is selected. The potential of the word line W3 or the potential of the non-selected word line is such that the electrical characteristics of the memory element 401 are not changed between the first conductive layer and the second conductive layer constituting the memory element 401. (For example, −5 to 5 V) may be applied.

  Next, an operation for reading data from the memory element is described with reference to FIG. Data reading is performed using the fact that the electrical characteristics between the first conductive layer and the second conductive layer are different between the memory element having the data “0” and the memory element having the data “1”. . For example, the effective electrical resistance (hereinafter simply referred to as the electrical resistance of the memory element) between the first conductive layer and the second conductive layer constituting the memory element having data “0” is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory element having data “1” is R1 in the read voltage will be described. Note that R1 << R0. The read / write circuit 415 can use, for example, a circuit including a resistance element 450 and a differential amplifier 451 illustrated in FIG. The resistance element 450 has a resistance value Rr, and R1 <Rr <R0. Further, as shown in FIG. 7C, a transistor 452 may be used instead of the resistance element 450, and a clocked inverter 453 may be used instead of the differential amplifier 451. The clocked inverter 453 receives a signal φ or its inverted signal that is High when reading is performed and is Low when the reading is not performed. Of course, the circuit configuration is not limited to FIGS. 7B and 7C.

  When data is read from the memory element 402, first, the memory element 402 is selected by the decoders 412 and 413 and the selector 414. Specifically, the decoder 413 applies a predetermined potential Vy to the word line Wy connected to the memory element 402. In addition, the bit line Bx connected to the memory element 402 by the decoder 412 and the selector 414 is connected to the terminal P of the read / write circuit 415. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vy and V0 by the resistance element 450 (resistance value Rr) and the memory element 402 (resistance value R0 or R1). Therefore, the potential Vp0 of the terminal P when the memory element 402 has data “0” is Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). Further, the potential Vp1 of the terminal P when the memory element 402 has data “1” is Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 7B, Vref is selected to be between Vp0 and Vp1, and in FIG. 7C, the changing point of the clocked inverter 453 is selected to be between Vp0 and Vp1. Thus, Low / High (or High / Low) is output according to the output potential Vout corresponding to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 451 is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the data in the memory element is “0”, Vp0 = 2.7V and Vout is High, and when the data in the memory element is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory element can be read.

  In the above method, the state of the electric resistance of the memory layer is read as a voltage value by utilizing the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. Further, when the electrical characteristics of the memory element have diode characteristics with different threshold voltages between data “0” and “1”, reading may be performed using the difference in threshold voltages.

  Further, a thin film transistor (TFT) may be provided over an insulating substrate, and a memory element or a memory element array may be provided thereover, or a semiconductor substrate such as Si or an SOI substrate may be used instead of the insulating substrate. A field effect transistor (FET) may be formed on the substrate, and a memory element or a memory element array may be provided thereon.

  In the semiconductor device shown in this embodiment mode, data can be written (added) as well as once. On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. In addition, since the memory element of the present invention that can be easily manufactured with high yield is provided, a semiconductor device having excellent performance and reliability can be manufactured at low cost.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. Therefore, the memory element included in the semiconductor device described in this embodiment includes an insulating layer or a semiconductor layer provided between, for example, the memory layer and at least one of the first conductive layer and the second conductive layer. good.

(Embodiment 3)
In this embodiment mode, a semiconductor device including the memory element of the present invention will be described with reference to FIG. Note that an active matrix memory device will be specifically described.

  One structural example of the semiconductor device described in this embodiment is illustrated in FIG. The semiconductor device 700 includes a memory cell array 711 in which memory cells 701 are provided in a matrix, decoders 712 and 713, a selector 714, and a read / write circuit 715. Note that the structure of the semiconductor device 700 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included.

  Note that the decoders 712 and 713, the selector 714, the read / write circuit 715, the interface, and the like may be formed over the substrate in the same manner as the memory element, or may be externally attached as an IC chip.

  The memory cell 701 includes a first wiring connected to the bit line Bx (1 ≦ x ≦ m), a second wiring connected to the word line Wy (1 ≦ y ≦ n), a thin film transistor 721, and a memory An element 722. The memory element 722 has a structure in which a memory layer is sandwiched between a pair of conductive layers.

  Next, an example of a top view and a cross-sectional view of the memory cell array 711 having the above structure is described with reference to FIGS. Note that FIG. 11A is a top view of part of the memory cell array 711. FIG.

  In the memory cell array 711, a plurality of memory cells 701 are provided in a matrix. In the memory cell 701, a thin film transistor 721 functioning as a switching element and a memory element connected to the thin film transistor 721 are provided over a substrate having an insulating surface.

  FIG. 11B illustrates an example of a cross-sectional structure between A and B in FIG. Note that in FIG. 11A, the partition (insulating layer) 822, the memory layer 111, the second conductive layer 112, and the insulating layer 522 which are provided over the first conductive layer 110 are omitted.

  The memory cell 701 includes a thin film transistor 721, a memory element 801, an insulating layer 821, and a partition wall (insulating layer) 822 that covers part of the first conductive layer 110. Note that an insulating layer 522 which covers the memory element 801 and functions as a protective film is provided. A memory element 801 connected to the thin film transistor 721 formed over the substrate 521 having an insulating surface includes a first conductive layer 110, a memory layer 111, and a second conductive layer 112 formed over the insulating layer 821. Have As described above, the memory layer 111 is composed of nanoparticles made of a conductive material covered with an organic thin film. The thin film transistor 721 is not particularly limited as long as it functions as a switch, and is not particularly required to be a thin film transistor.

  One mode of the thin film transistor 721 is described with reference to FIGS. FIG. 12A illustrates an example in which a top-gate thin film transistor is applied. An insulating layer 901 is provided as a base film over the substrate 521, and a thin film transistor 910 is provided over the insulating layer 901. In the thin film transistor 910, a semiconductor layer 902 and an insulating layer 903 that can function as a gate insulating layer are formed over the insulating layer 901, and a gate electrode 904 is formed over the semiconductor layer 902 with the insulating layer 903 interposed therebetween. . Note that an insulating layer 905 functioning as a protective layer and an insulating layer 821 functioning as an interlayer insulating layer are provided over the thin film transistor 910. In addition, wirings 907 connected to the source region and the drain region of the semiconductor layer are formed.

  As the insulating layer 901, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used, and these insulating films are formed as a single layer or two or more layers. Note that the insulating layer 901 may be formed by a sputtering method, a CVD method, or the like.

  As the semiconductor layer 902, a crystalline semiconductor film such as polysilicon may be used in addition to an amorphous semiconductor such as amorphous silicon, a semi-amorphous semiconductor, a microcrystalline semiconductor, or the like.

  In particular, an amorphous or microcrystalline semiconductor is crystallized by crystallizing a semiconductor that is crystallized by laser light irradiation, a crystallized semiconductor that is crystallized by heat treatment, or a combination of heat treatment and laser light irradiation. It is preferable to apply a crystalline semiconductor. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a silicon semiconductor can be applied.

In the case of crystallization by irradiating with laser light, high repetition frequency with continuous wave laser light irradiation or repetition frequency of 10 MHz or more and pulse width of 1 nanosecond or less, preferably 1 to 100 picoseconds. By irradiating with ultrashort pulse light, crystallization can be performed while continuously moving the molten zone in which the crystalline semiconductor is melted in the irradiation direction of the laser light. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, 400 cm ² / V · sec or more can be realized.

  When the crystallization process is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large-area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

  Alternatively, the semiconductor layer 902 may be formed by performing a crystallization step by heating at a temperature equal to or higher than the heat resistant temperature of the glass substrate using a substrate that can reach a heating temperature. Typically, a quartz substrate is used as the insulating substrate, and the semiconductor layer 902 is formed by heating an amorphous or microcrystalline semiconductor at 700 ° C. or higher. As a result, a semiconductor with high crystallinity can be formed. In this case, a thin film transistor which has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

  The gate electrode 904 can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. In the case of using a metal, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), or the like can be used. Alternatively, a metal nitride obtained by nitriding a metal can be used. Or it is good also as a structure which laminated | stacked the 1st layer which consists of the said metal nitride, and the 2nd layer which consists of a metal. In the case of a laminated structure, a so-called hat shape in which the end portion of the first layer protrudes outward from the end portion of the second layer may be employed. At this time, a barrier metal can be formed by using a metal nitride for the first layer. That is, the second layer metal can be prevented from diffusing into the insulating layer 903 and the semiconductor layer 902 below the insulating layer 903.

Note that a sidewall (side wall spacer) 908 may be formed on a side surface of the gate electrode 904. The sidewall can be formed by forming an insulating layer by a CVD method and anisotropically etching the insulating layer by a RIE (Reactive Ion Etching) method.

  Various structures such as a single drain structure, an LDD (low concentration drain) structure, and a gate overlap drain structure can be applied to a transistor including the semiconductor layer 902, the insulating layer 903, the gate electrode 904, and the like. Note that FIG. 12A illustrates an LDD thin film transistor in which a low-concentration impurity region 909 is formed in a semiconductor layer where sidewalls overlap. It is also possible to apply a single gate structure, equivalently a multi-gate structure in which transistors to which a gate voltage of the same potential is applied are connected in series, or a dual gate structure in which a semiconductor layer is sandwiched between gate electrodes. Is possible.

  The insulating layer 821 is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. When a coating method such as spin coating or roll coater is used, an insulating layer formed of silicon oxide by heat treatment can be used after applying an insulating film material dissolved in an organic solvent. For example, an insulating layer that can be formed by heat treatment at 200 to 400 ° C. after forming a coating film containing a siloxane bond can be used. By using an insulating layer formed by a coating method or an insulating layer flattened by reflowing as the insulating layer 821, disconnection of a wiring formed over the layer can be prevented. In addition, the insulating layer formed by such a method can be effectively used when forming a multilayer wiring.

  The wiring 907 formed over the insulating layer 821 can be provided so as to intersect with a wiring formed in the same layer as the gate electrode 904, so that a multilayer wiring structure is formed. A multilayer wiring structure can be formed by stacking a plurality of insulating layers having the same function as the insulating layer 821 and forming wirings on the insulating layers. The wiring 907 includes a low resistance material such as aluminum (Al) such as a laminated structure of titanium (Ti) and aluminum (Al), a laminated structure of molybdenum (Mo) and aluminum (Al), and titanium (Ti) or molybdenum ( It is preferably formed in combination with a barrier metal using a refractory metal material such as Mo).

  FIG. 12B illustrates an example in which a bottom-gate thin film transistor is applied. An insulating layer 901 is formed over the insulating substrate 521, and a thin film transistor 920 is provided thereover. The thin film transistor 920 is provided with a gate electrode 904, an insulating layer 903 that functions as a gate insulating layer, and a semiconductor layer 902, and a channel protective layer 921, an insulating layer 905 that functions as a protective layer, and an interlayer insulating layer thereon An insulating layer 821 is provided. Further, an insulating layer functioning as a protective layer may be formed thereon. The wiring 907 connected to each of the source region and the drain region of the semiconductor layer can be formed over the insulating layer 905 or the insulating layer 821. Note that in the case of a bottom-gate thin film transistor, the insulating layer 901 is not necessarily formed.

  In the case where the substrate 521 is a flexible substrate, the heat resistant temperature is lower than that of a non-flexible substrate such as a glass substrate. Therefore, the semiconductor layer of the thin film transistor is preferably formed using an organic semiconductor.

  Here, a structure of a thin film transistor using an organic semiconductor for a semiconductor layer is described with reference to FIGS. FIG. 12C illustrates an example in which a staggered organic semiconductor transistor is applied. An organic semiconductor transistor 931 is provided over a flexible substrate 930. The organic semiconductor transistor 931 includes a gate electrode 932, an insulating layer 933 functioning as a gate insulating film, and a semiconductor layer 934 provided in a place where the gate electrode 932 and the insulating layer 933 overlap with each other. Is connected. Note that the semiconductor layer is in contact with the insulating layer 933 functioning as a gate insulating film and the wiring 907.

  The gate electrode 932 can be formed using a material and a method similar to those of the gate electrode 904. Alternatively, the gate electrode 932 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 932 can be formed by printing a paste containing fine particles over a flexible substrate by a printing method, followed by drying and baking. As typical examples of the fine particles, fine particles mainly containing any of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver, and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

  The insulating layer 933 functioning as a gate insulating film can be formed using a material and a method similar to those of the insulating layer 903. However, when an insulating layer is formed by heat treatment after applying an insulating film material dissolved in an organic solvent, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate.

  As a material of the semiconductor layer 934 of the organic semiconductor transistor, a polycyclic aromatic compound, a conjugated double bond compound, phthalocyanine, a charge transfer complex, and the like can be given. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 934 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, when polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3-alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  In addition, as a method for forming a semiconductor layer of an organic semiconductor transistor, an evaporation method, a coating method, a spin coating method, a bar coating method, a solution casting method, a dipping method, a screen printing method, a roll coater method, or a droplet discharge method is used. Can do. The thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm.

  FIG. 12D illustrates an example in which a coplanar organic semiconductor transistor is applied. An organic semiconductor transistor 941 is provided over a flexible substrate 930. The organic semiconductor transistor 941 includes a gate electrode 932, an insulating layer 933 functioning as a gate insulating film, and a semiconductor layer 934 provided in a place where the gate electrode 932 and the insulating layer 933 overlap with each other. Is connected. The wiring 907 connected to the semiconductor layer 934 is in contact with the insulating layer and the semiconductor layer which function as a gate insulating film.

  The thin film transistor and the organic semiconductor transistor may have any structure as long as they can function as a switching element. Note that the wiring 907 may be used as the first conductive layer in the memory element of the present invention, or the memory element of the present invention may be connected to the wiring 907.

  Alternatively, a transistor may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. The SOI substrate may be formed by a method of bonding wafers or a method called SIMOX in which an insulating layer 831 is formed inside by implanting oxygen ions into the Si substrate.

  For example, in the case where a single crystal semiconductor is used for the substrate, the memory element 801 is connected to a field effect transistor 832 provided using the single crystal semiconductor substrate 830 as illustrated in FIG. In addition, an insulating layer 833 is provided so as to cover a wiring connected to the field-effect transistor 832, and the memory element 801 is provided over the insulating layer 833.

  Since a transistor formed using such a single crystal semiconductor has favorable characteristics such as response speed and mobility, a transistor that can operate at high speed can be provided. In addition, since the transistor has less variation in characteristics, a semiconductor device that achieves high reliability can be provided.

  Note that the memory element 801 includes a first conductive layer 110, a memory layer 111, and a second conductive layer 112 formed over the insulating layer 833. The memory layer 111 includes the first conductive layer 110 and the memory layer 111. The structure is sandwiched between the second conductive layers 112.

  In this manner, by providing the insulating layer 833 and forming the memory element 801, the first conductive layer 110 can be freely arranged. In other words, in the structure in FIG. 11B, the memory element needs to be provided in a region avoiding the wiring connected to the transistor. However, by providing the insulating layer 833, for example, as shown in FIG. The memory element 801 can also be formed over the transistor 832. As a result, the memory circuit can be more highly integrated. Needless to say, the wiring 907 included in the field-effect transistor 832 may be used as the first conductive layer included in the memory element.

  11B and 11C, an example in which the memory layer 111 is continuously provided in the first direction (A-B) is shown. However, these memory cells are only provided in each memory cell. A memory layer 111 may be provided. With such a configuration, it is possible to further improve the material utilization efficiency.

Further, after a separation layer is provided over the substrate and the layer 1030 including the transistor and the memory element 801 are formed over the separation layer, the layer 1030 including the transistor and the memory element 801 are separated from the substrate using the separation layer. As illustrated in FIG. 13, the layer 1030 including a transistor and the memory element 801 may be attached to a substrate 1031 which is different from the substrate using an adhesive layer 1032. As a peeling method, (1) a metal oxide layer is provided as a peeling layer between a substrate having high heat resistance and a layer having a transistor, the metal oxide layer is weakened by crystallization, and a layer having the transistor is formed. (2) An amorphous silicon film containing hydrogen is provided as a separation layer between a substrate having high heat resistance and a layer having a transistor, and the amorphous silicon film is removed by laser light irradiation or etching. Thus, a method of peeling the layer including the transistor, (3) mechanically removing the high heat-resistant substrate on which the layer including the transistor is formed, or a solution or a fluorine such as NF ₃ , BrF ₃ , or ClF ₃ (4) A metal layer and a metal oxide layer are provided as a separation layer between a substrate having high heat resistance and a layer having a transistor, and the metal acid is removed. Object layer weakened by crystallization, a part of the solution and NF ₃ or the like fluoride gas in the metal layer, BrF _3, was removed by etching by a halogen fluoride gas such as ClF _3, weakened metal oxide A method of physically peeling in the layer may be used.

  In addition, as the substrate 1031, a flexible substrate, a film, paper made of a fibrous material, or the like shown in the substrate 521 described in Embodiment 2 is used, so that the memory device can be reduced in size, thickness, and weight. It is possible.

  Next, a data writing operation to the memory device, that is, the semiconductor device 700 is described with reference to FIG. As in the second embodiment, an operation when data is written by an electrical action, typically, voltage application will be described here. Note that writing is performed by changing the electrical characteristics of the memory cell, but the initial state (state where no electrical action is applied) of the memory cell is data “0”, and the state where the electrical characteristic is changed is data “ 1 ”.

  A case where data is written to the memory cell 701 in the xth row and the yth column will be described. When data “1” is written to the memory cell 701, first, the memory cell 701 is selected by the decoders 712 and 713 and the selector 714. Specifically, the decoder 713 applies a predetermined potential V22 to the word line Wy connected to the memory cell 701. Further, the bit line Bx connected to the memory cell 701 is connected to the read / write circuit 715 by the decoder 712 and the selector 714. Then, the write potential V21 is output from the read / write circuit 715 to the bit line Bx.

  Thus, the thin film transistor 721 included in the memory cell is turned on, the common electrode and the bit line are electrically connected to the memory element 722, and a voltage of approximately Vw (Vw = Vcom−V21) is applied. Vcom is a potential of the common electrode in the memory element 722, that is, the second conductive layer. By appropriately selecting the voltage Vw, the memory layer provided between the electrode layers is physically or electrically changed, and data “1” is written. Specifically, in the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. Note that the voltage Vw may be, for example, 5 V or more and 15 V or less, or −15 V or more and −5 V or less.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential for turning off a transistor of a memory cell to be connected or a potential similar to Vcom may be applied to a non-selected word line.

  On the other hand, when data “0” is written to the memory cell 701, it is not necessary to apply an electrical action to the memory cell 701. In the circuit operation, for example, as in the case of writing “1”, the memory cell 701 is selected by the decoders 712 and 713 and the selector 714, but the output potential from the read / write circuit 715 to the bit line Bx is the same as Vcom. Or a potential at which the thin film transistor 721 of the memory cell is turned off. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 722 or no voltage is applied to the memory element 722, so that electrical characteristics do not change and data “0” writing is realized.

  Next, operation when data is read by electrical action is described with reference to FIG. Data is read using the fact that the electrical characteristics of the memory element 722 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the reading / writing circuit 715, for example, a circuit using a resistance element 750 and a differential amplifier 751 illustrated in FIG. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 752 may be used instead of the resistance element 750 as shown in FIG. 10C, or a clocked inverter 753 may be used instead of the differential amplifier 751. Of course, the circuit configuration is not limited to FIGS. 10B and 10C.

  When data is read from the memory cell 702 in the xth row and the yth column, first, the memory cell 702 is selected by the decoders 712 and 713 and the selector 714. Specifically, the decoder 713 applies a predetermined potential V24 to the word line Wy connected to the memory cell 702 to turn on the thin film transistor 721. In addition, the bit line Bx connected to the memory cell 702 is connected to the terminal P of the read / write circuit 715 by the decoder 712 and the selector 714. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 750 (resistance value Rr) and the memory element 722 (resistance value R0 or R1). Therefore, the potential Vp0 of the terminal P when the memory cell 702 has data “0” is Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). In addition, the potential Vp1 of the terminal P when the memory cell 702 has data “1” is Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 10B, Vref is selected to be between Vp0 and Vp1, and in FIG. 10C, the changing point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Low / High (or High / Low) is output according to the output potential Vout corresponding to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 751 is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. If it is assumed that R0 / Rr = Rr / R1 = 9 and the on-resistance of the thin film transistor 721 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as High, When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

  According to the above method, the voltage value is read using the difference in resistance value of the memory element 722 and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. Further, when the electrical characteristics of the memory cell have data “0” and “1” and the diode characteristics have different threshold voltages, reading may be performed using the difference in threshold voltages. .

  Further, a thin film transistor (TFT) may be provided over an insulating substrate, and a memory element or a memory element array may be provided thereover, or a semiconductor substrate such as Si or an SOI substrate may be used instead of the insulating substrate. A field effect transistor (FET) may be formed on the substrate, and a memory element or a memory element array may be provided thereon.

  In the semiconductor device shown in this embodiment mode, data can be written (added) as well as once. On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. In addition, since the memory element of the present invention that can be easily manufactured with high yield is provided, a semiconductor device having excellent performance and reliability can be manufactured at low cost.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. Therefore, the memory element included in the semiconductor device described in this embodiment includes an insulating layer or a semiconductor layer provided between, for example, the memory layer and at least one of the first conductive layer and the second conductive layer. good.

(Embodiment 4)
In this embodiment, a structural example of the semiconductor device including the memory device described in the above embodiments will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. There are two types of antennas used for data transmission. One is provided on a substrate provided with a transistor and a memory element, and the other is provided on a substrate provided with a transistor and a memory element. There is a case where a terminal portion is provided and an antenna provided on another substrate is connected to the terminal portion.

  The structure of the semiconductor device shown in this embodiment will be described with reference to FIG. As shown in FIG. 14A, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and other circuits. A control circuit 14 for controlling, an interface circuit 15, a memory circuit 16, a bus 17, and an antenna 18 are provided.

  Further, as shown in FIG. 14B, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14, the interface circuit 15, the memory circuit 16, the bus 17, and the antenna 18, the central processing unit 1 may be included.

  Further, as shown in FIG. 14C, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14 for controlling the circuit, the interface circuit 15, the storage circuit 16, the bus 17, the antenna 18, and the central processing unit 1, the detection unit 2 including the detection element 3 and the detection circuit 4 may be provided.

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The memory circuit 16 includes one or a plurality of memory elements selected from the memory elements described in Embodiment 1. By using the memory element of the present invention, a memory circuit can be easily manufactured with a high yield.

  In addition, the opportunity of writing data to the memory element is not limited to once, and data can be added (added). On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. Thus, a semiconductor device with excellent performance and reliability can be manufactured at low cost.

  The detection unit 2 can detect temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, gas component, liquid component, and other characteristics by physical or chemical means. The detection unit 2 includes a detection element 3 that detects a physical quantity or a chemical quantity, and a detection circuit 4 that converts the physical quantity or the chemical quantity detected by the detection element 3 into an appropriate signal such as an electrical signal. . The detection element 3 can be formed of a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, a diode, or the like. A plurality of detection units 2 may be provided. In this case, a plurality of physical quantities or chemical quantities can be detected simultaneously.

  Here, the physical quantity refers to temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, and the like, and the chemical quantity refers to a chemical substance such as a gas component such as gas or a liquid component such as ion. In addition, the chemical amount includes organic compounds such as specific biological substances (for example, blood glucose level contained in blood) contained in blood, sweat, urine and the like. In particular, when a chemical amount is to be detected, a specific substance is necessarily selectively detected. Therefore, a substance that selectively reacts with a substance to be detected is provided in advance in the detection element 3. . For example, when detecting a biological substance, it is preferable that an enzyme, an antibody, a microbial cell, or the like that selectively reacts with the biological substance to be detected by the detection element 3 is fixed to a polymer or the like.

  Next, FIG. 15 illustrates a configuration example of a semiconductor device in which an antenna is provided over a substrate provided with a plurality of elements and memory elements. FIG. 15 is a partial cross-sectional view of the memory circuit 16 and the antenna 18.

  FIG. 15A illustrates a semiconductor device including a memory circuit which is formed using a passive matrix type. The semiconductor device includes a layer 1351 including transistors 1300 and 1301 over a substrate 1350, a memory element portion 1352 formed above the layer 1351 including transistors, and a conductive layer 1353 functioning as an antenna.

  Note that although the case where the memory element portion 1352 and the conductive layer 1353 functioning as an antenna are provided above the layer 1351 including a transistor is shown here, the present invention is not limited to this structure, and the conductive layer 1353 functioning as the memory element portion 1352 or the antenna is used. May be provided below the layer 1351 including a transistor or in the same layer.

  The memory element portion 1352 includes a plurality of memory elements 1352a and 1352b. The memory element 1352a includes a first conductive layer 110 provided over the insulating layer 1252, and a memory layer 111a and a second conductive layer 112a provided over the first conductive layer 110. The memory element 1352b includes a first conductive layer 110 provided over the insulating layer 1252, and a memory layer 111b and a second conductive layer 112b provided over the first conductive layer 110. Note that the individual memory elements 1352 a and 1352 b are separated by a partition wall (insulating layer) 1374.

  The first conductive layer 110 in the memory element portion 1352 is connected to a wiring connected to the transistor 1301, and the memory element portion 1352 is formed using a material or a manufacturing method similar to those of the memory element described in the above embodiment mode. Can be formed. An insulating layer 522 functioning as a protective film is formed so as to cover the second conductive layers 112a and 112b and the conductive layer 1353 functioning as an antenna.

  Note that the conductive layer 1353 functioning as an antenna is provided over the conductive layer 1360. The conductive layer 1360 is connected to the transistor 1300 through a wiring 1310 formed in the same step as the first conductive layer 110 in the memory element portion 1352. The conductive layer functioning as an antenna may be formed using the same layer as the second conductive layers 112a and 112b.

  The conductive layer 1353 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when a conductive layer functioning as an antenna is formed using a screen printing method, a desired conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is desired. It can be provided by selectively printing in the area. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) is used as the material of the conductive paste, the conductive layer is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost. In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

  As the transistors 1300 and 1301 included in the transistor-containing layer 1351, the transistors described in Embodiment 3 can be selected as appropriate and used.

  Further, a separation layer is provided over the substrate, a layer 1351 including a transistor, a memory element portion 1352, and a conductive layer 1353 functioning as an antenna are formed over the separation layer, and the separation method described in Embodiment 3 is used as appropriate. The transistor-containing layer 1351, the memory element portion 1352, and the conductive layer 1353 functioning as an antenna may be peeled off and attached to the substrate with an adhesive layer. As the substrate, a flexible substrate, a film, paper made of a fibrous material, a base film, or the like shown as the substrate 521 of Embodiment 2 is used, so that the storage device can be reduced in size, thickness, and weight. Is possible.

  FIG. 15B illustrates an example of a semiconductor device including an active matrix memory circuit. Note that FIG. 15B will be described with respect to portions different from those in FIG.

  A semiconductor device illustrated in FIG. 15B includes a layer 1351 including transistors 1300 and 1301 over a substrate 1350, and a conductive element 1353 functioning as a memory element portion 1356 and an antenna above the layer 1351 including transistors. Note that here, a case where the memory element portion 1356 and the conductive layer 1353 functioning as an antenna are provided above the layer 1351 having a transistor is shown; Alternatively, the memory element portion 1356 and the conductive layer 1353 functioning as an antenna can be provided below the layer 1351 including the transistor or in the same layer.

  The memory element portion 1356 includes memory elements 1356a and 1356b. The memory element 1356a includes a first conductive layer 110a formed over the insulating layer 1252, and a memory layer 111 and a second conductive layer 112 provided over the first conductive layer 110a. The memory element 1356b includes a first conductive layer 110b formed over the insulating layer 1252, and a memory layer 111 and a second conductive layer 112 provided over the first conductive layer 110b. Note that the memory elements 1356a and 1356b are separated by a partition wall (insulating layer) 1374, and the memory element portion 1356 can be formed using a material or a manufacturing method similar to those of the memory elements described in the above embodiment modes. In addition, a wiring connected to the transistor is connected to each of the first conductive layers included in the memory element. That is, each memory element is connected to one transistor. Note that also in the cross-sectional direction illustrated in FIG. 15B, the memory layer 111 may be separated by each memory element.

  Further, a separation layer is provided over the substrate, a layer 1351 having a transistor, a memory element portion 1356, and a conductive layer 1353 functioning as an antenna are formed over the separation layer, and the separation method described in Embodiment 3 is used as appropriate. The conductive layer 1353 functioning as the antenna 1351, the memory element portion 1356, and the antenna may be peeled off and attached to the substrate with an adhesive layer.

  Next, one structure of a semiconductor device including a layer having a transistor, a first substrate having a terminal portion connected to the antenna and a memory element, and a second substrate on which the antenna connected to the terminal portion is formed An example will be described with reference to FIG. Note that portions different from FIG. 15 will be described with reference to FIG.

  FIG. 16A illustrates a semiconductor device having a passive matrix memory device. The semiconductor device functions as an antenna, a layer 1351 including transistors 1300 and 1301 formed over a substrate 1350, a memory element portion 1352 formed above the layer 1351 including transistors, a terminal portion connected to an antenna, and the like. And a substrate 1365 over which a conductive layer 1357 is formed. The conductive layer 1357 and the conductive layer 1360 serving as a connection terminal are electrically connected by conductive particles 1359 included in the resin 1375. Note that a substrate 1350 including a transistor-containing layer 1351, a memory element portion 1352, and the like, and a substrate 1365 provided with a conductive layer 1357 functioning as an antenna are attached to each other with a resin 1375 having adhesiveness.

  Alternatively, the conductive layer 1357 functioning as an antenna may be connected to the conductive layer 1360 serving as a connection terminal using a conductive adhesive such as silver paste, copper paste, or carbon paste, or a method of performing solder bonding. Although the case where the memory element portion 1352 is provided above the layer 1351 having a transistor is shown here, the present invention is not limited to this structure, and the memory element portion 1352 is provided below the layer 1351 having a transistor or in the same layer. Also good.

  FIG. 16B illustrates a semiconductor device provided with an active matrix memory device. The semiconductor device functions as an antenna, a layer 1351 including transistors 1300 and 1301 formed over a substrate 1350, a memory element portion 1356 formed above the layer 1351 including transistors, a terminal portion connected to the transistors, and the like. And a substrate 1365 over which a conductive layer 1357 is formed. The conductive layer 1357 and the conductive layer 1360 serving as a connection terminal are connected by conductive particles 1359 included in the resin 1375. Note that a substrate including the layer 1351 including a transistor, the memory element portion 1356, and the like and a substrate 1365 provided with a conductive layer 1357 functioning as an antenna are attached to each other with a resin 1375 having adhesiveness.

  Further, a conductive layer such as a silver paste, a copper paste, or a carbon paste, or a method of performing solder bonding, a layer 1351 having a transistor, a substrate 1350 having a memory element portion 1356, and the like, and a conductive layer 1357 functioning as an antenna are provided. The provided substrate 1365 may be attached. Although the case where the memory element portion 1352 is provided above the layer 1351 including a transistor is shown here, the present invention is not limited to this structure, and the memory element portion 1356 is provided below the layer 1351 including a transistor or in the same layer. Also good.

  Further, a separation layer is formed over the substrate, a layer 1351 having a transistor, a memory element portion 1352, or a memory element portion 1356 is formed over the separation layer, and the transistor is included by using the separation method described in Embodiment 3 as appropriate. The layer 1351 and the memory element portions 1352 and 1356 may be peeled off and attached to the substrate using an adhesive layer.

  Further, the memory element portions 1352 and 1356 may be provided over the substrate 1365 provided with the conductive layer 1357 functioning as an antenna. In other words, the first substrate over which a layer including a transistor is formed and the second substrate over which a conductive layer functioning as a memory element portion and an antenna are formed may be bonded to each other with a resin containing conductive particles. Further, similarly to the semiconductor device illustrated in FIGS. 15A and 15B, a sensor connected to a transistor may be provided.

  In the semiconductor device shown in this embodiment mode, data can be written (added) as well as once. On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. In addition, since the memory element of the present invention that can be easily manufactured with high yield is provided, a semiconductor device having excellent performance and reliability can be manufactured at low cost.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. Therefore, the memory element included in the semiconductor device described in this embodiment includes an insulating layer or a semiconductor layer provided between, for example, the memory layer and at least one of the first conductive layer and the second conductive layer. good.

(Embodiment 5)
In this embodiment, an example of a semiconductor device including the memory element of the present invention will be described with reference to drawings. A top view of the semiconductor device of this embodiment is shown in FIG. 17A, and a cross-sectional view taken along line XY in FIG. 17A is shown in FIG.

  As shown in FIG. 17A, a memory element portion 1404 having a memory element, a circuit portion 1421, and an antenna 1431 are formed over a substrate 1400. 17A and 17B show a state in which a memory element portion, a circuit portion, and an antenna are formed over a substrate 1400 that can withstand the manufacturing conditions in the middle of the manufacturing process. Materials and manufacturing steps may be selected as appropriate in the same manner as in the above embodiment mode.

  A transistor 1441 is provided in the memory element portion 1404 and a transistor 1442 is provided in the circuit portion 1421 with a separation layer 1452 and an insulating layer 1453 provided over a substrate 1400. An insulating layer 1461, an insulating layer 1454, and an insulating layer 1455 are formed over the transistors 1441 and 1442, and a memory element 1443 is formed over the insulating layer 1455.

  The memory element 1443 includes a first conductive layer 110d, a memory layer 111, and a second conductive layer 112 provided over the insulating layer 1455. The memory layer 111 includes the first conductive layer 110d and the second conductive layer 112d. The conductive layer 112 is sandwiched. Note that the memory element 1443 can be formed using a material or a manufacturing method similar to those of the memory element described in the above embodiment. Although omitted in FIG. 17, the memory elements 1443 provided in large numbers by the insulating layer 1460b functioning as a partition or the like are individually separated.

  The first conductive layer 110 d is connected to the wiring layer of the transistor 1441. On the other hand, the second conductive layer 112 is connected to a conductive layer 1457c stacked over the wiring layer 1456a. In addition, a conductive layer and an antenna 1431 illustrated in FIG. 17A are stacked over the insulating layer 1455. In FIG. 17B, the conductive layers are a conductive layer 1457a, a conductive layer 1457b, a conductive layer 1457e, and a conductive layer 1457f. The conductive layer 1457a and the antenna 1431a, the conductive layer 1457b and the antenna 1431b, and the conductive layer 1457f and the antenna 1431d is laminated. Note that the conductive layer 1457e and the antenna 1431c are formed in openings that reach the wiring layer 1456b formed in the insulating layer 1455, and the conductive layer 1457e and the wiring layer 1456b are connected to each other. In this manner, the antenna, the memory element portion 1404, and the circuit portion 1421 are electrically connected. In addition, the conductive layer 1457a, the conductive layer 1457b, the conductive layer 1457e, and the conductive layer 1457f formed under the antenna 1431a, the antenna 1431b, the antenna 1431c, and 1431d, respectively, are effective in improving the adhesion between the insulating layer 1455 and the antenna. Also have. In this embodiment, a polyimide film is used for the insulating layer 1455, a titanium film is used for the conductive layer 1457a, a conductive layer 1457b, a conductive layer 1457e, and a conductive layer 1457f, and an aluminum film is used for the antenna 1431a, the antenna 1431b, the antenna 1431c, and the antenna 1431d. Used.

  Note that an opening (also referred to as a contact hole) is formed in the insulating layer 1455 so that the first conductive layer 110d and the transistor 1441, the conductive layer 1457c and the wiring layer 1456a, and the conductive layer 1457e and the wiring layer 1456b are connected to each other. . When the opening is increased and the contact area between the conductive layers is increased, the resistance becomes lower. Therefore, in this embodiment, the opening where the first conductive layer 110d and the transistor 1441 are connected is the smallest, and the next However, the openings are set in order so that the opening connecting the conductive layer 1457c and the wiring layer 1456a and the opening connecting the conductive layer 1457e and the wiring layer 1456b are the largest. In this embodiment, an opening connecting the first conductive layer 110d and the transistor 1441 is 5 μm × 5 μm, an opening connecting the conductive layer 1457c and the wiring layer 1456a is 50 μm × 50 μm, and the conductive layer 1457e and the wiring layer 1456b are connected. The opening for connecting is set to 500 μm × 500 μm.

  In this embodiment, the distance a from the insulating layer 1460a to the antenna 1431b is 500 μm or more, the distance b from the end of the second conductive layer 112 to the end of the insulating layer 1460a is 250 μm or more, and the second conductive layer 112 The distance c from the end of the insulating layer 1460c to the end of the insulating layer 1460c is 500 μm or more, and the distance d from the end of the insulating layer 1460c to the antenna 1431c is 250 μm or more. Note that the insulating layer 1460 c is partially formed in the circuit portion 1421, and the transistor 1442 includes a region not covered with the insulating layer 1460 c and a covered region.

  By using the semiconductor device as described above, a power supply voltage or a signal is directly input to the memory element unit 1404 from the external input unit, thereby writing data (corresponding to information) in the memory element unit 1404 or the memory element unit. Data can be read from 1404.

  Further, the antenna may be provided so as to overlap with the memory element portion, or may be provided around the memory element portion without overlapping. When overlapping, the entire surface may overlap, or a structure where a part overlaps may be used. For example, when the antenna unit and the memory element unit overlap, the malfunction of the semiconductor device due to the influence of noise on the signal when the antenna communicates or fluctuations in electromotive force generated by electromagnetic induction is reduced. Is possible.

  As a signal transmission method in the semiconductor device capable of inputting / outputting non-contact data described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected in consideration of the application, and an optimal antenna may be provided according to the transmission method.

  FIGS. 18A to 18D illustrate an example of a chip-shaped semiconductor device including a conductive layer 1502 functioning as an antenna formed over a substrate 1501 and a memory element portion 1503. Note that an integrated circuit or the like may be mounted in addition to the memory element in the semiconductor device.

  When a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, an antenna is used in consideration of the wavelength of an electromagnetic wave used for signal transmission. For example, the conductive layer functioning as an antenna has a linear shape (for example, a dipole antenna (see FIG. 18A)), a flat shape (for example, A patch antenna (see FIG. 18B)) or a ribbon shape (see FIGS. 18C and 18D) can be formed. Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  When an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, a conductive layer that functions as an antenna is used because electromagnetic induction due to a change in magnetic field density is used. Is preferably formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna).

  Further, in the case where an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device provided with an antenna is provided in contact with a metal, a magnetic material having a permeability between the semiconductor device and the metal is used. It is preferable to provide it. When a semiconductor device provided with an antenna is provided in contact with a metal, an eddy current flows in the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, thereby reducing the communication distance. . Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, ferrite or metal thin film having high magnetic permeability and low high-frequency loss can be used.

  In the case of providing an antenna, a semiconductor element such as a transistor and a conductive layer functioning as an antenna may be directly formed over one substrate, or the semiconductor element and the conductive layer functioning as an antenna may be provided separately. After being provided on the substrate, it may be provided by bonding so as to be electrically connected.

  In the semiconductor device described in this embodiment, data can be written (added) not only once but also once. On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. In addition, since the memory element of the present invention that can be easily manufactured with high yield is provided, a semiconductor device having excellent performance and reliability can be manufactured at low cost.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. For example, in the memory element included in the semiconductor device described in this embodiment, an insulating layer or a semiconductor layer may be provided between the memory layer and at least one of the first conductive layer and the second conductive layer. .

(Embodiment 6)
According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 19A), packaging containers (wrapping paper and Bottle, etc., see FIG. 19C), recording medium (DVD software, video tape, etc., see FIG. 19B), vehicles (bicycle, etc., see FIG. 19D), personal items (bags, glasses, etc.) ), Used on goods such as foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and luggage tags (see FIGS. 19E and 19F). be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  A semiconductor device 1610 of the present invention includes the memory element of the present invention, and is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded in a board. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. Since the semiconductor device 1610 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 1610 of the present invention on bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, forgery can be prevented. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted is described with reference to FIGS. The electronic device illustrated here is a mobile phone, and includes housings 1700 and 1706, a panel 1701, a housing 1702, a printed wiring board 1703, operation buttons 1704, and a battery 1705. The panel 1701 is detachably incorporated in the housing 1702, and the housing 1702 is fitted on the printed wiring board 1703. The shape and dimensions of the housing 1702 are changed as appropriate in accordance with the electronic device in which the panel 1701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 1703, and a semiconductor device including the memory element of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 1703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 1701 is connected to the printed wiring board 1703 via the connection film 1708. The panel 1701, the housing 1702, and the printed wiring board 1703 are housed in the housings 1700 and 1706 together with the operation buttons 1704 and the battery 1705. A pixel region 1709 included in the panel 1701 is arranged so as to be visible from an opening window provided in the housing 1700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the casings 1700 and 1706 of the electronic device can be effectively used due to the above characteristics. . Note that the casings 1700 and 1706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

  Note that the memory element of the present invention includes a first conductive layer, a memory layer, and a second conductive layer, and the memory layer is sandwiched between the first conductive layer and the second conductive layer. Note that the memory layer is composed of nanoparticles made of a conductive material covered with an organic thin film, and is formed using a droplet discharge method. Therefore, the memory element of the present invention can be easily manufactured with a high yield.

  In addition, in a semiconductor device having such a memory element, data can be written (added) as well as once. On the other hand, since it is impossible to erase data from a memory element once written, forgery due to rewriting can be prevented. Thus, a semiconductor device with excellent performance and reliability can be manufactured at low cost.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. For example, in the memory element included in the semiconductor device described in this embodiment, an insulating layer or a semiconductor layer may be provided between the memory layer and at least one of the first conductive layer and the second conductive layer. .

3A and 3B each illustrate a structure example of a memory element of the present invention. 3A and 3B illustrate an operation mechanism of a memory element of the present invention. The figure which shows the example of 1 structure of the memory element after writing. The figure which shows an example of the top view of the memory layer before and behind writing. The figure which shows the one aspect | mode of a droplet discharge apparatus. 3A and 3B each illustrate a structure example of a memory element of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 6A and 6B illustrate a memory cell included in a semiconductor device of the present invention. 3A and 3B each illustrate a structure example of a memory element of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 6A and 6B illustrate a memory cell included in a semiconductor device of the present invention. 4A and 4B illustrate one embodiment of a thin film transistor. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 6A and 6B illustrate part of a cross section of a semiconductor device of the present invention. 6A and 6B illustrate part of a cross section of a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a chip-like semiconductor device of the present invention. 6A and 6B illustrate an article on which a semiconductor device of the present invention is mounted. 6A and 6B illustrate a mobile phone equipped with a semiconductor device of the present invention.

Explanation of symbols

110 First conductive layer 111 Memory layer 112 Second conductive layer 113 Organic thin film 114 Nanoparticle 120 Conductive part 121 Conductive part 300 Layer 400 Semiconductor device 401 Memory element 402 Memory element 411 Memory cell array 412 Decoder 413 Decoder 414 Selector 415 Read / Write circuit 450 Resistive element 451 Differential amplifier 452 Transistor 453 Clocked inverter 510 First conductive layer 512 Second conductive layer 520 Partition (insulating layer)
521 Substrate 522 Insulating layer 611 Diode 612 Conductive layer 613 Semiconductor layer 614 Interlayer insulating film 621 Partition (insulating layer)

Claims (21)

Having a first conductive layer, a second conductive layer, nanoparticles made of a plurality of conductive materials, and an insulating film;
The memory element, wherein the second conductive layer is provided on the first conductive layer through a region where the insulating film and the nanoparticles are alternately arranged. In claim 1,
A memory element, comprising: a conductive portion electrically connecting the first conductive layer and the second conductive layer, wherein the nanoparticles are fused to each other by application of voltage. A first conductive layer; a second conductive layer; and a memory layer sandwiched between the first conductive layer and the second conductive layer;
The memory layer has a portion composed of nanoparticles made of a conductive material coated with an organic thin film, and a conductive portion formed by fusing the nanoparticles,
The memory element, wherein the first conductive layer and the second conductive layer are electrically connected through the conductive portion. In claim 3,
The memory element, wherein the portion composed of the nanoparticles is formed using a droplet discharge method. In claim 3 or claim 4,
The memory element according to claim 1, wherein the nanoparticles have a particle size of 1 nm to 200 nm. In any one of Claim 3 thru | or 5,
The memory element, wherein the organic thin film is composed of at least a substance or a surfactant capable of forming a coordinate bond with the conductive material. In claim 6,
The organic thin film further contains a reducing agent, a resin, and a plasticizer. In any one of Claims 3 thru | or 7,
The memory element, wherein the conductive portion is formed by applying a voltage between the first conductive layer and the second conductive layer. In any one of Claims 3 thru | or 8,
The memory element according to claim 1, wherein the number of the conductive portions is one for the memory layer. In any one of Claim 3 thru | or Claim 9,
A memory element, wherein a certain distance is maintained between the first conductive layer and the second conductive layer. In any one of Claims 2 thru | or 10,
A memory element, wherein the shape of the conductive portion is columnar, conical, or spherical. In any one of Claims 1 to 11,
A memory element, wherein an insulating layer is provided in contact with the first conductive layer. In any one of Claims 1 to 12,
A memory element, wherein an insulating layer is provided in contact with the second conductive layer. In claim 12 or claim 13,
The memory element, wherein the insulating layer is formed using a droplet discharge method. In any one of Claims 1 to 11,
A memory element, wherein a semiconductor layer is provided in contact with the first conductive layer. In any one of Claim 1 thru | or Claim 11 and Claim 15,
A memory element, wherein a semiconductor layer is provided in contact with the second conductive layer. In claim 15 or claim 16,
The memory element, wherein the semiconductor layer is formed by a droplet discharge method. Having a plurality of memory elements arranged in a matrix;
Each of the plurality of memory elements includes a first conductive layer, a second conductive layer, and a memory layer sandwiched between the first conductive layer and the second conductive layer,
The memory layer is composed of nanoparticles made of a conductive material coated with an organic thin film,
At least one memory layer of the plurality of memory elements includes a conductive portion that electrically connects the first conductive layer and the second conductive layer. In claim 18,
The semiconductor device, wherein the conductive portion is formed by fusing together some of the nanoparticles of the memory layer. In claim 18 or claim 19,
Each of the plurality of memory elements is electrically connected to a thin film transistor. In claim 20,
The semiconductor device is characterized in that the thin film transistor is provided on a glass substrate or a flexible substrate.

Images