TWI533381B - Connection of semiconductor devices - Google Patents
Connection of semiconductor devices Download PDFInfo
- Publication number
- TWI533381B TWI533381B TW097146887A TW97146887A TWI533381B TW I533381 B TWI533381 B TW I533381B TW 097146887 A TW097146887 A TW 097146887A TW 97146887 A TW97146887 A TW 97146887A TW I533381 B TWI533381 B TW I533381B
- Authority
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- Taiwan
- Prior art keywords
- wire
- skin layer
- core material
- wiring
- layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 239000010410 layer Substances 0.000 claims description 222
- 239000011162 core material Substances 0.000 claims description 116
- 239000013078 crystal Substances 0.000 claims description 98
- 229910052751 metal Inorganic materials 0.000 claims description 72
- 239000002184 metal Substances 0.000 claims description 72
- 229910052763 palladium Inorganic materials 0.000 claims description 28
- 238000009792 diffusion process Methods 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 229910052697 platinum Inorganic materials 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 239000000203 mixture Substances 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- 229910052790 beryllium Inorganic materials 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 239000004615 ingredient Substances 0.000 claims 1
- 210000003491 skin Anatomy 0.000 description 136
- 238000000034 method Methods 0.000 description 76
- 229910000679 solder Inorganic materials 0.000 description 67
- 230000000694 effects Effects 0.000 description 44
- 238000005520 cutting process Methods 0.000 description 43
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 39
- 239000000306 component Substances 0.000 description 39
- 238000005259 measurement Methods 0.000 description 38
- 238000010438 heat treatment Methods 0.000 description 35
- 239000010949 copper Substances 0.000 description 33
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- 238000004458 analytical method Methods 0.000 description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 21
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- 230000015572 biosynthetic process Effects 0.000 description 20
- 239000010931 gold Substances 0.000 description 20
- 239000000463 material Substances 0.000 description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 17
- 239000002356 single layer Substances 0.000 description 17
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
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- 238000004544 sputter deposition Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
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- 238000002360 preparation method Methods 0.000 description 3
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- 239000012467 final product Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
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- 150000002500 ions Chemical class 0.000 description 2
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- 239000002994 raw material Substances 0.000 description 2
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- ZEMPKEQAKRGZGQ-AAKVHIHISA-N 2,3-bis[[(z)-12-hydroxyoctadec-9-enoyl]oxy]propyl (z)-12-hydroxyoctadec-9-enoate Chemical compound CCCCCCC(O)C\C=C/CCCCCCCC(=O)OCC(OC(=O)CCCCCCC\C=C/CC(O)CCCCCC)COC(=O)CCCCCCC\C=C/CC(O)CCCCCC ZEMPKEQAKRGZGQ-AAKVHIHISA-N 0.000 description 1
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
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- 229910052804 chromium Inorganic materials 0.000 description 1
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- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- 230000004927 fusion Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000001771 vacuum deposition Methods 0.000 description 1
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/3006—Ag as the principal constituent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/3013—Au as the principal constituent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/302—Cu as the principal constituent
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C5/00—Alloys based on noble metals
- C22C5/02—Alloys based on gold
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C5/00—Alloys based on noble metals
- C22C5/04—Alloys based on a platinum group metal
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C5/00—Alloys based on noble metals
- C22C5/06—Alloys based on silver
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C9/00—Alloys based on copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/431—Pre-treatment of the preform connector
- H01L2224/4312—Applying permanent coating, e.g. in-situ coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/432—Mechanical processes
- H01L2224/4321—Pulling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/438—Post-treatment of the connector
- H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
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Description
本發明係關於為將半導體元件上的電極、與外部端子間進行耦接而利用的半導體裝置用合接線。
目前將半導體元件上的電極、與電路配線基板(引線框架、基板、膠帶等)的配線之外部端子間進行接合的合接線,主要係使用線徑20~50μm程度的細線(合接線)。一般就合接線的接合係使用超音波併用熱壓接方式,使用汎用焊接裝置、將合接線穿過內部並用於耦接的焊針夾具等。將合接線的焊線前端利用電弧熱輸入施行加熱熔融,並利用表面張力形成焊球之後,再於150~300℃範圍內,使該焊球部壓接接合於經加熱過半導體元件的電極上,然後,利用超音波壓接直接將合接線接合於外部引線側。
近年,半導體安裝的構造、材料、耦接技術等正急速多樣化,例如安裝構造,除現行使用引線框架的QFP(Quad Flat Packaging)之外,使用基板、聚醯亞胺膠帶等的BGA(Ball Grid Array)、CSP(Chip Scale Packaging)等等新形態已然實用化,將要求更加提升迴路性、接合性、量產使用性等的合接線。
正朝相鄰合接線的間隔變狹窄的窄間距化演進。對因應此現象的合接線要求,將要求細線化、高強度化、迴路控制、接合性的提升等。隨半導體安裝的高密度化,迴路形狀呈複雜化。迴路形狀的分類係以迴路高度、合接線的
焊線長度(跨距)為指標。最新的半導體係在單一封裝內部混載著高迴路與低迴路、短跨距與長跨距等、相反的迴路形成的情況。為將此情形利用單一種合接線實現,便需要嚴格的合接線材料設計。
合接線的素材截至目前為止主要係使用高純度4N系(純度>99.99mass%)的金。為提升高強度化、高接合等特性,將實施微量合金元素的調整。最近,在提升接合部可靠度之目的等情況下,添加元素濃度增加至1%以下的純度2N(純度>99%)金合焊線已然實用化。藉由調整在金中所添加的合金元素種類、濃度,便可進行高強度化、可靠度控制等。另一方面,依照合金化,亦有發生接合性降低、電阻增加等弊害的情形,頗難綜合性滿足對合接線所要求的多樣特性。
再者,因為金係屬高單價,因而期盼材料費較低廉的其他種類金屬,有開發出以材料費廉價、導電性優越之銅為素材的合接線。但是,就銅的合接線將會有容易發生因焊線表面的氧化導致接合強度降低、施行樹脂密封時引發焊線表面遭腐蝕等問題。該等亦成為銅合接線無法實用化的原因。
截至目前已實用化的合接線特徵在於全部均屬單層構造。即使素材改變為金、銅等,但仍是內部均勻含有合金元素,若依合接線的焊線截面觀之,便屬焊線單層構造。雖亦有在合接線的焊線表面上形成較薄的自然氧化膜、為表面保護用的有機膜等情況,但該等亦僅限於最表面的極薄區域(~數原子層程度)而已。
因應對合接線所要求的多樣需求,便有提案在焊線表面上被覆其他金屬的多層構造合接線。
防止銅合接線發生表面氧化的方法,在專利文獻1中有提案:利用諸如:金、銀、白金、鈀、鎳、鈷、鉻、鈦等貴金屬、或耐蝕性金屬,將銅被覆的合接線。此外,就從焊球形成性、防止電鍍液劣化等觀點,在專利文獻2中有提案:以銅為主成分的芯材、在該芯材上形成由除銅以外的金屬所構成之異種金屬層,以及形成於該異種金屬層上,且由熔點較高於銅之高熔點耐氧化性金屬構成的被覆層構造合接線。在專利文獻3中所提案的合接線,係具有以銅為主成分的芯材,以及在該芯材上設置外皮層(其係含有與芯材就成分或組成中任一者不同或二者均不同的金屬、與銅),且該外皮層厚度係0.001~0.02μm薄膜。
再者,就金合接線亦有多層構造的多數提案。例如在專利文獻4中有提案:在由高純度Au或Au合金構成的芯線外周面上,被覆著由高純度Pd或Pd合金構成被覆材的合接線。在專利文獻5中有提案:在由高純度Au或Au合金構成的芯線外周面上,被覆著由高純度Pt或Pt合金構成被覆材的合接線。在專利文獻6中有提案:在由高純度Au或Au合金構成的芯線外周面上,被覆著由高純度Ag或Ag合金構成被覆材的合接線。
就量產所使用合接線的焊線特性,期盼藉由滿足諸如:在焊接步驟中的迴路控制呈安定、亦提升接合性、在樹脂密封步驟中能抑制合接線變形、耦接部的長期可靠度等綜合特性,便可因應最前端的窄間距、三維配線等高密
度安裝。
相關焊球接合,就焊球形成時形成正球性良好的焊球,並利用該焊球部與電極的接合部,獲得充分接合強度之事將屬重要。此外,為因應接合溫度的低溫化、焊線的細線化等,在電路配線基板上的配線部,將合接線進行楔形耦接之部位處的接合強度、拉伸強度等亦屬必要。
焊線的表面性狀多數情況會左右著使用性能,例如即使僅發生刮傷、切削,在量產使用上仍將構成問題。因切削將有導致相鄰接合接線間發生電氣短路的危險性,而刮傷則將成為合接線製造良率、樹脂密封時的焊線變形等損及合接線品質、可靠度的原因。此外,由於迴路形狀控制的安定性、低溫下的接合性提升等,若無法因應依ppm等級對半導體製造步驟中不良發生率進行管理的嚴格要求,則無法達實用化。
依此雖就半導體用的多層構造合接線大幅期盼實用化,但截至目前仍尚未實用化。期待利用多層構造進行表面改質、高附加價值等,另一方面,必需綜合性滿足合接線的生產性、品質、及焊接步驟的良率、性能安定性、以及半導體使用時的長期可靠度等。
專利文獻1:日本專利特開昭62-97360號公報
專利文獻2:日本專利特開2004-64033號公報
專利文獻3:日本專利特開2007-12776號公報
專利文獻4:日本專利特開平4-79236號公報
專利文獻5:日本專利特開平4-79240號公報
專利文獻6:日本專利特開平4-79242號公報
習知單層構造的合接線(以下稱「單層焊線」),為改善拉伸強度、接合部強度、可靠度等,添加合金化元素雖屬有效方法,但特性提升卻有極限限制。形成多層構造的合接線(以下稱「複層焊線」),相較於單層焊線將可期待更加提升特性並提高附加價值。具高功能化的複層焊線例如為防止銅合接線發生表面氧化情形,便可在焊線表面上被覆著貴金屬或耐氧化性金屬。金合接線亦可利用在焊線表面上被覆著高強度金屬或合金,便可期待降低樹脂流動的效果。
但是,考慮半導體安裝的高密度化、小型化、薄型化等需求,經本發明者等的評估後,判斷複層焊線在實用上會有殘留如後述問題。
相關複層焊線,因焊線製造步驟中的拉線加工、及焊線焊接步驟中的複雜迴路控制等,在使用於焊線最終成品或半導體元件耦接的狀態下,將有焊線表面容易發生刮傷、切削等等問題。例如會有焊線表面的刮傷發生次微米的微小溝之情況,就切削不良例係在複層焊線的焊線長邊方向上發生木屑狀切削,該切削長度亦有達數百μm的情況。因表面刮傷、切削,將導致迴路形狀呈不安定、或對複層焊線造成損傷導致強度降低,或者若切削屑接觸到相鄰複層焊線便會引發短路不良,成為實用上故障的原因。
因為依此相關表面刮傷、切削等不良情形的發生頻
度,係焊線線徑越細將越上升,因而不利於窄間距耦接,且高迴路與低迴路混載等的迴路控制複雜性亦將上升,導致頗難適應三維耦接。在形成低迴路時,會有表面刮傷發生頻度增加的傾向。若不降低該等不良情形,便會有複層焊線的實用範圍受限制的顧慮。
不僅會發生此種直接性的不良情形,且亦會有因焊線表面發生刮傷、切削而造成間接性不良、或者良率降低等顧慮。例如在複層焊線的焊線製造途中步驟,一經發生的刮傷、切削,即使在最終成品中未被檢測出,但將因表皮層厚度呈不均勻、或殘留內部龜裂,亦會有導致迴路形狀呈不安定的情況發生。此外,亦會有發生在量產步驟中利用光學顯微鏡施行的迴路外觀檢查,屬於較難檢測出之諸如迴路背側的刮傷、切削等情況。依此發生的不良情況,即使較難直接辨識與刮傷、切削間的因果關係,仍會造成製造良率降低等不良影響。
表面刮傷、切削的發生頻度、現象等係依照表皮層的素材而有變化,截至目前為止尚無充分的對策出現。多數情形係複層焊線發生的頻度較多於單層焊線,此現象可認為就複層焊線,在形成迴路的步驟中對表皮層的應力、應變等負荷增加、焊線製造步驟的製程條件不同等因素所造成。
當依複層焊線形成迴路時,會有迴路直線性降低、複層焊線倒塌、下垂、彎曲等不良情況發生。因該迴路直線性降低,將導致製造良率降低的問題發生。
複層焊線的焊球接合部的不良情況,代表性係有如花
瓣現象與偏芯現象。所謂「花瓣現象」係指焊球接合部的外周附近出現花瓣狀凹凸變形,偏離正圓性,在接合於小電極上時,會造成誘發焊球滲出、接合強度降低的不良原因。所謂「偏芯現象」係指焊線前端所形成的焊球部相對焊線軸形成非對稱,出現如高爾夫球桿頭狀的現象,在窄間距耦接中,當偏芯焊球進行接合時,會有引發與鄰接焊球相接觸的短路不良問題。該等複層焊線的花瓣現象與偏芯現象之發生頻度有較單層焊線增加的傾向,導致生產性降低的原因之一,因而必需增加焊線焊接步驟的管理基準嚴格度。
複層銅線相較於單層銅線,雖可期待氧化遲緩的效果,但該效果將因表皮層或焊線表面附近的組成、構造、厚度等而有大幅差異。複層銅線的構造最佳化便趨於重要。為確保與焊線同等的作業性,必需例如即使在大氣中進行2個月程度的保管後,仍可保障諸如楔形接合性、迴路形狀等不會劣化。此情形若相較於單層銅線的保管壽命之下,必需提升數十倍的壽命,且就以銅為主體的材料將必需要求相當嚴格的條件。
本發明為解決如上述的習知技術問題,目的在於提供除習知基本性能之外,能達抑制焊線表面發生刮傷與切削、迴路形狀安定化、良好焊球形成等性能的半導體裝置用合接線。
本發明者等為解決上述焊線發生的表面刮傷與切削等問題,就複層構造的合接線進行檢討,結果發現特定表皮
層且控制上述表皮層的組織將屬有效方法。
本發明係根據上述發現而完成,主旨如以下的構成:
本發明申請專利範圍第1項的半導體裝置用合接線,具有由導電性金屬構成的芯材、以及在上述芯材上且以該芯材不同金屬為主成分的表皮層,其特徵在於:上述表皮層的金屬係面心立方晶,且上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,含有對上述焊線長邊方向之角度差為15°以內之<111>的方位比率係50%以上。
本發明申請專利範圍第2項的半導體裝置用合接線,係申請專利範圍第1項中,上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,含有對上述焊線長邊方向之角度差為15°以內之<111>與<100>的方位比率總計係60%以上。
本發明申請專利範圍第3項的半導體裝置用合接線,係申請專利範圍第1項中,上述芯材截面結晶面的焊線長邊方向結晶方位<hk1>內,含有對上述焊線長邊方向之角度差為15°以內之<111>與<100>的方位比率總計係15%以上。
本發明申請專利範圍第4項的半導體裝置用合接線,係申請專利範圍第1項中,上述芯材截面結晶面的焊線長邊方向結晶方位<hk1>內,<111>與<100>的方位比率總計係30%以上。
本發明申請專利範圍第5項的半導體裝置用合接線,係申請專利範圍第1項中,上述表皮層表面的結晶粒平均尺寸,焊線長邊方向平均尺寸對圓周方向平均尺寸的比率
係3以上。
本發明申請專利範圍第6項的半導體裝置用合接線,係申請專利範圍第1項中,上述表皮層表面的焊線長邊方向結晶方位的上述<111>結晶粒面積,相對焊線表面總面積的比例係30%以上。
本發明申請專利範圍第7項的半導體裝置用合接線,係申請專利範圍第1項中,構成上述表皮層的主成分係Pd、Pt、Ru、Ag中至少1種。
本發明申請專利範圍第8項的半導體裝置用合接線,係申請專利範圍第1項中,構成上述芯材的主成分係Cu、Au中至少1種。
本發明申請專利範圍第9項的半導體裝置用合接線,係申請專利範圍第1項中,在上述表皮層與上述芯材間設有中間金屬層,該中間金屬層係由與構成上述表皮層及上述芯材的主成分為不同成分構成。
本發明申請專利範圍第10項的半導體裝置用合接線,係申請專利範圍第1項中,上述表皮層的厚度係0.005~0.2μm範圍。
本發明申請專利範圍第11項的半導體裝置用合接線,係申請專利範圍第1項中,在上述表皮層與芯材間設有具濃度斜率的擴散層。
本發明申請專利範圍第12項的半導體裝置用合接線,係申請專利範圍第7項中,構成上述芯材的主成分係Cu,且B、Pd、Bi、P、Zr中1種以上係含有5~300ppm範圍。
本發明申請專利範圍第13項的半導體裝置用合接線,係申請專利範圍第7項中,構成上述芯材的主成分係Cu,且Pd係含有5~10000ppm範圍,構成上述表皮層的主成分係Pd或Ag。
本發明申請專利範圍第14項的半導體裝置用合接線,係申請專利範圍第7項中,構成上述芯材的主成分係Au,且Be、Ca、Ni、Pd、Pt中1種以上係含有5~8000ppm範圍。
藉由本發明的半導體裝置用合接線,便可抑制焊線表面的刮傷、切削,俾改善表面性狀。且,可提升迴路直線性、迴路高度安定性。此外,可促進半導體裝置用合接線的接合形狀安定化。結果,可提供能適應諸如細線化、窄間距化、長跨距化、三維安裝等,最新半導體安裝技術的的高功能半導體裝置用合接線。
針對半導體裝置用合接線(以下稱「合接線」),就由導電性金屬構成的芯材、與在該芯材上由與芯材不同面心立方晶的金屬為主成分之表皮層所構成物進行探討,結果得知藉由在合接線表面附近含有導電性金屬,雖可期待楔形接合性的提升等,但另一方面,在焊線製造步驟中的拉線加工、及焊線焊接步驟中的複雜迴路控制等,將會發生焊線表面遭受刮傷、切削等問題,且會發生迴路形狀安定性等嫌不足等等情況。
在此針對亦可因應窄間距耦接、三維耦接的嚴格迴路控制等新需求,且在細線的焊線拉線加工中可提升良率等複層構造合接線進行探討,結果發現屬於特定表皮層,且控制上述表皮層的組織將屬有效方法。特別係藉由著眼於截至目前為止幾乎無人知曉的複層焊線表面集合組織與焊線焊接使用性能的關係,首次確認藉由對特定結晶方位進行控制,便可獲得加工性、接合性、迴路控制性等綜合性改善。更發現表皮層與芯材的組織組合等控制係屬有效方法。
即,合接線必需具備的特徵為具備有:由導電性金屬構成的芯材、與在該芯材上且以與芯材不同面心立方晶金屬為主成分的表皮層之合接線,其中,上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,50%以上係<111>。若屬於該合接線,在焊線製造步驟中的拉線加工、及焊線焊接步驟中的複雜迴路控制等,便可高效果獲得抑制焊線表面發生刮傷、切削。
若構成表皮層的成分係面心立方晶的金屬,加工時便不會發生降伏下降,加工性亦呈良好,容易因應拉線加工、迴路控制等複雜加工、彎曲等。
藉由合接線焊線長邊方向的結晶方位<hk1>內,50%以上係<111>,便可綜合性改善表皮層表面硬度、加工性、彎曲耐性等以往難兼顧的特性組,結果可抑制焊線表面遭受刮傷、切削。面心立方晶金屬的<111>方位係屬於最稠密方向,該<111>方位越集中於表皮層,越有表面機械特性提升的傾向,例如提高硬度、增強彈性變形、對塑
性變形的耐性增強、韌性亦提高。若結晶方位內的<111>方位所佔比例達50%以上,可獲得抑制焊線表面遭刮傷、切削的充分效果。最好該<111>方位的比例達60%以上,便可提高抑制切削的效果,即使焊線長達5mm以上的長跨距,仍可減輕切削、刮傷情形。更佳係若達70%以上,便更加提高抑制刮傷的效果,例如即使迴路高度在65μm以下的低迴路,仍可抑制刮傷、切削,俾形成安定的迴路形成。
因為複層焊線係表皮層與芯材將由不同成分構成,因而可較容易將被覆著焊線表面的表皮層組織分離進行控制。由該表面組織的控制所獲得特性改善效果亦高。就此點而言係不同於習知單層焊線的組織控制。單層焊線係可進行焊線整體的集合組織及結晶方位管理,但較難僅在表面附近與焊線內部分離並進行組織控制。所以,複層焊線的表皮層組織控制將要求複層焊線的獨立想法,並無法適用單層焊線的焊線截面之集合組織及結晶方位的管理。
表皮層表面結晶面的焊線長邊方向結晶方位<hk1>內,若<111>與<100>所佔比例總計達60%以上,便可使降低迴路高度的變動、高速動作下的迴路安定控制趨於容易。通常焊線耦接步驟中,將通過焊針孔的接線進行吐出或縮回等複雜動作。此動作係依數十毫秒級的相當高速進行合接線的進出入動作。相關<111>與<100>各自方位的具體效果並無明確,但判斷藉由降低合接線與焊針的滑動阻力,將使迴路高度呈安定化。換言之,為能依此使滑動性及迴路高度呈安定化,降低除<111>與<100>以
外的結晶方位將屬有效。若表皮層的<111>與<100>所佔比例總計達60%以上,依焊線長3mm以下的一般跨距,便可獲得使迴路高度呈安定化的高度效果。最好若達80%以上,即使焊線長達5mm以上的長跨距,仍可獲得使迴路高度呈安定化的高度效果。此外,提高<111>與<100>所佔比例而產生的效果,藉由降低成膜後的加工、熱處理製程的膜厚不均勻性,亦有利於表皮層厚度的均勻化。
芯材截面的焊線長邊方向結晶方位<hk1>內,若<111>與<100>所佔比例合計達15%以上,便可抑制發生焊球接合部大幅偏離正圓的異常變形不良情況。該異常變形將成為與鄰接電極間發生電氣短路的直接原因等,屬於焊球接合最忌諱的不良形態之一。異常變形判斷基準的指標係若焊球接合部成為長軸尺寸與短軸尺寸比率達1.3倍以上的橢圓狀便判斷屬不良。例如即使依低發生率的突發性發生,仍會阻礙焊線焊接的生產性。最好若<111>與<100>所佔比例合計達30%以上,便可減輕焊球接合部外周附近的凹凸變形之小花瓣不良情況,可使焊球接合部接近正圓而安定化。若正圓性良好,將有利於接合面積的縮小,接合步驟的製造管理趨於容易,或者可提升窄間距接合的生產性。焊球部的凝固組織亦將大幅反映出芯材組織,確認芯材結晶方位<hk1>內,提高<111>與<100>所佔比例將屬有效方法。相關芯材結晶方位的控制,就單層焊線而言效果係嫌不足,但相對的確認到就複層焊線而言將可獲得高效果。相關該要因雖尚無法完全明朗,但推測在複層焊線的焊球熔融時,藉由首先表皮層、接著芯材的階段
性熔融,芯材組織對焊球部的組織將造成大幅影響。該作用效果在普通焊球尺寸的情況將確認到更高效果。例如將初期焊球徑/焊線徑比率1.9~2.2的普通尺寸焊球進行接合時,將可減輕焊球接合部的異向性與花瓣狀等形狀不良情況,可提升正圓性。經調查壓縮變形、依超音波施加所產生的焊球部變形行為,結果相關焊球接合形狀確認到與表皮層組織間的相關性較小,不如說係由芯材組織產生支配性作用。所以,若芯材的<111>與<100>所佔比例合計未滿15%,焊球接合時的異常變形發生頻度將提高,反之,若未滿30%,在焊球進行接合時,發生花瓣狀、橢圓狀變形的頻度將提高,會有發生不良情況。焊線組織對焊球變形所造成的影響係對複層焊線較為明顯,多屬情況係不同於單層焊線組織的影響。最好若芯材的<111>與<100>所佔比例合計達50%以上,便可使小徑焊球的接合形狀呈安定化。例如當將初期焊球徑/焊線徑比率1.5~1.7範圍的小徑焊球進行接合時,便可提升焊球接合部的正圓性,即使電極間隔40μm以下的窄間距接合仍可獲得良好的焊球接合形狀。芯材的<111>與<100>所佔比例合計上限並無特別的限制,若在85%以下,便具有製造時的控制較為容易的優點。
藉由此種芯材組織與前述表皮層組織的組合便可期待相乘作用,可同時改善迴路形狀控制、焊球變形安定化。即,最好表皮層表面結晶面的焊線長邊方向結晶方位<hk1>內,50%以上係<111>,且芯材截面的焊線長邊方向結晶方位<hk1>內,<111>與<100>所佔比例係40%以上
的複層構造合接線。藉此,就三維安裝代表例之將複數晶片積層的積層晶片耦接,最近在BGA、CSP中所使用,鄰接合接線迴路高度60~500μm範圍的大幅差異多層次耦接(Multi-Tier Bonding)等,將可改善合接線的綜合特性。
截至此所說明,針對以可測定的結晶方位為基準,就特定配向所佔比例造成的作用、效果進行說明。今後因應窄間距化而朝細線化演進,隨表面的影響度增加,結晶方位所產生的效果係以合接線表面為基準進行整理,較能正確整握實用效果。
具體而言,最好表皮層表面結晶面的焊線長邊方向結晶方位<hk1>內,50%以上為<111>的複層構造合接線,且表皮層表面的焊線長邊方向結晶方位為<111>的結晶粒面積,相對焊線表面總面積的比例達30%以上。藉此,將提高使迴路形狀安定化的效果,其中即使經細線化達直徑22μm以下的合接線,仍可使迴路特性呈安定化,可有效減輕刮傷、切削情形。線徑22μm以下的細合接線,將因拉線加工應變的增加等,導致較難測定的結晶方位區域增加等,僅利用可測定之結晶方位內的<111>配向比例,無法正確掌握迴路特性的區域將有增加的傾向。所以,若表皮層表面的<111>結晶粒面積,相對焊線表面總面積的比例(面積比率)成為適當比例(適當面積比率),即使細線仍可獲得良好特性。該面積比率在30%以上的理由係若結晶方位內,即使50%以上係<111>,而面積比率仍未滿30%,則若使用線徑22μm以下的合接線進行窄間距耦接,亦無法抑制刮傷、切削等。最好若該面積比率達40%以上,
即使將直徑18μm以下的細線進行耦接,便可減輕迴路形成時的刮傷、切削。更佳係若該面積比率達50%以上,更加提高抑制直徑18μm以下細線遭刮傷、切削的效果,因而亦有利於40μm間距以下的窄間距耦接。
表皮層表面結晶面的焊線長邊方向結晶方位<hk1>內,50%以上係<111>的複層構造合接線,更進一步相關表皮層表面的結晶粒平均尺寸,若相對圓周方向平均尺寸的焊線長邊方向平均尺寸比率(結晶粒徑的長寬比)達3以上的複層構造合接線,便可提升已形成迴路的合接線直線性。合接線係藉由從焊針前端的孔中進行伸出、縮回而形成迴路之際,將因與焊針內壁的摩擦等,導致發生合接線倒塌、因彎曲而造成捲曲不良、因下垂而造成焊接不良等情形,造成良率降低。就抑制此種不良情形俾提升迴路直線性而言,發現提高表皮層表面的結晶粒徑長寬比將屬有效方法。若提高長寬比,焊線長邊方向上較長的結晶粒將形成纖維狀組織,而有利於減輕迴路形成時在合接線中所殘留的應變、變形變動。若長寬比達3以上,可獲得提升迴路直線性的充分效果。最好若長寬比達5以上,即使直徑25μm以下,且焊線長達5mm以上的長跨距,仍可獲得良好的迴路直線性。更佳係若長寬比達10以上,即使焊線長達7mm以上的超長跨距,仍可提高迴路直線性的提升效果。
所謂表皮層主成分的面心立方晶金屬,最好指與芯材主成分的導電性金屬為不同的金屬,對合接線的接合性改善具有效果,對合接線的抗氧化亦屬有效的金屬。具體而
言,如Pd、Pt、Ru、Rh、Ag等,若更進一步重視實用性、成本效益等,最好為Pd、Pt、Ru、Ag中至少1種的金屬。此處所謂主成分,係指具有濃度50mol%以上的元素。Pd係具有與密封樹脂的密接性、對電極的接合性均充分,品質管理亦容易等優點。Pt係使焊球形狀呈安定化較為容易。Ru係屬於硬質,且容易形成緻密膜,材料費亦較廉價。Rh係雖耐氧化性等性能良好,但因為材料費屬高單價,因而今後尚待就薄膜化等進行檢討。Ag係屬於軟質,因而就形成了表皮層的焊線進行拉線加工時,抑制刮傷等情形較為容易,且材料費亦屬廉價,因而有利於重視成本的半導體等。
即,表皮層最好係以Pd、Pt、Ru等導電性金屬中至少1種為主成分的純金屬、或以該導電性金屬為主成分的合金。若為純金屬,便具有容易提升耐氧化性、接合性等的優點,若為合金,便具有利用拉伸強度、彈性模數的提升,而抑制樹脂密封時的焊線變形優點。此處所謂上述純金屬,係相當於表皮層其中一部分含有達99mol%以上濃度的層,或者除擴散層以外的表皮層平均濃度達80mol%以上。所謂上述合金,係指含有Pd、Pt、Ru中至少1種金屬達50mol%以上。
構成芯材的導電性金屬係有如Cu、Au、Ag等,若重視實用性,則最好以Cu、Au中至少1種為主成分。Cu係材料費廉價,導電性高,在焊球形成時若吹抵保護氣體便可輕易地進行良好的焊球形成等,屬操作性較良好。Au係具有耐氧化性強、在焊球形成時並不需要保護氣體等、在接
合時的變形亦良好、且容易確保接合性等優點。Ag雖導電性優越,但拉線加工略難,必需將製造技術最佳化。另一方面,Cu、Au係使用為單層合接線用素材的情況較多,亦具有優點。
若芯材係以導電性金屬為主成分的合金,就因焊線強度增加所造成的細線化、或接合可靠度提升等亦具有利情況。Cu合金的情況,藉由B、Pd、Bi、P、Zr中1種以上含有5~300ppm範圍,便將因合接線的拉伸強度、彈性模數增加等,可獲得提升跨距達5mm程度的長跨距直線性之效果。在提高上述添加作用方面,確認到對Cu的單層焊線而言並不足,但相對的若適用於芯材主成分為Cu的複層焊線便可獲得高效果。即,芯材為B、Pd、Bi、P、Zr依5~300ppm範圍含有的Cu合金,表皮層為Pd、Pt、Ru中至少1種的主成分,上述表皮層表面結晶面的焊線長邊方向結晶方位<hk1>中,藉由<111>所佔比例達50%以上,便可更加提高長跨距直線性的效果。理由可認為藉由經控制結晶方位的表皮層、與含合金元素的芯材之相乘效果,而提升直線性。
若屬於上述表皮層表面結晶面的焊線長邊方向結晶方位<hk1>中,<111>所佔比例達50%以上,且構成表皮層的主成分係Pd或Ag,構成芯材的主成分係Cu,在芯材中含有Pd為5~10000ppm範圍的複層構造合接線,則可輕易綜合性滿足:抑制刮傷/切削、使迴路形狀及高度安定化、或使焊球接合部的壓接形狀安定化等。在焊線製造的熱處理步驟中,於芯材/表皮層的界面附近,當芯材中的
Pd、與表皮層中的Pd、Ag相互擴散時,利用Pd濃度變化的均勻化且緩和的相乘作用,便可獲得減輕迴路上面附近的剝離/切削作用、以及減輕迴路倒塌、彎曲等形狀變動的高度作用。因為該濃度變化不僅焊線整體,就連受焊球熔融熱影響的頸部亦具有效果,因而對迴路高度的安定化亦屬有效。此外,Cu芯材與Pd表皮層的組合,在焊球熔融時,會有Cu、與Pd、Ag的混合呈不均勻,導至焊球形狀發生異形的情況出現,但藉由在芯材中含有Pd,便可提高使焊球接合部形狀呈正圓化的效果。在此相關芯材中所含的Pd濃度,若達5ppm以上便可確認到上述效果,最好達200ppm以上,改善效果將更為明顯。相關該Pd濃度的上限,若在10000ppm以下,便可抑制因焊球硬化所造成的晶片損傷,最好在8000ppm以下,便可更加提高抑制晶片損傷的效果,亦有利於窄間距耦接。
Au合金的情況,若Be、Ca、Ni、Pd、Pt中1種以上含有5~8000ppm範圍,便具有同樣效果,可輕易確保良好直線性。即,最好芯材係Be、Ca、Ni、Pd、Pt的1種以上含有5~8000ppm範圍的Au合金,表皮層係以Pd、Pt、Ru中至少1種為主成分,且上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,<111>所佔比例達50%以上。
複層構造合接線的構成係藉由在表皮層與上述芯材間,設有由與構成上述表皮層及上述芯材的主成分為不同成分構成的中間金屬層,對前述表皮層結晶方位配向的控制將更為有利。在表皮層的形成時會受到底層結晶方位的
影響,理由係相較於芯材結晶方位的控制之下,在芯材上所形成中間金屬層的結晶方位控制較為容易的緣故。具體而言,中間金屬層最好係與表皮層金屬屬相同面心立方晶的金屬。特別更佳係表皮層金屬的晶格常數與中間金屬層金屬的晶格常數相接近。
即,最好特徵為在上述表皮層與上述芯材之間,具有由與構成上述表皮層及上述芯材的主成分為不同成分構成的中間金屬層之複層構造合接線。加設中間金屬層的效果,係藉由表皮層與芯材間的密接性提升等,便可提高楔形接合部接合強度指標之一的剝離強度。此處,剝離強度的測定係可代用楔形接合附近的拉力強度測定之簡便方法。所以,藉由中間金屬的插入便可增加剝離強度。其中,中間金屬層的成分係應配合表皮層及芯材的成分組合而進行選定,最好為如上述的金屬成分,特別更佳為Au、Pd、Pt。更佳的是當表皮層/芯材的主成分組合係Pd/Cu時,若中間金屬層主成分為Au,便有利於表皮層結晶方位的控制,且表皮層/中間金屬層/芯材各個界面處的密接性亦較良好。此外,當表皮層/芯材主成分的組合係Pd/Au時,若中間金屬層主成分係Pt,便有利於結晶方位的控制、以及表皮層組成、膜厚的均勻性。
若表皮層厚度在0.005~0.2μm範圍,亦有利於前述表皮層結晶方位的控制,亦可輕易綜合性滿足接合性、迴路控制等要求特性。理由係若厚度達0.005μm以上,便可獲得經控制結晶方位表皮層的充分效果,而若超過0.2μm,因焊球部合金化將導致硬化趨於明顯,在接合時會有造成
晶片出現龜裂等損傷的問題出現。
最好若表皮層厚度在0.01~0.15μm範圍,即使複雜迴路控制亦不會使速度降低,可安定地形成所需迴路形狀。更佳係若0.020~0.1μm範圍,便可輕易獲得維持合接線使用性能,且提高膜形成步驟的處理效率等安定膜質。
若中間金屬層厚度在0.005~0.2μm範圍,則表皮層的結晶方位控制將趨於容易,且將提升與芯材間的界面密接性,亦可因應複雜的迴路控制。最好若在0.01~0.1μm範圍,便可輕易地確保膜厚的均勻性、重現性。
其中,表皮層與芯材的邊界係構成表皮層的導電性金屬之檢測濃度總計為50mol%的部位。所以,本發明中所謂「表皮層」係指從構成表皮層的導電性金屬檢測濃度總計為50mol%部位到表面,即,構成表皮層的導電性金屬檢測濃度總計達50mol%以上的部位。
本發明的結晶方位最好包含合接線結晶方位對焊線長邊方向的角度差在15°以內。通常即使著眼於某方向的結晶方位,各個結晶仍具有某程度角度差,且依照樣品準備、結晶方位測定法等實驗法,亦會發生若干角度差。理由係此處若角度差範圍在15°以內,便具有各自的結晶方位特性,亦可有效活用對合接線諸特性所造成的影響度。
相關25μm徑程度的微細線表面之集合組織,以往鮮為人知,特別係相關微細線複層焊線最表面之集合組織的報告例亦少。如合接線之類,就精度佳測定較軟質且細線徑金屬線的集合組織時,將需要高度測定技術。
集合組織的測定法係就從測定區域集中於微小處,僅
獲得最表面的資訊便屬有利的觀點,可使用最近開發的電子背向散射圖形(Electron Back Scattering pattern,以下稱「EBSP」)法。利用EBSP法施行集合組織測定,即使如合接線般的細線,仍可對表面或截面的集合組織,依精度佳且充分重現性地施行測定。利用該測定方法,相關合接線的微細組織,便可高精度且重現佳地測定次微米微細結晶粒的結晶方位、焊線表面的結晶方位分佈等。
EBSP法中,通常在試料的凹凸、曲面較大之情況下,較難高精度測定結晶方位。然而,若將測定條件最佳化,便可進行高精度的測定、解析。具體而言,將合接線在平面呈直線狀固定,並利用EBSP法測定合接線中心附近的平坦部。相關測定區域,圓周方向的尺寸係以焊線長邊方向的中心為軸,且在線徑50%以下,若焊線長邊方向的尺寸在100μm以下,除精度之外,尚可提高測定效率。最好圓周方向的尺寸係在線徑的40%以下,若焊線長邊方向的尺寸在40μm以下,便可因測定時間縮短而更加提高測定效率。
利用EBSP法施行高精度測定時,因為1次可測定的區域有限制,因而最好施行3處以上的測定,俾獲得經考慮變動的平均資訊。為使測定地方不要相接近,最好依可觀察圓周方向上不同區域的方式選擇測定地方。
例如線徑25μm合接線的測定時,係使用在平板上固定成盡量改變焊線方向狀態的合接線,就以該焊線軸為中心在圓周方向上將8μm設為一次的測定區域,在焊線長邊方向上將30μm尺寸設為一次的測定區域,且相隔1mm以
上地施行3處測定,便可取得焊線表面結晶方位的平均資訊。但,測定的區域、地方的選定並無限制,最好經考慮測定裝置、焊線狀態等之後再最佳化。
再者,測定芯材結晶方位時,可就焊線長邊方向的垂直截面、或焊線長邊方向並行且焊線中心附近的平行截面等任一測定。最好為垂直截面,將可輕易獲得所需求的研磨面。當利用機械研磨製作截面時,為減輕研磨面的殘留應變,最好利用蝕刻將表皮層除去。
利用EBSP法施行測定結果的解析,係藉由利用裝置中所裝設的分析軟體,便可計算出上述焊線各方位結晶粒面積對表面測定面積所佔面積比,或以測定區域中能辨識結晶方位的結晶粒或區域總面積為分母,計算出各結晶方位所佔比率等。此處計算結晶方位面積的最小單位係可為結晶粒、或結晶粒內其中一部分的微小區域。相關結晶粒的尺寸亦是可計算焊線長邊方向與圓周方向的平均尺寸等。
當製造本發明合接線時,必需包括有:在芯材表面上形成表皮層的步驟;以及對表皮層、擴散層、芯材等的構造進行控制的加工.熱處理步驟。
將表皮層形成於芯材表面上的方法,係有如鍍敷法、蒸鍍法、熔融法等。鍍敷法係可分為電解電鍍、無電解電鍍法。電解電鍍係鍍敷速度快速,且與底層間的密接性亦良好。電解電鍍係可依1次鍍敷處理實施,但亦可區分為通稱「閃鍍」的薄鍍敷、與後續膜成長的正式鍍敷,藉由分為該等複數步驟,便更有利於膜質安定化。無電解電鍍所使用的溶液係可分類為取代型與還原型,當膜較薄的情
況,只要使用取代型鍍敷便足夠,但當形成較厚膜的情況,在取代型鍍敷後,再階段式施行還原型鍍敷便屬有效方法。無電解法的裝置等較為簡便,且容易,但較電解法耗時。
蒸鍍法係可利用例如:濺鍍法、離子蒸鍍法、真空蒸鍍等物理吸附,以及電漿CVD等化學吸附。任一者均屬乾式,在膜形成後並不需要洗淨,不會有洗淨時擔心表面污染等情況發生。
相關實施鍍敷或蒸鍍的階段,有如:依目標線徑形成導電性金屬膜的手法,以及在粗徑芯材上形成膜之後,再施行複數次拉線直到目標線徑為止的手法,任一方法均屬有效。前者依最終徑進行膜形成,就製造、品質管理等而言較為簡便,而後者的膜形成與拉線之組合,則有利於膜與芯材的密接性提升。各個形成法的具體例係有如:在目標線徑的細線上,於電鍍溶液中使焊線一邊連續進行偏移一邊進行膜形成的手法,或者將粗線浸漬於電解或無電解的鍍浴中而形成膜之後,再將焊線施行拉線俾到達最終徑的手法等。
此處,前述依最終線徑形成表皮層的最終鍍敷法,在成膜後僅為熱處理步驟而已。且,在粗徑芯材上進行膜形成的粗徑鍍敷法,必需截至目標線徑為止的加工步驟、與熱處理步驟的組合。
形成表皮層後的加工步驟,依照目的可選擇、分開使用諸如輥軋、型鍛、模具拉線等。利用加工速度、壓加率或模具減面率等,對加工組織、差排、晶界缺陷等進行控
制,亦會對表皮層的組織、密接性等構成影響。
僅單純地將焊線施行成膜、加工及加熱,便無法就表皮層表面及內部的集合組織結晶方位進行控制。通常即使直接適用在焊線製造所使用最終線徑下的加工應力退火,仍將因表皮層與芯材間的密接性降低,導至迴路控制呈不安定、或焊線長邊方向的表皮層均質性、焊線截面的表皮層、擴散層等分佈較難控制。所以,藉由表皮層成膜條件、拉線步驟的減面率、速度等加工條件、熱處理步驟的時序、溫度、速度、時間等最佳化等等綜合性組合,便可安定地控制表皮層的集合組織。
在焊線的軋延、拉線步驟中將形成加工集合組織,在熱處理步驟中進行回復、再結晶,便形成再結晶集合組織,該等集合組織係相互關聯,並決定最終的表皮層集合組織及結晶方位。在使表皮層的結晶方位配向於<111>時,利用加工集合組織將屬有效方法。經成膜後將拉線加工的處理條件最佳化,可提高對<111>的配向率。依上述拉線加工所形成對<111>的配向率係依照加工前的組成等焊線條件而異,為使前述表皮層的<111>配向率達50%以上,例如將加工率上升達80%以上便屬有效方法。最好將加工率設為95%以上,便具有使合接線整體提升<111>配向率的效果。
熱處理步驟中,熱處理係可實施1回或複數次均屬有效。熱處理步驟係可分類為:膜剛形成後的退火、加工途中的退火、及最終徑的精整退火,選擇、區分使用該等係屬重要。依照在哪一加工階段實施熱處理,最終的表皮層、
表皮層與芯材間之界面的擴散行為等便會有變化。其中一例,在鍍敷處理後的加工途中實施中間退火,更將焊線施行拉線,利用依最終徑實施精整退火的步驟進行製作,相較於未實施中間退火的步驟,便有利於在表皮層/芯材的界面上形成擴散層並提升密接性。
熱處理法係一邊使焊線連續式偏移一邊施行熱處理,且一般熱處理的爐內溫度並非設為一定,而是在爐內賦予溫度傾斜,便可輕易地量產本發明特徵之具有表皮層及芯材的合接線。具體的事例係有如:局部性導入溫度傾斜的方法、或使爐內溫度變化的方法等。當抑制合接線表面氧化時,一邊使N2或Ar等非活性氣體在爐內流動一邊施行加熱亦屬有效。
熔融法係使表皮層或芯材中任一者熔融並鑄入的手法,依10~100mm程度的粗徑將表皮層與芯材相耦接後再施行拉線,便具有生產性優越的優點,且相較於鍍敷、蒸鍍法之下,表皮層的合金成分設計較為容易,亦具有強度、接合性等特性改善容易等優點。具體的步驟係可區分為:在預先製作的芯線周圍,鑄入熔融導電性金屬而形成表皮層的方法,以及使用預先製作的導電性金屬中空圓柱,將熔融金屬鑄入中央部而形成芯線的方法。最好在後者中空圓柱內部中鑄入芯材的方法,較容易在表皮層中安定形成芯材主成分的濃度斜率等。所以,若在預先製作的表皮層中少量含有銅,便可使表皮層表面的銅濃度控制趨於容易。此外,熔融法係可省略為使Cu擴散於表皮層中的熱處理作業,但為調整表皮層內的Cu分佈,預估施行熱處理將
會更加獲得特性改善。
再者,利用此種熔融金屬的情況,芯線及表皮層中至少其中一者係可利用連續鑄造進行製造。利用該連續鑄造法,相較於上述鑄入方法,可使步驟簡略化,且亦將線徑變細亦可提升生產性。
使用芯材主成分為銅的複層銅線進行焊接時,在形成焊球時將需要保護氣體,使用含有1~10%範圍H2的N2混合氣體,或純N2氣體。習知單層銅線係建議使用5%H2+N2所代表的混合氣體。另一方面,複層銅線係使用廉價純N2氣體亦可獲得良好接合性,因而相較於標準氣體5%H2+N2氣體之下,將可降低營運成本。最好N2氣體的純度係達99.95%以上。即,最好一邊將純度99.95%以上的N2氣體吹抵於焊線前端或其周圍,一邊產生電弧放電而形成焊球部,再將該焊球部進行接合的焊接方法。
再者,藉由在表皮層與芯材間形成擴散層便可提升密接性。所謂「擴散層」係指利用芯材與表皮層的主成分相互擴散而形成的區域,具有該主成分的濃度斜率。藉由形成擴散層,便提升芯材與表皮層的密接性,可抑制迴路控制、接合時的表皮層剝離,更藉由具有濃度斜率,相較導電性金屬係表皮層整體呈均勻濃度的情況,可使發生複雜塑性變形的迴路進行控制時,焊線變形呈安定化。且,藉由前述使表皮層表面的<111>方位提高達50%以上,便具有抑制刮傷.切削的效果,但確認到若設置具有濃度斜率的擴散層,便可更加提升此效果。擴散層內的濃度斜率最好朝深度方向的濃度變化程度係每1μm達10mol%以上。
最好若每0.1μm達5mol%以上,便可期待在不損及表皮層與芯材的不同物性之情況下,獲得相互利用的高效果。擴散層厚度最好在0.002~0.2μm範圍內。理由係若擴散層厚度未滿0.002μm,則效果較小,亦較難利用分析進行辨識,若超過0.2μm,因為會對表皮層組織造成影響,因而頗難安定地形成前述結晶方位。為控制該擴散層,利用熱處理便屬有效。如前述,藉由熱處理與加工的組合而控制著擴散的進行程度,便可在焊線的圓周方向或焊線長邊方向上均勻地形成所需擴散層。
相關表皮層、芯材等的濃度分析,係有如:一邊從合接線表面利用濺鍍等朝深度方向鑿下一邊施行分析的手法,或者利用焊線截面的線分析或點分析方法等均屬有效。前者係表皮層較薄的情況較為有效,但若變厚則測定時間將過於耗時。後者的截面分析係表皮層較厚的情況較為有效,且具有截面整體的濃度分佈、數處的重現性確認等較為容易的優點,但當表皮層較薄時則精度會降低。亦可將合接線施行斜向研磨,經擴大擴散層厚度後再施行測定。截面係較容易施行線分析,但當欲提升分析精度時,將線分析的分析間隔變狹窄,或集中於欲觀察界面附近的區域並施行點分析的方式亦屬有效。該等濃度分析所使用的解析裝置,係可利用例如:電子微探分析法(EPMA)、能量分散型X線分析法(EDX)、歐傑分光分析法(AES)、穿透型電子顯微鏡(TEM)等。特別係AES法因為空間分解能力較高,因此對最表面較薄區域的濃度分析將屬有效。此外,為進行平均組成調查等,亦可從表面部起階段性溶解於酸
等之中,並從溶液中所含濃度,求取溶解部位處的組成等。本發明中,依上述所有分析手法所獲得的濃度值,並不需要全部均滿足本發明的規定範圍,若依1項分析手法所獲得濃度值滿足本發明規定範圍,便可獲得該項效果。
以下,針對實施例進行說明。
就合接線的原材料,準備:芯材所使用Cu、Au、Ag純度約99.99質量%以上的高純度素材,表皮層或中間金屬層所使用Au、Pt、Pd、Ru、Rh素材純度達99.9質量%以上的原料。
將經細達某線徑的焊線當作芯材,並在該焊線表面上形成不同金屬的層時,係施行諸如電鍍法、無電鍍法、蒸鍍法、熔融法等,並實施熱處理。利用依最終線徑形成表皮層的方法,以及依某線徑形成表皮層後,更利用拉線加工而變細至最終線徑的方法。電解電鍍液、無電解電鍍液係使用在半導體用途中的市售電鍍液,蒸鍍係使用濺鍍法。預先準備直徑約15~1500μm的焊線,在該焊線表面上利用蒸鍍、鍍敷等施行被覆,並施行拉線直到成為最終徑15~50μm為止,最後為使加工應變的消除延伸值為5~15%範圍而施行熱處理。視需要,在施行模具拉線達線徑25~200μm之後,經施行擴散熱處理後,更進一步施行拉線加工。所準備拉線用模具的減面率係每1個模具為5~15%範圍,藉由該等模具的組合,便調整焊線表面的加工應變導入等。拉線速度係在20~500m/min間最佳化。
利用熔融法的情況,係採用:在預先製作的芯線周圍,
鑄入熔融金屬的方法,以及在預先製作的中空圓柱中央部中,鑄入熔融金屬的方法。然後,施行鍛造、輥軋、模具拉線等加工、與熱處理,而製造焊線。
相關本發明例的焊線熱處理,係一邊使焊線進行連續式偏移一邊施行加熱。利用局部性導入溫度傾斜的方式、使爐內的溫度產生變化的方式等。例如利用將爐內溫度分割為3部份並可進行控制的改造熱處理爐。溫度分佈一例係從焊線插入口朝向出口,獲得高溫→中溫→低溫、或中溫→高溫→低溫的分佈,亦管理各個加熱長度。配合溫度分佈,焊線偏移速度等亦最佳化。熱處理的雰圍氣係在抑制氧化之目的下,亦利用N2、Ar等非活性氣體。氣體流量係在0.0002~0.004m3/min範圍內進行調整,亦利用於爐內的溫度控制。施行熱處理的時序係分為:當對拉線後的焊線施行熱處理之後才形成表皮層的情況,以及在加工前、加工途中、或剛形成表皮層後等期間,施行1次或2次以上熱處理等情況。
相關形成表皮層後的軋延、拉線所施行加工程度,係可依成膜時的焊線與最終線徑的面積比率,所計算出累積加工率進行整理。當該加工率(%)未滿30%時便記為R1,當30%以上且未滿70%時便記為R2,當70%以上且未滿95%時便記為R3,當95%以上時便記為R4。
在表皮層的表面組織控制時,必需將材質、組成、厚度等材料因子、以及膜形成條件、加工.熱處理條件等製程因子進行最佳化。實施例中,增加表皮層表面焊線長邊方向<111>比率的對策,係有如:提高加工率,削薄初期
膜厚、使熱處理低溫化等方法均屬有效。其中一例係若上述加工率為R2~R4,便可輕易地增加<111>比率。另一方面,比較例中為減少<111>比例,則諸如:減少加工率、或依高溫或長時間實施熱處理將屬有效。
相關焊線表面的組織觀察,在合接線表皮層的表面某區域,利用EBSP法施行結晶方位測定。測定試料的準備係將3~5條合接線在平板上固定成盡量改變相互朝焊線方向狀態。觀察區域係包括焊線軸的四角形區域,尺寸係將圓周方向5~10μm、焊線長邊方向10~50μm設定為一次的測定區域。測定地方係設定為3~10處,並選擇相互隔開0.5mm以上。測定點的間隔係依0.01~0.2μm間隔實施。
芯材的組織觀察中,使用將合接線的截面施行研磨,並利用化學蝕刻減輕表面加工應變的試料,且依照EBSP法施行結晶方位測定。截面係主要就焊線長邊方向的垂直截面進行測定,一邊檢討試料狀態、重現性等,一邊視需要亦就平行於焊線長邊方向且通過中心軸的截面實施測定。
EBSP測定的數據解析係利用專用軟體(TSL製OIM analysis等)。進行測定區域中的結晶方位解析,求取其中的<111>、<100>方位等結晶粒比例。將合接線的焊線長邊方向決定為基準方位,亦涵蓋至具各自結晶方位的角度差在15°以內者。相關該結晶粒比例的計算方法,可求得:以測定區域整體面積為分母,並計算各方位比例(以下稱「面積比率」),以及以測定區域內可鑑定某可靠度基準的結晶方位面積為分母,所計算出的各方位比例(以下稱「方位比率」)等2種。在後者求取方位比率的過程中,除
無法測定結晶方位的部位、或者即便可測定但方位解析可靠度較低的部位等之外,均進行計算。此處所謂「可靠度」係指分析軟體有準備參數的情況,例如利用Confidential Index(CI值)、Image Quality(IQ值)等數種參數,最好配合試料狀態、解析目的等而選擇判定基準。
焊線表面的膜厚測定係使用依AES施行的深度分析,在晶界的濃度變化等元素分佈觀察時,係利用AES、EPMA等實施面分析、線分析。利用AES施行深度分析,係一邊利用Ar離子施行濺鍍,一邊朝深度方向施行測定,深度單位係依SiO2換算表示。合接線中的導電性金屬濃度係利用ICP分析、ICP質量分析等施行測定。
合接線的耦接係使用市售自動焊線機並施行焊球/楔形接合。利用電弧放電在焊線前端製作焊球,將其接合於矽基板上的電極膜,並將焊線另一端楔形接合於引線端子上。為抑制焊球形成時的氧化而使用之保護氣體,主要係使用純N2氣體。氣體流量係調整為0.001~0.01m3/min範圍。
接合對像係使用矽基板上的電極膜材料,厚度1μm的Al合金膜(Al-1%Si-0.5%Cu膜、Al-0.5%Cu膜)。另一方面,楔形接合的對象係使用表面施行Ag鍍敷(厚度:2~4μm)的引線框架。此外,相關對BGA基板上的Au/Ni/Cu電極接合性,使用其中一部分焊線試料,確認可獲得與上述引線框架相同的效果。
焊線表面的刮傷、切削等評估,係利用經焊接的迴路外觀觀察進行調查。在焊線製造步驟中所發生的刮傷、切削等迴路形成前之影響亦可涵蓋在內實施評估。線徑設為
25μm。焊線長度係有2mm的通用跨距、與5mm的長跨距等2種,形成高度目標值100~250μm的梯形迴路,分別將1000條合接線利用投影機進行觀察。刮傷觀察係以迴路外側為中心進行觀察,切削觀察係以發生頻度較高的焊球接合部附近之頸部為中心進行觀察,計數尺寸達10μm以上的刮傷數。此外,低迴路評估係形成迴路高度目標值約65μm的低迴路,同樣的觀察刮傷、切削的發生。一般,焊線長越長、或者迴路高度越低,焊線表面的磨擦程度越增加,因而將採更嚴格的評估。當切削達4條以上、且刮傷亦明顯時便判斷有問題,並標記「×」;當切削在1~3條範圍內,但出現刮傷發生較多、焊針阻塞等影響顧慮時便判斷必需改善,並標記「△」;當切削在1~3條範圍內,且無發現構成問題的較大刮傷時,因為焊線表面係較良好因而標記為「○」;當無發生切削,且刮傷亦無明顯時,便判斷安定呈良好,並標記為「◎」。刮傷、切削的判定,因為依照觀察者的個人判斷而多少有會受影響的顧慮,因而依2人以上的觀察者施行評估,並依平均資訊施行等級評分。
細線的焊線表面之刮傷、切削評估,係使用線徑22μm與18μm等2種。形成焊線長2mm、高度目標值70~200μm的梯形迴路,分別將1000條合接線利用投影機進行觀察。刮傷、切削等判定基準係採用如同前述。
為進行所焊接迴路的直線性評估,便依焊線間隔(跨距)2mm的普通跨距、5mm的長跨距、7mm的超長跨距等3種方式施行焊接。線徑係設為25μm。對30條合接線利用投影機從上方進行觀察,對焊球側與楔形側的接合部連結
直線,將離合接線最遠的部位的偏移視為彎曲量並施行測定。該彎曲量的平均係若未滿線徑1條份便判斷屬良好,並標記為「◎」,若達2條份以上便屬不良,並標記為「△」,若在二者中間,因為通常不會構成問題,因而標記為「○」。
相關焊接步驟中的迴路形狀安定性,依焊線長5mm的長跨距、迴路高度200~250μm的方式,將梯形迴路進行30條耦接,利用高度標準偏差施行評估。線徑設為25μm。高度測定係使用光學顯微鏡,位置係在迴路最頂點附近、與迴路中央部等2處施行測定。若迴路高度的標準偏差達焊線徑1/2以上,便判斷變動較大,當未滿1/2,便判斷變動較小,屬良好。以該項基準為基礎進行判斷,當3處的變動均較小時,便判斷迴路形狀呈安定,並標記為「◎」;當變動較大的地方有1處時,因為屬較良好,因而標記為「○」;當有2處的情況便標記為「△」;當3處均屬變動較大時便標記為「×」。
壓接焊球部的接合形狀判定,係觀察所接合焊球200條,評估形狀的正圓性、異常變形不良、尺寸精度等。線徑設為20μm。分別依形成初期焊球徑/焊線徑比率1.9~2.2的通常尺寸焊球情況、以及形成比率1.5~1.7範圍的小徑焊球情況等2種情況進行評估。若偏移正圓的異向性、花瓣狀等不良焊球形狀達5條以上,便判定屬不良並標記為「×」;若偏離正圓的不良焊球形狀有2~4條的情況,可分類為二種情況,若異常變形發生1條以上,因為期待量產改善,因而標記為「▲」,若無發生異常變形,因為屬可使用,因而標記為「△」,若不良焊球形狀在1
條以下,便屬良好,因而標記為「○」。
剝離接合強度的評估係使用楔形接合部的拉力試驗。線徑設為25μm,跨距設為2mm。在較焊線長3/4更靠近楔形接合部的位置處,使掛勾於迴路上的鉤在上方進行移動,並測定合接線的斷裂強度。拉力強度係受合接線線徑、迴路形狀、接合條件等因素所左右,並非絕對值,利用拉力強度/焊線拉伸強度的相對比率(Rp)。若Rp達20%以上則楔形接合性屬良好,並標記為「◎」;若15%以上、未滿20%便判斷屬無問題,並標記為「○」;若10%以上、未滿15%便判斷會有發生不良情況的情形,並標記為「△」;若達10%以上,因為量產步驟會有問題,因而標記為「×」。
為進行迴路形成的外皮層與芯材的密接性評估,便從上方利用光學顯微鏡觀察迴路,調查外皮層的剝離發生。使用線徑25μm、跨距3mm的普通迴路,觀察迴路數係400條。依剝離數進行比較,若為零便判斷屬良好,並標記為「○」;若有1~4條,因為雖通常使用時不會構成問題,但有尚待改善的情形,因而標記為「△」;若達5條以上,因為量產步驟會出現問題,因而標記為「×」。
在AES分光分析的深度分析中,確認到表皮層與芯材間有濃度斜率的擴散層,當該擴散層厚度在0.002~0.2μm範圍時,便在表1中的「擴散層」欄位中標記「○」。
對晶片的損傷評估,將焊球部接合於電極膜上之後,再將電極膜施行蝕刻除去,並利用SEM觀察對絕緣膜或矽晶片造成的損傷。電極數係觀察400處。當無發現損傷的情況便標記為「○」;當龜裂出現2個以下的情況,便判
斷為不會構成問題的程度,並標記為「△」;當龜裂達3個以上的情況,便判斷屬堪慮程度,並標記為「×」。
表1及表2所示係本發明的合接線實施例與比較例。
申請專利範圍第1項的合接線係相當於實施例1~39,申請專利範圍第2項的合接線係相當於實施例2~14、16、18~39,申請專利範圍第3項的合接線係相當於實施例1~30、33~39,申請專利範圍第4項的合接線係相當於實施例1~7、10~13、15~17、19~30、33~39,申請專利範圍第5項的合接線係相當於實施例1~9、12~14、16、17、19~24、26~39,申請專利範圍第6項的合接線係相當於實施例1~5、9~21、23~39,申請專利範圍第7項的合接線係相當於實施例1~10、12~39,申請專利範圍第8項的合接線係相當於實施例1~22、24~39,申請專利範圍第9項的合接線係相當於實施例25~30,申請專利範圍第10項的合接線係相當於實施例1~32、34~39,申請專利範圍第11項的合接線係相當於實施例1~9、11~31、33~39,申請專利範圍第12項的合接線係相當於實施例2、8、9、12、27、33、34,申請專利範圍第13項的合接線係相當於實施例8、34~37、39,申請專利範圍第14項的合接線係相當於實施例17、19、20、22、30。比較例1~6係未滿足申請專利範圍第1項時的結果。
第1圖所示係實施例4的合接線表面,EBSP測定結果一例。將焊線長邊方向結晶方位距<111>方位的角度差15°以內區域施行著色,而角度差達15°以上的晶界依線標示。第1圖中,<111>面積比率係88%。
針對各申請專利範圍的代表例,就部分評估結果進行說明。
實施例1~39的複層構造合接線,係本發明藉由表皮層
表面的焊線長邊方向結晶方位內,<111>所佔比例(<111>方位比率)達50%以上,確認到減輕焊線表面的刮傷、切削情形。另一方面,相關表皮層表面的<111>方位比率未滿50%的複層構造合接線之比較例1~6,即使進行通常的迴路形成,仍確認到多數切削、刮傷。最好的情況係表皮層的<111>方位比率達60%以上的實施例2~5、8、9、11、13、14、16、18~21、23、24、26、27、29、31、35~37、39,即使長跨距仍可減輕刮傷、切削,且表皮層的<111>方位比率達70%以上的實施例3~5、9、11、14、20、21、23、26、29、35,即使低迴路的嚴格條件,確認仍將抑制刮傷、切削的不良。
實施例2~14、16、18~39的複層構造合接線,係藉由本發明的表皮層表面之<111>與<100>合計方位比率達60%以上,確認到在跨距3mm的通常迴路條件下,將抑制迴路高度變動,呈安定狀態。最好該方位比率達80%以上的實施例3~5、7~11、14、16、20、21、23、26、29、30、31、35、36、39,即使跨距5mm長跨距,仍可使迴路高度呈安定化。
實施例1~7、10~13、15~17、19~30、33~39的複層構造合接線,係藉由本發明的芯材截面之<111>與<100>合計方位比率達30%以上,在通常的焊球尺寸,將可減少焊球接合部的花瓣不良,確認可使形狀安定化。最好該方位比率達50%以上的實施例3、7、10、11、19~21、23、24、26、29、30、35、37、39,即使嚴格接合條件的小徑焊球,確認仍可提升焊球接合部的正圓性。
實施例1~9、12~14、16、17、19~24、26~39的複層構造合接線,係藉由本發明的表皮層表面結晶粒平均尺寸之焊線長邊方向/圓周方向長寬比達3以上,在通常條件的3mm跨距中,確認迴路直線性呈良好。最好該長寬比達5以上的實施例2~5、7、8、13、14、16、20~24、26、27、29、30、31、35~38,即使嚴格接合條件的5mm長跨距,確認仍可提升直線性。更佳係該長寬比達10以上的實施例3~5、14、21、24、26、29、36,即使嚴格接合條件的7mm長跨距,確認仍可提升直線性。
實施例1~5、9~21、23~39的複層構造合接線,係藉由本發明的表皮層表面的焊線長邊方向結晶方位,<111>的結晶粒面積相對焊線表面的比例(<111>面積比率)達30%以上,確認依線徑22μm的細線,將可減輕焊線表面的刮傷、切削。最好<111>面積比率達40%以上的實施例3~5、11、14、16、18、20、21、23、26、29、30、31、33~36、39,即使更細的18μm極細線,確認仍可抑制刮傷、切削。更佳係<111>面積比率達50%以上的實施例4、5、20、21、29、35,確認到對18μm極細線抑制刮傷、切削的效果更高。
實施例25~30的複層構造合接線係藉由本發明前述<111>方位比率達50%以上,且表皮層與芯材間設有中間金屬層,確認將提高楔形接合部處的剝離強度。
實施例1~30、33~39的複層構造合接線,係藉由本發明的芯材截面之<111>與<100>合計方位比率達15%以上,確認依通常焊球尺寸,可減輕焊球接合部的異常變形,
且形狀呈安定化。
實施例1~32、34~39的複層構造合接線,係藉由本發明的外皮層厚度設為0.005~0.2μm範圍,便可減輕晶片損傷,而呈良好狀況。為求比較,在實施例33中因為外皮層厚度超過0.2μm,因而確認到晶片損傷有增加。
實施例1~9、11~31、33~39的複層構造合接線,係屬於本發明之在表皮層與芯材間設有具濃度斜率的擴散層,因而確認到迴路上方不會發生剝離情形,表皮層密接性良好。
實施例2、8、9、12、27、33、34的複層構造合接線,係藉由本發明構成芯材的主成分為Cu,且含有B、Pd、P、Zr中1種以上5~300ppm範圍,確認到可提升跨距5mm程度的迴路直線性。同樣的,實施例17、19、20、22、30係藉由本發明構成芯材的主成分為Au,且含有Be、Ca、Ni、Pd中1種以上5~8000ppm範圍,確認可提升直線性。在此相關改善跨距5mm程度的迴路直線性作用,前述焊線長邊方向/圓周方向長寬比設為5以上亦屬有效方法,亦有與上述合金成分添加所產生效果難分高下的情況。另一方面,實施例9、12、17、19、33係雖長寬比未滿5,但藉由含有上述合金成分,確認跨距5mm程度的直線性可獲改善。
實施例8、34~37、39的複層構造合接線係藉由本發明的構成上述芯材之主成分為Cu,且含有Pd為5~10000ppm範圍,構成上述表皮層的主成分為Pd或Ag,確認可獲得減輕迴路上面附近的剝離.切削情形的高效果。最好為實施例8、35~37、39,因為Pd濃度達200ppm以上,因而上
述效果更為明顯。且,因為實施例8、34~36、39係Pd含有量為5~8000ppm範圍,因而確認到抑制晶片損傷。
第1圖係複層構造合接線(線徑25μm)的EBSP測定結果(將在焊線長邊方向上配向於<111>方位的區域施行著色。晶界依線表示)。
Claims (14)
- 一種半導體裝置用合接線,具有由導電性金屬構成的芯材以及在上述芯材上且以該芯材不同金屬為主成分的表皮層,其特徵在於:上述表皮層的金屬係面心立方晶,且上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,對上述焊線長邊方向之角度差為15°以內之<111>的方位比率係50%以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,上述表皮層表面結晶面中的焊線長邊方向結晶方位<hk1>內,對上述焊線長邊方向之角度差為15°以內之<111>與<100>的方位比率總計係60%以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,上述芯材截面結晶面的焊線長邊方向結晶方位<hk1>內,對上述焊線長邊方向之角度差為15°以內之<111>與<100>的方位比率總計係15%以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,上述芯材截面結晶面的焊線長邊方向結晶方位<hk1>內,對上述焊線長邊方向之角度差為15°以內之<111>與<100>的方位比率總計係30%以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,上述表皮層表面的結晶粒平均尺寸,焊線長邊方向平均尺寸對圓周方向平均尺寸的比率係3以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其 中,上述表皮層表面的焊線長邊方向結晶方位的上述<111>結晶粒面積,相對焊線表面總面積的比例係30%以上。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,構成上述表皮層的主成分係Pd、Pt、Ru、Ag中至少1種。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,構成上述芯材的主成分係Cu、Au中至少1種。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,在上述表皮層與上述芯材間設有中間金屬層,該中間金屬層係由與構成上述表皮層及上述芯材的主成分為不同成分構成。
- 如申請專利範圍第1項之半導體裝置用合接線,其中,上述表皮層的厚度係0.005~0.2μm範圍。
- 如申請專利範圍第1至10項中任一項之半導體裝置用合接線,其中,在上述表皮層與芯材間設有具濃度斜率的擴散層。
- 如申請專利範圍第7項之半導體裝置用合接線,其中,構成上述芯材的主成分係Cu,且B、Pd、Bi、P、Zr中1種以上係含有5~300ppm範圍。
- 如申請專利範圍第7項之半導體裝置用合接線,其中,構成上述芯材的主成分係Cu,且Pd係含有5~10000ppm範圍,構成上述表皮層的主成分係Pd或Ag。
- 如申請專利範圍第7項之半導體裝置用合接線,其中,構成上述芯材的主成分係Au,且Be、Ca、Ni、Pd、Pt中1種以上係含有5~8000ppm範圍。
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PCT/JP2008/071899 WO2009072498A1 (ja) | 2007-12-03 | 2008-12-02 | 半導体装置用ボンディングワイヤ |
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TW200937546A (en) | 2009-09-01 |
US20100294532A1 (en) | 2010-11-25 |
KR20100134719A (ko) | 2010-12-23 |
TWI364806B (zh) | 2012-05-21 |
MY159518A (en) | 2017-01-13 |
KR101100564B1 (ko) | 2011-12-29 |
KR101383401B1 (ko) | 2014-04-08 |
EP2200076A4 (en) | 2012-06-06 |
KR101030384B1 (ko) | 2011-04-20 |
JP4617375B2 (ja) | 2011-01-26 |
CN101689519B (zh) | 2015-05-06 |
US8299356B2 (en) | 2012-10-30 |
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EP2200076A1 (en) | 2010-06-23 |
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EP2200076B1 (en) | 2016-09-28 |
TW201207971A (en) | 2012-02-16 |
CN101689519A (zh) | 2010-03-31 |
JP2009158931A (ja) | 2009-07-16 |
KR20100013328A (ko) | 2010-02-09 |
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