TWI501398B - 使用氧化矽封裝、早暈及延伸植入於２８奈米低功率高效能技術之ｐｍｏｓ設備的晚原位摻雜矽鍺接合 - Google Patents

使用氧化矽封裝、早暈及延伸植入於２８奈米低功率高效能技術之ｐｍｏｓ設備的晚原位摻雜矽鍺接合 Download PDF

Info

Publication number
TWI501398B
TWI501398B TW102109981A TW102109981A TWI501398B TW I501398 B TWI501398 B TW I501398B TW 102109981 A TW102109981 A TW 102109981A TW 102109981 A TW102109981 A TW 102109981A TW I501398 B TWI501398 B TW I501398B
Authority
TW
Taiwan
Prior art keywords
hkmg
forming
spacer
oxide
gate stack
Prior art date
Application number
TW102109981A
Other languages
English (en)
Other versions
TW201349504A (zh
Inventor
簡 渥契爾
翁祥陽
史帝芬 弗拉霍斯基
蒂洛 沙伊佩爾
Original Assignee
格羅方德半導體私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體私人有限公司 filed Critical 格羅方德半導體私人有限公司
Publication of TW201349504A publication Critical patent/TW201349504A/zh
Application granted granted Critical
Publication of TWI501398B publication Critical patent/TWI501398B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Description

使用氧化矽封裝、早暈及延伸植入於28奈米低功率高效能技術之PMOS設備的晚原位摻雜矽鍺接合
本發明係關於一種具有嵌入式矽鍺(silicon germanium,SiGe)之源極/汲極區域的高介電常數金屬閘極(High-K Metal Gate,HKMG)半導體裝置。本發明係特別適用於28奈米(nm)之超級低功率(28nm super-low-power,28SLP)技術。
在目前之行動/多媒體市場中，對於長待機時間，確切的說，低漏電產品有巨大的需求。28SLP製程原本係設計來滿足此需求。然而，對於高效能且低功耗亦有需求。用於高效能之驅動需要要求高驅動電流之微電子元件的高速運作。典型地，傾向於提供所需要之驅動電流之增加的結構及摻雜參數對於漏電電流會有不利的影響。高介電常數金屬閘極(High-k metal gate,HKMG)電極係發展來藉由降低多晶矽空乏(polysilicon depletion)以改善驅動 電流。
在現代之CMOS技術中，嵌入式矽鍺(silicon germanium,SiGe)之源極/汲極區域在PFET裝置中係為標準的，因其藉由導入單軸應變至通道中來改善效能。然而，至今28SLP製程並未包含例如矽鍺之嵌入式源極/汲極壓力源(stressor)在p活躍(p-active)之源極/汲極區域中，且因此由於較低的電洞遷移率而在效能上有所缺乏。
因此，存在需要用於藉由整合矽鍺至HKMG製程中以使具有高效能之SLP裝置能夠製造之方法及所產生之裝置。
本發明揭露之實施態樣係為一種用於形成具有嵌入式矽鍺(eSiGe)在PMOS中之HKMG CMOS裝置的晚原位摻雜(in-situ-doped late)矽鍺(在製程流程中所有的植入之後)製程流程。
本發明揭露之另一實施態樣係為一種由晚矽鍺製程所形成之具有嵌入式矽鍺在PMOS中之HKMGCMOS裝置。
本發明揭露的額外態樣及其他特徵將在以下的內容中加以描述，其中某些部分對於本領域中具有通常知識者而言，在檢視過以下的內容後，會認為是顯而易見的，或者也可從本發明的實作中加以學習。本發明的優點，可藉由附隨的申請專利範圍中所特別指出的，來加以實現及獲得。
根據本發明揭露的態樣，一些技術效果可藉由一種方法部分達成，該方法包含：形成第一及第二高介電常數金屬閘極(HKMG)閘極堆疊於基板上；形成氮化物襯墊及氧化物間隙壁於各該第一及第二HKMG閘極堆疊之各側；於各該第一及第二HKMG閘極堆疊之各側執行暈/延伸植入；形成氧化物襯墊及氮化物間隙壁於各該第一及第二HKMG閘極堆疊之該氧化物間隙壁上；形成深源極/汲極區域在該第二HKMG閘極堆疊之相反側上；形成氧化物硬遮罩於該第二高介電金屬閘極閘極堆疊之上；形成嵌入式矽鍺於該第一HKMG閘極堆疊之相反側上；以及移除該氧化物硬遮罩。
本發明揭露的態樣包括：形成氮化矽之該氮化物襯墊；形成二氧化矽之該氧化物間隙壁；以及形成氮化矽之該氮化物間隙壁。本發明揭露的另一態樣包括該第一及第二HKMG閘極堆疊各包含高介電常數介電質、功函數金屬、多晶矽、以及氮化矽上蓋。本發明揭露的其他態樣包括於形成該嵌入式矽鍺前進行預清洗；以及最佳化該預清洗以保護該二氧化矽間隙壁。本發明揭露的又一態樣包括形成該嵌入式矽鍺於該第一HKMG閘極堆疊之各側上，藉由：經由以氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)之濕式蝕刻形成孔穴；以及於該孔穴中磊晶成長矽鍺。本發明揭露的額外態樣包括例如以梯度摻雜分佈原位植入硼摻質至該嵌入式矽鍺中。本發明揭露的再一態樣包括退火以在形成該氧化物硬遮罩之後活化植入 之摻質。本發明揭露的另一態樣包括經由以稀釋氫氟酸(diluted hydrofluoric acid,dHF)之濕式蝕刻移除該氧化物硬遮罩。本發明揭露的其他態樣包括於移除該氧化物硬遮罩之後移除該氮化矽上蓋及該氮化物間隙壁。本發明揭露的額外態樣包括由乾式或濕式蝕刻製程移除該氮化矽上蓋及該氮化物間隙壁。本發明揭露的又一態樣包括形成矽化物於該源極/汲極區域、該嵌入式矽鍺、及該第一及第二HKMG閘極堆疊上。本發明揭露的另一態樣包括形成通道矽鍺區域在該第一HKMG閘極堆疊之下。
本發明揭露的再一態樣係為一種裝置包括：第一及第二高介電常數金屬閘極(HKMG)閘極堆疊，各自包含高介電常數介電質、功函數金屬、及多晶矽；氮化物襯墊及第一與第二氧化物間隙壁，依次地形成於各該第一及第二高介電金屬閘極閘極堆疊之各側；暈及延伸植入區域，位於各該第一及第二HKMG閘極堆疊之相反側，係形成於該第二氧化物間隙壁之前；深源極/汲極區域，位於該第二HKMG閘極堆疊之相反側上，係形成於該第二氧化物間隙壁之後；以及嵌入式矽鍺，位於該第一HKMG閘極堆疊之相反側上，係利用該第二閘極堆疊之上的氧化物硬遮罩形成於該深源極/汲極區域之後。
態樣包括第一及第二高介電常數金屬閘極(HKMG)閘極堆疊，各自包含高介電常數介電質、功函數金屬、及多晶矽；氮化物襯墊及第一與第二氧化物間隙壁，依次地形成於各該第一及第二HKMG閘極堆疊之各 側；暈及延伸植入區域，位於各該第一及第二HKMG閘極堆疊之相反側，係形成於該第二氧化物間隙壁之前；深源極/汲極區域，位於該第二閘極HKMG閘極堆疊之相反側上，係形成於該第二氧化物間隙壁之後；以及嵌入式矽鍺，位於該第一HKMG閘極堆疊之相反側上，係利用該第二閘極堆疊之上的氧化物硬遮罩形成於該深源極/汲極區域之後。其他態樣包括氮化物間隙壁係形成於該第二氧化物間隙壁之上，且位於該第二閘極HKMG閘極堆疊之相反側上的該深源極/汲極區域係以該氮化物間隙壁作為軟遮罩而形成。另一態樣包括該氮化物襯墊及該氮化物間隙壁包含氮化矽(silicon nitride,SiN)且該氧化物間隙壁包含二氧化矽(silicon dioxide,SiO2 )。額外態樣包括該嵌入式矽鍺係以具有梯度摻雜分佈之硼原位植入。其他態樣包括矽化物，係位於該嵌入式矽鍺、該深源極/汲極區域、及該第一及第二HKMG閘極堆疊上。再一態樣包括通道矽鍺區域，係位於該第一HKMG閘極堆疊之下。
本發明揭露的另一態樣係為一種方法包括：形成PMOS及NMOS高介電常數金屬閘極(HKMG)閘極堆疊於基板上；形成L型氮化矽襯墊及二氧化矽間隙壁於各該PMOS及NMOS高介電金屬閘極閘極堆疊之各側；於各該PMOS及NMOS之HKMG閘極堆疊之各側執行暈/延伸植入；形成L型二氧化矽襯墊及氮化矽間隙壁於各該PMOS及NMOS之HKMG閘極堆疊之該二氧化矽間隙壁上；植入深源極/汲極區域在該NMOS之HKMG閘極堆疊之相反 側；形成二氧化矽硬遮罩於該NMOS之HKMG閘極堆疊之上；形成嵌入式矽鍺於該PMOS之HKMG閘極堆疊之相反側上，藉由：經由以氫氧化四甲基銨(TMAH)之濕式蝕刻在該PMOS之HKMG閘極堆疊之各側形成孔穴；於該孔穴中磊晶成長矽鍺；及於磊晶成長之同時，以梯度摻雜分佈原位植入硼摻質至該嵌入式矽鍺中；經由稀釋氫氟酸濕式蝕刻該氧化物硬遮罩；乾式或濕式蝕刻該氮化矽上蓋及該氮化矽間隙壁；以及形成矽化物於該源極/汲極區域、該嵌入式矽鍺、及該PMOS及NMOS之HKMG閘極堆疊上。
對於本領域中具有通常知識者而言，從以下的詳細描述中，可明顯地認識到本案的額外態樣及技術效果，其中，本發明的實施例僅藉由例示用以實行本發明的最佳模式來加以描述。將會瞭解到，本發明可有其他不同的實施例，並且，可針對各種顯而易知的方面，修改部分的細節，而不致背離本發明。因此，圖式及描述其本質僅視為例示之用，而非用以限制本發明。
101‧‧‧高介電常數金屬閘極閘極堆疊
103‧‧‧高介電常數介電質
105‧‧‧功函數金屬
107‧‧‧多晶矽
109‧‧‧氮化矽上蓋
111‧‧‧基板
113‧‧‧NMOS
115‧‧‧PMOS
117‧‧‧通道矽鍺
119‧‧‧多層沉積氮化矽層
121‧‧‧低壓氧基矽烷/高溫氧化氧化層
123‧‧‧SiO2 間隙壁
125‧‧‧暈植入
127‧‧‧延伸植入
129‧‧‧暈區域
131‧‧‧延伸區域
133‧‧‧氮化物間隙壁
135‧‧‧氧化物襯墊
137‧‧‧深源極/汲極區域
139‧‧‧硬遮罩
141‧‧‧孔穴
143‧‧‧矽鍺
145‧‧‧矽化物
本發明是藉由範例中的隨附圖式來加以例示，而非限制之用，在該圖式中，相同的元件符號視為類似的元件，其中：第1A至1I圖係根據本發明揭露的實施例，示意地例示用於形成具有PMOS嵌入式矽鍺源極/汲極區域之半導體裝置的製程。
在以下的描述中，為了解釋的目的，列出各種特定的細節，以提供示範實施例的全盤瞭解。然而，很明顯地，示範實施例不需要這些特定細節、或以均等配置，也可加以實行。在其他例子中，衆所周知的結構及裝置是以方塊圖的表現形式加以顯示，以避免不必要地模糊示範實施例。此外，除非特別指明，否則應瞭解到，說明書及圖式中所使用的所有數字表示的數量、比例、以及成分及反應條件等的數值特性。在所有例子中，均可藉由“大約”這個術語來加以修飾。
本發明面對並解決目前閘極優先(gate first)HKMG之包覆不足的問題，並伴隨著在PMOS裝置中形成嵌入式矽鍺源極/汲極區域。依據本發明揭露之實施例，一種晚矽鍺方法係合併至HKMG製程中，在較高之PFET效能下增加良率。詳言之，在各種植入過程期間，形成氮化物襯墊、氧化物間隙壁、氧化物襯墊、及氮化物間隙壁以包覆該閘極，在全部植入完成後，形成氧化物硬遮罩於該NMOS閘極堆疊之上，並在形成於PMOS之相反側的孔穴中磊晶成長嵌入式矽鍺。
依據本發明之實施例的方法包括形成第一及第二高介電常數金屬閘極(HKMG)閘極堆疊於基板上、形成氮化物襯墊及氧化物間隙壁於各該第一及第二HKMG閘極堆疊之各側上、於各該第一及第二HKMG閘極堆疊之各側執行暈/延伸植入、形成氧化物襯墊及氮化物間隙壁於各 該第一及第二HKMG閘極堆疊之該氧化物間隙壁上、形成深源極/汲極區域在該第二HKMG閘極堆疊之相反側上、形成氧化物硬遮罩於該第二HKMG閘極堆疊之上、形成嵌入式矽鍺於該第一HKMG閘極堆疊之相反側上、以及移除該氧化物硬遮罩。
對於本技術領域中具有通常知識者而言，從以下的詳細描述中，可明顯地認識到本案的額外態樣、特徵及技術效果，其中，本發明的實施例僅藉由例示用以實行本發明的最佳模式來加以描述。本發明可有其他不同的實施例，並且，可針對各種顯而易知的態樣，修改部分的細節。因此，圖式及描述其本質僅視為例示之用，而非用以限制本發明。
第1A至1I圖係根據本發明之示範實施例，例示將嵌入式矽鍺整合至PMOS的製程流程。參照第1A圖，閘極優先HKMG堆疊101，包括高介電常數介電質103(例如二氧化鉿(hafnium oxide,HfO2 )或氮氧矽鉿(hafnium silicon oxynitride,HfSiON))、功函數金屬105(例如氮化鈦(titanium nitride,TiN))、多晶矽107(poly silicon,poly-Si)、以及氮化矽上蓋109係顯示在基板111上以用於NMOS 113及PMOS 115各者。PMOS 115復包括在基板111中，位於該高介電常數介電質103之下的5至10nm厚度之通道矽鍺117(channel SiGe,cSiGe)以調整由於該閘極優先方法之臨限電壓(threshold voltage)。使用閘極優先方法復需要包覆層圍繞該閘極堆疊以於之後例如清洗及蝕刻的 製程步驟保護HKMG。為此目的，多層沉積(multilayer deposition,MLD)氮化矽(Si3 N4 )層119係毯覆式沉積(blanket deposition)在整個基板上達3nm至6nm的厚度。低壓氧基矽烷(low pressure tetra ethyl ortho silicate,LPTEOS)/高溫氧化物(high temperature oxide,HTO)氧化層121係以5nm至10nm的厚度形成於Si3 N4 MLD層119上，用以在各閘極堆疊之各側上形成間隙壁零層(spacer zero)。
如第1B圖所示，非等向性蝕刻氧化層121以形成SiO2 間隙壁(SP0)123。MLD Si3 N4 層119亦從該打開的作用區域被蝕刻。該間隙壁係在形成暈區域129及延伸區域131時，使用來補償(offset)及調整暈/延伸植入(125/127)，如第1C圖所示，對於該NMOS及PMOS二者，係對各者使用植入遮罩(為了例示方便而未圖示)。暈區域係藉由在中等能量(例如，35keV至50keV)下，植入低到中劑量(例如，3.5E13至7E13)之砷(As)、硼(B)、或氟化硼(BF2 )而形成。延伸區域係藉由在低能量(例如，0.7keV對硼或4keV對砷)下，植入高劑量(例如，1.1E15)之砷(As)、硼(B)、或氟化硼(BF2 )而形成。
參照第1D圖，例如為氮化矽之氮化物間隙壁133係形成於該NMOS及該PMOS二者上，具有氧化物襯墊135在下方以作為蝕刻停止層。在NMOS中，氮化物間隙壁133係用作為軟遮罩用於深源極/汲極植入，以形成深源極/汲極區域137。舉例而言，可在高劑量(例如，2E15)及高能量(例如，6keV對硼或20keV對砷)下植入砷(As)、 硼(B)、或氟化硼(BF2 )。
隨後，如第1E圖所示，氧化層139係以10nm至25nm之厚度沉積在NMOS 113上。氧化層139可被形成在NMOS 113及PMOS 115上，然後由PMOS 115上清除。該氧化層用作為NMOS 113上之硬遮罩。接著執行快速熱退火(rapid thermal anneal,RTA)以活化該摻質並退火處理所有的植入傷害。RTA透過槽密實化(trough densification)同時硬化了硬遮罩139。或者，可在n型深源極/汲極植入之後，以及因此係在該氧化硬質遮罩139形成前，直接執行RTA。
如第1F圖所示，在該基板中該PMOS 115閘極堆疊之各側上，Σ形狀(sigma shaped)孔穴141係使用氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)所形成。雖然可能為其他形狀，該Σ形狀孔穴141允許非常接近的近似性(proximity)以及因此該電晶體通道區域內的最大應力。在進一步處理之前，係執行預清洗，其係為最佳化的(亦即，並不非常侵略性的)以保護該氧化物硬遮罩139。
在預清洗之後，如第1G圖所示，矽鍺143係在該孔穴141中成長，舉例而言藉由低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)製程作為用於該PMOS裝置之深源極/汲極區域的原位梯度硼摻雜沉積。原位摻雜(in-situ doping)係被使用以允許高且均勻之摻雜水準(doping level)，其因此降低寄生電阻與接觸電阻， 藉此允許較高之驅動電流。此外，硼允許鍺之含量增加，例如大於35%，相對於未摻雜矽鍺之25%，其引發較高之應力並進一步改善電洞遷移率提升。藉由在磊晶過程中摻雜PMOS之源極/汲極區域，消除了專用之源極/汲極植入，藉此節省用於遮罩及植入之製程成本、減少週期時間(cycle time)、及降低來自植入傷害的應力鬆弛。再者，硼摻質係藉由磊晶而活化，從而消除額外退火之需求。稍微的過度成長(overgrowth)係幫助形成更為堅固之包覆以及用於其會攻擊主動開放矽區域(active open silicon area)之後續清洗的裕度(margin)。過度成長復提供額外的裕度以用於形成堅固的矽化物，例如矽化鎳(nickel silicide,NiSi)，並具有較佳的接觸電阻。
如第1H圖所示，另一清洗步驟，例如使用濕式蝕刻，舉例而言以稀釋氫氟酸(diluted hydrofluoric acid,dHF)，將由NMOS 113上移除該氧化物硬遮罩139。參照第1I圖，該濕式蝕刻係接著乾式蝕刻或一額外的濕式蝕刻，舉例而言，使用熱磷酸(hot phosphoric acid,H3 PO4 )，以移除該氮化物上蓋109及氮化物間隙壁133。如圖所示，此將保留曝露出來之L型氧化物間隙壁135。
金屬，例如鎳(Ni)、鎳鈦(NiTi)或鈷(Co)，可隨後沉積在整個裝置上並退火處理以形成在源極/汲極區域137及多晶矽107上之矽化物145(即，矽化鎳、矽化鎳鈦、或矽化鈷)以及在矽鍺143上之矽化物145(即，矽鍺化鎳(NiSiGe)、矽鍺化鎳鈦(NiTiSiGe)、或矽鍺化鈷 (CoSiGe))，以形成低電阻區域。與矽鍺結合之矽化物降低了片電阻及接觸電阻，從而改善了效能行為。製程流程隨後繼續傳統的中段(middle-of-line,MOL)製程以及接觸形成。或者，在矽化之時間，若L型氧化物間隙壁135過薄，例如小於10nm，舉例而言因為在沉積鎳之前的預清洗過程中薄化，則必須在形成矽化物之前形成額外之氮化物間隙壁(氮化矽保護間隙壁，為了例示方便而未圖示)，以增加遠離該通道區域的矽化物距離。之後製程可繼續所揭露之矽化製程、中段製程以及接觸形成。
本發明揭露的實施例可達成數種技術效果，包含增進閘極優先HKMG之包覆，從而改善良率、降低接觸電阻、降低在PMOS裝置中的串聯電阻、增加在PMOS裝置中的載子遷移率及驅動電流、增進效能、及降低製造成本。依據本發明揭露的實施例所形成之裝置可在各種產業應用中享有實用性，例如，微處理器、智慧型手機、行動電話、蜂巢式手機，機上盒、DVD錄影機及播放機、汽車導航、印表機及週邊設備、網路及電信裝備、遊戲系統、以及數位相機。因此，本發明在任何高度整合之半導體裝置之各種類型，特別是32nm及28nm技術以上的技術，係享有產業利用性。
在先前的段落中，本發明是參考本發明的特定示範實施例來加以描述。然而，很明顯地，可對本發明作出各種修正及改變，而不致於背離本發明在申請專利範圍中所呈現的最廣精神及範圍。因此，該說明書及圖式將 被視為例示、而非限制之用。應瞭解到，本發明可使用不同的其他組合及實施例，並因此可在本文所表示的發明概念的範圍內，作任何的改變或修正。
103‧‧‧高介電常數介電質
105‧‧‧功函數金屬
107‧‧‧多晶矽
111‧‧‧基板
113‧‧‧NMOS
115‧‧‧PMOS
117‧‧‧通道矽鍺
119‧‧‧多層沉積氮化矽層
123‧‧‧SiO2 間隙壁
129‧‧‧暈區域
131‧‧‧延伸區域
135‧‧‧氧化物襯墊
137‧‧‧深源極/汲極區域
143‧‧‧矽鍺
145‧‧‧矽化物

Claims (20)

  1. 一種形成半導體裝置的方法，包括：形成第一及第二高介電常數金屬閘極(HKMG)閘極堆疊於基板上；形成氮化物襯墊及氧化物間隙壁於各該第一及第二HKMG閘極堆疊之各側上；於各該第一及第二HKMG閘極堆疊之各側執行暈/延伸植入；形成氧化物襯墊及氮化物間隙壁於各該第一及第二HKMG閘極堆疊之該氧化物間隙壁上；形成深源極/汲極區域在該第二HKMG閘極堆疊之相反側上，其中，該氮化物間隙壁係作為軟遮罩以用於該深源極/汲極之植入；形成氧化物硬遮罩於該第二HKMG閘極堆疊之上；形成嵌入式矽鍺於該第一HKMG閘極堆疊之相反側上；以及移除該氧化物硬遮罩。
  2. 如申請專利範圍第1項所述之方法，包括：形成氮化矽之該氮化物襯墊；形成二氧化矽之該氧化物間隙壁；以及形成氮化矽之該氮化物間隙壁。
  3. 如申請專利範圍第1項所述之方法，其中，該第一及第二HKMG閘極堆疊各復包含高介電常數介電質、功函數金屬、多晶矽、以及氮化矽上蓋。
  4. 如申請專利範圍第3項所述之方法，復包括：於形成該嵌入式矽鍺前進行預清洗；以及最佳化該預清洗，以保護該氧化物硬遮罩。
  5. 如申請專利範圍第1項所述之方法，包括：形成該嵌入式矽鍺於該第一HKMG閘極堆疊之各側上，其係藉由：經由以氫氧化四甲基銨(TMAH)之濕式蝕刻形成孔穴；以及於該孔穴中磊晶成長矽鍺。
  6. 如申請專利範圍第5項所述之方法，復包括原位植入硼摻質至該嵌入式矽鍺中。
  7. 如申請專利範圍第6項所述之方法，包括以梯度摻雜分佈植入硼。
  8. 如申請專利範圍第1項所述之方法，復包括退火，以在形成該氧化物硬遮罩之後活化植入之摻質。
  9. 如申請專利範圍第1項所述之方法，包括經由以稀釋氫氟酸(dHF)之濕式蝕刻移除氧化物硬遮罩。
  10. 如申請專利範圍第9項所述之方法，復包括於移除該氧化物硬遮罩之後移除該氮化矽上蓋及該氮化物間隙壁。
  11. 如申請專利範圍第10項所述之方法，包括經由乾式或濕式蝕刻製程移除該氮化矽上蓋及該氮化物間隙壁。
  12. 如申請專利範圍第11項所述之方法，復包括形成矽化物於該源極/汲極區域、該嵌入式矽鍺、及該第一及第 二HKMG閘極堆疊上。
  13. 如申請專利範圍第1項所述之方法，復包括形成通道矽鍺區域在該第一HKMG閘極堆疊之下。
  14. 一種半導體裝置，包括：第一及第二高介電常數金屬閘極(HKMG)閘極堆疊，各自包含高介電常數介電質、功函數金屬、及多晶矽；氮化物襯墊，第一與第二氧化物間隙壁，且氧化物間隙壁依次地形成於各該第一及第二HKMG閘極堆疊之各側上；暈及延伸區域，位於各該第一及第二HKMG閘極堆疊之相反側，係形成於該第二氧化物間隙壁之前；深源極/汲極區域，位於該第二HKMG閘極堆疊之相反側上，係形成於該第二氧化物間隙壁之後，其中，該氮化物間隙壁係作為軟遮罩以用於該深源極/汲極之植入；以及嵌入式矽鍺，位於該第一HKMG閘極堆疊之相反側上，係利用該第二閘極堆疊之上的硬遮罩形成於該深源極/汲極區域之後。
  15. 如申請專利範圍第14項所述之裝置，其中，該氮化物間隙壁係形成於該第二氧化物間隙壁之上，以及位於該第二HKMG閘極堆疊之相反側上的該深源極/汲極區域係以該氮化物間隙壁作為該軟遮罩而形成。
  16. 如申請專利範圍第15項所述之裝置，其中，該氮化物 襯墊及該氮化物間隙壁包含氮化矽，以及該氧化物間隙壁包含二氧化矽。
  17. 如申請專利範圍第14項所述之裝置，其中，該嵌入式矽鍺係以具有梯度摻雜分佈之硼原位摻雜。
  18. 如申請專利範圍第14項所述之裝置，復包括矽化物，係位於該嵌入式矽鍺、該深源極/汲極區域、及該第一及第二HKMG閘極堆疊上。
  19. 如申請專利範圍第14項所述之裝置，復包括通道矽鍺區域，係位於該第一HKMG閘極堆疊之下。
  20. 一種形成半導體裝置的方法，包括：形成PMOS及NMOS高介電常數金屬閘極(HKMG)閘極堆疊於基板上；形成L型氮化矽襯墊及二氧化矽間隙壁於各該PMOS及NMOS之HKMG閘極堆疊之各側上；於各該PMOS及NMOS之HKMG閘極堆疊之各側執行暈/延伸植入；形成L型二氧化矽襯墊及氮化矽間隙壁於各該PMOS及NMOS之HKMG閘極堆疊之該二氧化矽間隙壁上；植入深源極/汲極區域在該NMOS之HKMG閘極堆疊之相反側；形成二氧化矽硬遮罩於該NMOS之HKMG閘極堆疊之上；形成嵌入式矽鍺於該PMOS之HKMG閘極堆疊之 相反側上，其係藉由：經由以氫氧化四甲基銨(TMAH)之濕式蝕刻在該PMOS之HKMG閘極堆疊之各側形成孔穴；於該孔穴中磊晶成長矽鍺；及於磊晶成長之同時，以梯度摻雜分佈原位植入硼摻質至該嵌入式矽鍺中；經由稀釋氫氟酸濕式蝕刻該二氧化矽硬遮罩；乾式或濕式蝕刻該氮化矽上蓋及該氮化矽間隙壁；以及形成矽化物於該源極/汲極區域、該嵌入式矽鍺、及該PMOS及NMOS之HKMG閘極堆疊上。
TW102109981A 2012-05-29 2013-03-21 使用氧化矽封裝、早暈及延伸植入於２８奈米低功率高效能技術之ｐｍｏｓ設備的晚原位摻雜矽鍺接合 TWI501398B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/482,393 US8936977B2 (en) 2012-05-29 2012-05-29 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Publications (2)

Publication Number Publication Date
TW201349504A TW201349504A (zh) 2013-12-01
TWI501398B true TWI501398B (zh) 2015-09-21

Family

ID=49669184

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102109981A TWI501398B (zh) 2012-05-29 2013-03-21 使用氧化矽封裝、早暈及延伸植入於２８奈米低功率高效能技術之ｐｍｏｓ設備的晚原位摻雜矽鍺接合

Country Status (3)

Country Link
US (2) US8936977B2 (zh)
CN (1) CN103456641B (zh)
TW (1) TWI501398B (zh)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9012956B2 (en) * 2013-03-04 2015-04-21 Globalfoundries Inc. Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe
CN103178014B (zh) * 2013-03-14 2016-01-27 上海华力微电子有限公司 一种u型沟槽的制造方法
CN104576378B (zh) * 2013-10-13 2017-12-12 中国科学院微电子研究所 一种mosfet结构及其制造方法
US20150214331A1 (en) * 2014-01-30 2015-07-30 Globalfoundries Inc. Replacement metal gate including dielectric gate material
US10153371B2 (en) 2014-02-07 2018-12-11 Stmicroelectronics, Inc. Semiconductor device with fins including sidewall recesses
US9721947B2 (en) * 2014-02-12 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US10008383B2 (en) * 2014-03-10 2018-06-26 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9466718B2 (en) 2014-03-31 2016-10-11 Stmicroelectronics, Inc. Semiconductor device with fin and related methods
TWI671805B (zh) 2014-06-18 2019-09-11 聯華電子股份有限公司 半導體元件及其製作方法
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102219295B1 (ko) 2014-07-25 2021-02-23 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
US20160071954A1 (en) * 2014-09-04 2016-03-10 Globalfoundries Inc. Robust post-gate spacer processing and device
US9343374B1 (en) * 2014-10-29 2016-05-17 Globalfoundries Inc. Efficient main spacer pull back process for advanced VLSI CMOS technologies
CN104409321B (zh) * 2014-10-30 2017-05-10 上海工程技术大学 一种使用NiTi合金外延生长NiSiGe材料的方法
US9703266B2 (en) 2014-11-04 2017-07-11 Spectracom Corporation Independent fiber-optic reference apparatuses and methods thereof
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
CN110120340B (zh) * 2015-06-16 2024-01-05 原相科技股份有限公司 半导体元件及其制造方法
US9601693B1 (en) 2015-09-24 2017-03-21 Lam Research Corporation Method for encapsulating a chalcogenide material
US10312334B2 (en) 2016-04-29 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid doping profile
US10629435B2 (en) 2016-07-29 2020-04-21 Lam Research Corporation Doped ALD films for semiconductor patterning applications
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US9865455B1 (en) 2016-09-07 2018-01-09 Lam Research Corporation Nitride film formed by plasma-enhanced and thermal atomic layer deposition process
US10832908B2 (en) 2016-11-11 2020-11-10 Lam Research Corporation Self-aligned multi-patterning process flow with ALD gapfill spacer mask
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US10460925B2 (en) * 2017-06-30 2019-10-29 United Microelectronics Corp. Method for processing semiconductor device
US20190081145A1 (en) * 2017-09-12 2019-03-14 Globalfoundries Inc. Contact to source/drain regions and method of forming same
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
WO2019169335A1 (en) 2018-03-02 2019-09-06 Lam Research Corporation Selective deposition using hydrolysis
US10998241B2 (en) * 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
US10756184B2 (en) 2018-11-05 2020-08-25 Globalfoundries Inc. Faceted epitaxial source/drain regions
FR3095549B1 (fr) * 2019-04-25 2021-05-21 Commissariat Energie Atomique Procede de realisation d’un transistor dont la zone active comporte un materiau semi-metallique
CN110491780A (zh) * 2019-08-27 2019-11-22 上海华力集成电路制造有限公司 增大多晶硅栅极硬掩膜去除工艺窗口的方法
CN114121660B (zh) * 2020-08-31 2024-03-12 联华电子股份有限公司 半导体元件及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110024840A1 (en) * 2009-07-29 2011-02-03 International Business Machines Corporation Soi transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US20110104863A1 (en) * 2009-10-30 2011-05-05 Sven Beyer Transistor including a high-k metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer
US20110254090A1 (en) * 2010-04-14 2011-10-20 International Business Machines Corporation Raised source/drain structure for enhanced strain coupling from stress liner
US20120001228A1 (en) * 2006-04-05 2012-01-05 International Business Machines Corporation (Ibm) Method to control source/drain stressor profiles for stress engineering
US20120056245A1 (en) * 2010-09-07 2012-03-08 Samsung Electronics Co., Ltd. Semiconductor devices including silicide regions and methods of fabricating the same
US20120153399A1 (en) * 2010-12-16 2012-06-21 Globalfoundries Inc. Low-Diffusion Drain and Source Regions in CMOS Transistors for Low Power/High Performance Applications

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6949482B2 (en) * 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
US7652332B2 (en) * 2007-08-10 2010-01-26 International Business Machines Corporation Extremely-thin silicon-on-insulator transistor with raised source/drain
US8338292B2 (en) * 2009-02-18 2012-12-25 International Business Machines Corporation Body contacts for FET in SOI SRAM array
US9318571B2 (en) * 2009-02-23 2016-04-19 United Microelectronics Corp. Gate structure and method for trimming spacers
JP5442332B2 (ja) * 2009-06-26 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
US8022488B2 (en) * 2009-09-24 2011-09-20 International Business Machines Corporation High-performance FETs with embedded stressors
US8513106B2 (en) * 2010-12-09 2013-08-20 International Business Machines Corporation Pseudo butted junction structure for back plane connection
DE102011003439B4 (de) * 2011-02-01 2014-03-06 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Durchlassstromerhöhung in Feldeffekttransistoren durch asymmetrische Konzentrationsprofile von Legierungssubstanzen einer Kanalhalbleiterlegierung und Halbleiterbauelement
US20130065367A1 (en) * 2011-09-13 2013-03-14 Globalfoundries Inc. Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120001228A1 (en) * 2006-04-05 2012-01-05 International Business Machines Corporation (Ibm) Method to control source/drain stressor profiles for stress engineering
US20110024840A1 (en) * 2009-07-29 2011-02-03 International Business Machines Corporation Soi transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US20110104863A1 (en) * 2009-10-30 2011-05-05 Sven Beyer Transistor including a high-k metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer
US20110254090A1 (en) * 2010-04-14 2011-10-20 International Business Machines Corporation Raised source/drain structure for enhanced strain coupling from stress liner
US20120056245A1 (en) * 2010-09-07 2012-03-08 Samsung Electronics Co., Ltd. Semiconductor devices including silicide regions and methods of fabricating the same
US20120153399A1 (en) * 2010-12-16 2012-06-21 Globalfoundries Inc. Low-Diffusion Drain and Source Regions in CMOS Transistors for Low Power/High Performance Applications

Also Published As

Publication number Publication date
US20150054072A1 (en) 2015-02-26
CN103456641B (zh) 2016-12-07
TW201349504A (zh) 2013-12-01
US8936977B2 (en) 2015-01-20
US20130320449A1 (en) 2013-12-05
CN103456641A (zh) 2013-12-18

Similar Documents

Publication Publication Date Title
TWI501398B (zh) 使用氧化矽封裝、早暈及延伸植入於２８奈米低功率高效能技術之ｐｍｏｓ設備的晚原位摻雜矽鍺接合
US8975704B2 (en) Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
US7888195B2 (en) Metal gate transistor and method for fabricating the same
CN102456691B (zh) 半导体装置和半导体装置制造方法
CN103545213B (zh) 半导体器件及其制造方法
US8980753B2 (en) Metal gate transistor and method for fabricating the same
US20140167110A1 (en) Partial poly amorphization for channeling prevention
US8518784B2 (en) Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment
US8129236B2 (en) Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode
WO2011075989A1 (zh) 形成有沟道应力层的半导体结构及其形成方法
US8039342B2 (en) Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal
US9343374B1 (en) Efficient main spacer pull back process for advanced VLSI CMOS technologies
TW202018777A (zh) 一種製作半導體元件的方法
US20090057786A1 (en) Semiconductor device and method of manufacturing semiconductor device
US7994591B2 (en) Semiconductor device and method for manufacturing the same
US20130040435A1 (en) Method for manufacturing transistor and semiconductor device
US20150349065A1 (en) Transistor structure including epitaxial channel layers and raised source/drain regions
CN103594374B (zh) 半导体器件制造方法
KR100679812B1 (ko) 모스 트랜지스터 및 그 제조 방법
US20080124879A1 (en) Method for Fabricating Semiconductor Device
CN104779286A (zh) 一种nmosfet器件及其制备方法
JP2004014779A (ja) 半導体装置および半導体装置の製造方法
JP2006049781A (ja) 絶縁ゲート型半導体装置及びその駆動方法
JP2004281693A (ja) 半導体装置及びその製造方法
JP2009111145A (ja) 半導体装置の製造方法