US20110104863A1 - Transistor including a high-k metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer - Google Patents
Transistor including a high-k metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer Download PDFInfo
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- US20110104863A1 US20110104863A1 US12/894,579 US89457910A US2011104863A1 US 20110104863 A1 US20110104863 A1 US 20110104863A1 US 89457910 A US89457910 A US 89457910A US 2011104863 A1 US2011104863 A1 US 2011104863A1
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- spacer
- gate electrode
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- 1. Field of the Invention
- Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
- 2. Description of the Related Art
- The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
- Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
- For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and, thus, reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
- For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials also may have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided. The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence due to, for instance, the adjustment of an appropriate work function for the transistors of different conductivity type and the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required. In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on the plurality of well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and, in particular, the sensitive high-k dielectric materials in combination with any metal-containing cap layers may remain reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
- Further concepts for enhancing performance of transistors have been developed by providing a plurality of strain-inducing mechanisms in order to increase the charge carrier mobility in the channel regions of the various transistors. It is well known that charge carrier mobility in silicon may be efficiently increased by applying certain strain components, such as tensile and compressive strain for N-channel transistors and P-channel transistors, respectively, so that superior transistor performance may be obtained for an otherwise identical transistor configuration compared to non-strained silicon materials. For instance, efficient strain-inducing mechanisms may be implemented by incorporating a strained semiconductor material in the drain and source regions of transistors, for instance in the form of a silicon/germanium alloy, a silicon/carbon alloy and the like, wherein the lattice mismatch between the semiconductor alloy and the silicon base material may result in a tensile or compressive state, which in turn may induce a desired type of strain in the channel region of the transistor. Other efficient strain-inducing mechanisms are well established in which a highly stressed dielectric material may be positioned in close proximity to the transistor, thereby also inducing a certain type of strain in the channel region.
- Although the approach of providing a sophisticated high-k metal gate electrode structure in an early manufacturing stage, possibly in combination with additional strain-inducing mechanisms, may have the potential of providing extremely powerful semiconductor devices, such as CPUs, storage devices, systems on a chip (SOC) and the like, conventional approaches may still suffer from process non-uniformities, as will be described with reference to
FIGS. 1 a-1 f. -
FIG. 1 a schematically illustrates a cross-sectional view of asemiconductor device 100 comprising asubstrate 101, such as a silicon substrate, in combination with asemiconductor layer 102, such as a silicon layer or a semiconductor material comprising a significant amount of silicon. In the manufacturing stage shown, thesemiconductor device 100 further comprisestransistors active region layer 102 in which PN junctions for one or more transistors are to be formed. An isolation structure 102C, such as a trench isolation, is provided in thesemiconductor layer 102 and may laterally delineate active regions, such as theregions gate electrode structures semiconductor layer 102. InFIG. 1 a, thegate electrode structures gate electrode structures active regions gate electrode structure 160C may represent a corresponding portion of a gate electrode structure or may represent a conductive line or any other circuit element, such as a resistive structure and the like, which may have a similar configuration as thegate electrode structures gate insulation layer 161 formed on theactive region gate insulation layer 161 may additionally comprise a conventional dielectric material, such as a silicon oxide-based material, however, with a significantly reduced thickness of approximately 0.8 nm and less. Consequently, in total, thegate insulation layer 161 may have a thickness of 1.5 nm and more, while still providing an oxide equivalent thickness that may be 1 nm and less, while leakage currents may be significantly less compared to a conventional extremely thin silicon oxide-based material. Moreover, a metal-containing material may be formed on thegate insulation layer 161 and may have a different composition for transistors of different conductivity type. For example, aconductive cap layer 162A may be provided in thegate electrode structure 160A including a work function adjusting species for thetransistor 150A, while aconductive cap layer 162B including a work function species for thetransistor 150B may be applied in thegate electrode structure 160B. Typically, thegate electrode structure 160C may have one of thelayers electrode material 163, such as silicon, silicon/germanium and the like, may be formed above theconductive cap layers dielectric cap layer 164, which is typically comprised of silicon nitride. - Furthermore, a
sidewall spacer structure 165, which may comprise aliner material 165A in combination with aspacer element 165B may be provided so as to protect the sidewalls of theelectrode material 163 and in particular of thesensitive materials liner 165A and thespacer element 165B may typically be comprised of silicon nitride. As illustrated, above the active region 102 b and thegate electrode structure 160B, thematerials semiconductor material 151 in theactive region 102A so as to increase the charge carrier mobility in achannel region 152 of thetransistor 150A. Moreover, theactive region 102A may comprise asemiconductor alloy 152A in the channel region, for instance a silicon/germanium alloy, in order to adjust the band gap offset of the channel region, thereby obtaining a desired threshold voltage in combination with thematerials transistor 150A. - As previously discussed, the
semiconductor alloy 151, for instance provided in the form of a silicon/germanium alloy, may have a strained state and may thus induce a desired strain in thechannel region 152. For instance, silicon/germanium may represent a very efficient strain-inducing source for P-channel transistors. - The
semiconductor device 100 as illustrated inFIG. 1 a may be formed on the basis of the following conventional process strategies. After forming the isolation region 102C and thus delineating theactive regions material layer 152A may be formed selectively in theactive region 102A. Next, appropriate materials for thegate insulation layer 161 and one of thelayers layers gate insulation layer 161. Prior to or after the corresponding adjustment of the work function, theelectrode material 163, for instance in the form of silicon, may be deposited on the basis of well-established deposition techniques, followed by the deposition of thedielectric cap layer 164. Furthermore, additional materials, such as hard mask materials and the like, may be provided if required and thereafter a sophisticated lithography process and an anisotropic etch sequence may be performed in order to obtain thegate electrode structures dielectric cap layer 164 may thus provide superior efficiency of the patterning process and may also be used during the subsequent processing so as to encapsulate theelectrode material 163 and thematerials gate electrode structures FIG. 1 a, a horizontal extension of theelectrode material 163, may be 50 nm and less. Next, thematerials liner material 165A as a very dense silicon nitride material so as to reliably confine the sidewalls of the gate electrode structures. Thereafter, an etch mask may be provided to cover thetransistor 150B in order to form thespacer elements 165B and possibly etch into theactive region 102A in order to form corresponding cavities therein. During the corresponding etch process, thespacer structure 165 may substantially determine a lateral offset of the corresponding cavities with respect to thechannel region 152. Next, a selective epitaxial growth process is performed in order to grow the strain-inducingsemiconductor material 151. During a selective epitaxial growth process, process parameters are adjusted such that a significant material deposition on dielectric surface areas, such as the cap layers 164, the material 165B and the isolation region 102C, is substantially suppressed. -
FIG. 1 b schematically illustrates thesemiconductor device 100 in a manufacturing stage in which anetch mask 103 covers theactive region 102A and possibly the isolation region 102C, while exposing thegate electrode structure 160B and theactive region 102B. Moreover, anetch process 104 is applied so as to obtain thespacer structure 165 on sidewalls of thegate electrode structure 160B. For this purpose, well-established plasma assisted etch recipes are applied. It should be appreciated that, during theetch process 104, a certain amount of material erosion in theactive region 102B or material modification may occur, depending on the etch chemistry used. For example, plasma assisted etch recipes for removing silicon nitride may exhibit a self-limiting behavior when etching a silicon material, which may be caused by the generation of silicon dioxide, which may then act as an efficient etch stop material. - Thereafter, the
etch mask 103 may be removed and thus thegate electrode structures sidewall spacer structure 165, which may be used as an offset spacer structure for controlling a subsequent implantation sequence for introducing dopant species so as to form drain and source extension regions and halo regions, i.e., counter-doped regions, in order to obtain the required complex dopant profile for adjusting the overall transistor characteristics. During the further processing, the dielectric cap layers 164 may also have to be removed, which may, however, have a significant influence on the resulting device topography and thus on the resulting transistor characteristics. For instance, upon removing thedielectric cap material 164, etch chemistries, such as hot phosphoric acid, are typically applied which, however, may exhibit a significant lateral etch rate, thereby causing a significant degree of material erosion of thespacer structure 165. For this reason, thespacer structure 165 is protected by providing a sacrificial oxide spacer element having a high etch resistivity with respect to hot phosphoric acid. -
FIG. 1 c schematically illustrates thesemiconductor device 100 with anoxide spacer layer 166, which may be etched during anetch process 105 in order to formsacrificial oxide spacers 166S on thesidewall spacer structure 165. Consequently, during theetch process 105, a certain degree ofmaterial erosion 105R may occur in the isolation structure 102C due to a certain required overetch time during which oxide material of the isolation structure 102C is removed. -
FIG. 1 d schematically illustrates thedevice 100 when exposed to afurther etch process 106 for removing the dielectric cap material 164 (FIG. 1 c) on the basis of hot phosphoric acid. As discussed above, during theetch process 106, the siliconnitride spacer structure 165 is protected by thesacrificial spacer elements 166S. -
FIG. 1 e schematically illustrates thesemiconductor device 100 in a further advanced manufacturing stage. As illustrated, the sacrificial sidewall spacers 166 s (FIG. 1 d) are removed, which may be accomplished on the basis of diluted hydrofluoric acid (HF), which, however, may also remove a further portion of the isolation structure 102C, thereby increasing therecess 105R. Consequently, after the removal of the dielectric cap layer 164 (FIG. 1 c), a pronounced surface topography in the form of therecess 105R may be created, which may have a significant influence on the further processing. -
FIG. 1 f schematically illustrates thesemiconductor device 100 in a further advanced manufacturing stage. As illustrated, a furthersidewall spacer structure 155 is formed adjacent to the spacer structure 165 (FIG. 1 e) and is typically comprised of silicon nitride, possibly in combination with a silicon dioxide etch stop liner (not shown). Furthermore, drain andsource regions 153 are formed in theactive regions transistors metal silicide regions 154 are formed in the drain andsource regions 153 andmetal silicide regions 167 are provided in thegate electrode structures dielectric layer 120, which may have a high internal stress level, is formed above theactive regions gate electrode structures layer 120 and the amount of highly stressed material positioned in close proximity to thechannel region 152, which in turn may thus depend on the thickness of thelayer 120. Consequently, in view of enhancing transistor performance, an increased layer thickness is highly desirable for thelayer 120, which, however, may be restricted by the pronounced surface topography, in particular in the isolation region 102C. That is, in device areas comprising closely spaced gate electrode structures extending along an isolation region, such as the region 102C, the pronounced recessing caused by the previous processing may additionally increase the resulting aspect ratio that is “seen” during the deposition of thematerial 120. Consequently, in view of the pronounced recessing of the isolation structure 102C, a reduced thickness of thelayer 120 may have to be provided in order to avoid deposition-related irregularities, which may otherwise result in significant yield losses during the further processing, for instance when forming contact elements and the like. - The
semiconductor device 100 as illustrated inFIG. 1 f may be formed in accordance with the following process techniques. Thespacer structure 155 is typically formed by depositing a silicon nitride material, possibly in combination with a silicon dioxide etch stop liner, and patterning the silicon nitride layer so as to obtain a spacer element, as shown. Prior to and after forming thesidewall spacer structure 155, implantation processes are performed in order to introduce dopant species, thereby forming the drain andsource regions 153. After any anneal processes in which the final dopant profile may be established, further cleaning processes are performed in order to prepare the exposed semiconductor surface areas for forming themetal silicide regions spacer structure 155 may substantially determine the lateral offset of themetal silicide regions 154 with respect to thechannel region 152. Next, thedielectric material 120 is deposited, wherein, depending on the process requirements, a complex deposition and patterning sequence may also have to be applied when dielectric materials of different internal stress levels are to be provided above thetransistor 150A and thetransistor 150B. During the corresponding deposition process or processes, the pronounced surface topography has to be taken into consideration, as discussed above, thereby possibly reducing the efficiency of the strain-inducing effect of thedielectric material 120. - Consequently, although the conventional approach may provide high performance transistors on the basis of the high-k metal
gate electrode structures dielectric cap layer 164, results in reduced device performance and increased yield loss. - The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the present disclosure provides manufacturing techniques in which a sophisticated high-k metal gate electrode structure may be provided in an early manufacturing stage. Furthermore, a sidewall spacer structure required for reliably confining sensitive materials of the gate electrode structure may be preserved throughout the entire process flow and, in particular, the removal of a dielectric cap material of the gate electrode structure, which may be accomplished by providing a sacrificial spacer structure. The sacrificial spacer structure, or at least a significant portion thereof, may be removed substantially without affecting the resulting surface topography, thereby enabling the further processing on the basis of superior process conditions, which in turn may translate into enhanced performance and reliability of the resulting semiconductor device. In some illustrative aspects, the sacrificial spacer structure may comprise a carbon spacer element, which may provide high etch resistivity with respect to a plurality of plasma-assisted etch processes, for instance as used for removing silicon nitride materials, while, on the other hand, a carbon material may be efficiently removed, for instance, on the basis of an oxygen plasma, substantially without affecting other device areas, such as silicon oxide based isolation structures and the like.
- One illustrative method disclosed herein comprises forming a gate electrode structure of a transistor above a semiconductor region of a semiconductor device. The gate electrode structure comprises a gate insulation layer comprising a high-k gate dielectric material, a metal-containing cap material formed on the gate insulation layer, an electrode material formed above the cap material, a dielectric cap layer formed above the electrode material and a sidewall spacer structure. The method additionally comprises forming a sacrificial carbon spacer on the sidewall spacer structure and removing the dielectric cap layer by using the sacrificial carbon spacer as an etch stop material for protecting the sidewall spacer structure. Moreover, the sacrificial carbon spacer is removed.
- One further illustrative method disclosed herein relates to forming a transistor of a semiconductor device. The method comprises forming a strain-inducing semiconductor alloy in an active region in the presence of a gate electrode structure, which comprises a high-k dielectric material, an electrode material, a dielectric cap layer and a sidewall spacer structure. The method further comprises forming a sacrificial spacer structure on the sidewall spacer structure and removing the dielectric cap layer selectively to the sacrificial spacer structure by performing a plasma-assisted etch process. The method further comprises removing at least a portion of the sacrificial spacer structure and forming drain and source regions in the active region.
- A still further illustrative method disclosed herein relates to forming a semiconductor device. The method comprises forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region. The method further comprises forming a first spacer structure selectively on sidewalls of the first gate electrode structure from a spacer layer, wherein a remaining portion of the spacer layer covers the second gate electrode structure and the second active region. The method further comprises forming a strain-inducing semiconductor material in the first active region by using the first spacer structure, the remaining portion of the spacer layer and a dielectric cap layer of the first and second gate electrode structures as a mask. Additionally, the method comprises forming a second spacer structure on sidewalls of the second gate electrode structure from the remaining portion of the spacer layer and forming a protective spacer structure on the first and second spacer structures, wherein the protective spacer structure comprises a carbon spacer element. The method additionally comprises removing the dielectric cap layer from the first and second gate electrode structures by using the protective spacer structure as an etch mask. Furthermore, drain and source regions are formed in the first and second active regions.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1 a-1 f schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages in providing a sophisticated high-k metal gate electrode structure in combination with a strain-inducing material on the basis of a conventional strategy, in which integrity of the gate electrode structure may be maintained on the basis of a sidewall spacer structure in combination with a sacrificial oxide spacer; and -
FIGS. 2 a-2 d schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages in which a sidewall spacer structure of a sophisticated gate electrode structure may be protected during the removal of a dielectric cap material on the basis of a sacrificial spacer element, which may comprise a carbon spacer, in accordance with illustrative embodiments. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
- The present disclosure provides manufacturing techniques in which the superior characteristics of a carbon material may be taken advantage of in protecting a sophisticated sidewall spacer structure during a critical manufacturing phase in which a dielectric cap material is to be removed from a sophisticated gate electrode structure. As is well known, amorphous carbon material may be increasingly used as an efficient hard mask material in complex patterning processes during semiconductor fabrication, since amorphous carbon may be deposited on the basis of plasma enhanced CVD techniques within a wide range of process temperatures and with moderately high deposition rates. Furthermore, the amorphous carbon material may be efficiently removed on the basis of oxygen plasma recipes, substantially without affecting other material systems, such as semiconductor materials, silicon dioxide, silicon nitride and the like. Consequently, amorphous carbon material may be used as a very efficient “sacrificial” material due to its high etch resistivity in plasma-based reactive etch processes and due to the efficient removal behavior during oxygen-based plasmas. According to the principles disclosed herein, the complex process sequence, as previously described with reference to the
semiconductor device 100 inFIGS. 1 a-1 f, may be modified in order to reduce the pronounced surface topography, resulting from the removal of a dielectric cap layer of sophisticated gate electrode structures, by implementing a sacrificial spacer structure, which may include at least one carbon spacer element, which may be removed substantially without affecting sensitive device areas, such as active regions and, in particular, isolation regions. In order to efficiently use a carbon-based sacrificial spacer structure, the etch process for removing the dielectric cap material may be performed on the basis of a plasma-assisted etch process, wherein, as discussed above, a lateral etch rate may not negatively affect the gate electrode structure and a corresponding spacer structure formed thereon due to the presence of the carbon-based sacrificial spacer structure, which has a high etch selectivity with respect to the plasma etch ambient. Consequently, the integrity of the sophisticated gate electrode structures may be preserved throughout the entire process flow without contributing to an undesired pronounced surface topography. - With reference to
FIGS. 2 a-2 d, further illustrative embodiments will now be described in more detail, wherein reference is also made toFIGS. 1 a-1 f. -
FIG. 2 a schematically illustrates a cross-sectional view of asemiconductor device 200 comprising asubstrate 201, in and above which may be formed asemiconductor layer 202, such as a silicon layer, a silicon/germanium layer and the like. Moreover, thesemiconductor layer 202 may compriseactive regions active region 202A and/or theactive region 202B. Atransistor 250A may be formed in and above theactive region 202A and may comprise, in the manufacturing stage shown, agate electrode structure 260A. Similarly, atransistor 250B may be formed in and above theactive region 202B and may comprise agate electrode structure 260B. As is also previously discussed with reference to thesemiconductor device 100, thegate electrode structures gate electrode structure 260C may thus be formed above the isolation structure 202C and may extend to other active regions (not shown) that are located laterally adjacent to the structure 202C in a direction perpendicular to the drawing plane ofFIG. 2 a. In the example shown, thegate electrode structures gate electrode structure 260B may represent an N-channel transistor. It should be appreciated, however, that any other configuration may be contemplated by the present disclosure. Thus, thegate electrode structures dialectic material 261 in combination with aconductive cap material 262A, which may also include an appropriate metal species for adjusting the work function of thegate electrode structures transistor 250A. Moreover, anelectrode material 263, such as a silicon material and the like, may be provided above thelayers 262A. Moreover, adielectric cap layer 264, such as a silicon nitride material, may be formed above theelectrode material 263. As indicated, athin oxide layer 268 may be formed between the material 263 and thedielectric cap layer 264, if required. On the other hand, thegate electrode structure 260B may comprise a gatedialectic material 261 with aconductive cap layer 262B, which may be appropriately configured so as to obtain the desired work function for thegate electrode structure 260B. On the other hand,materials gate electrode structure 260B. Additionally, thegate electrode structures sidewall spacer structure 265 in order to confine the sensitive materials, in particular thematerials semiconductor device 100. As illustrated, thespacer structure 265 may comprise aliner material 265A in combination with aspacer element 265B, while, in other cases, a sidewall spacer element may be provided. It should be appreciated that, with respect to the components described so far, the same criteria may apply as previously described with reference to thedevice 100 when referring to these components. - Moreover, in the manufacturing stage shown, the
transistor 250A may comprise a strain-inducingsemiconductor alloy 251, such as a silicon/germanium alloy and the like, in order to provide a desired strain component in achannel region 252. Furthermore, thechannel region 252 may comprise a threshold adjustingsemiconductor alloy 252A, if required, for instance in the form of a silicon/germanium material. In some illustrative embodiments, drain andsource extension regions 253E may be provided in theactive regions regions 253E may be formed in a later manufacturing stage. It should be appreciated that, additionally, any counter-doped regions (not shown), typically referred to as “halo regions,” may be provided together with theextension regions 253E in order to establish the desired complex dopant profile so as to adjust a threshold voltage of thetransistors gate electrode structures - Moreover, in the manufacturing stage shown, a
sacrificial spacer structure 266S may be formed on thespacer structures 265 and may comprise, in one illustrative embodiment, a carbon-based spacer element. In the embodiment shown, thespacer structure 266S may be substantially provided in the form of a single carbon spacer element, while, in other cases, if required, additional material layers (not shown), such as thin oxide liners, nitride liners and the like, may be provided in addition to a carbon-based spacer element, if desired. - The
semiconductor device 200 may be formed on the basis of the following processes. Theactive regions semiconductor device 100. Similarly, at any appropriate manufacturing stage, thethreshold adjusting material 252A may be selectively formed in theactive region 202A, which may be accomplished by epitaxial growth techniques and the like. Thereafter, thegate electrode structures dielectric cap layer 264 and thespacer structure 265 may be formed in accordance with any appropriate manufacturing technique, as is also described with reference to thesemiconductor device 100. Hence, work function adjusting species in thelayers dielectric material 261, which may include a high-k dielectric material. After the patterning of thematerials spacer structure 265 may be formed by depositing a spacer layer, as previously described, and selectively patterning the spacer layer to obtain thespacer structure 265, for instance, selectively on sidewalls of thegate electrode structures transistor 250B and theactive region 202B, as is previously described with reference toFIG. 1 a. - Thereafter, the strain-inducing
semiconductor material 251 may be formed, as previously described, followed by the patterning of the spacer layer covering theactive region 202B and thegate electrode structure 260B in order to obtain thesidewall spacer structure 265 for thegate electrode structure 260B, as is also previously described with reference toFIG. 1 b. In some illustrative embodiments, the drain andsource extension regions 253E may be formed on the basis of an appropriate implantation sequence, which may include an appropriate masking regime for alternatively covering thetransistors active regions channel region 252. It should be appreciated that, due to the presence of thecap layer 264, an increased implantation energy may be used for forming the halo regions or counter-doped regions, thereby obtaining a superior distribution of the counter-doping species, while thecap layer 264 may suppress undue penetration of lower portions of theelectrode material 263. - In other illustrative embodiments, the
extension regions 253E and the halo regions may be formed in a later manufacturing stage. Next, thespacer layer 266 may be formed so as to comprise a carbon layer, possibly in combination with additional liner materials, if required. As discussed above, carbon material may readily be established on the basis of plasma-enhanced CVD techniques using any type of hydrocarbon gas as a precursor material. Furthermore, on the basis of additional gases, such as nitrogen, hydrogen, helium, argon and the like, specific characteristics, such as density and the like, of the carbon material may be adjusted. For example, thespacer layer 266 may be provided with a thickness of approximately 10-40 nm, while other thickness values may also be used, if considered appropriate. Thereafter, anetch process 211 may be performed to form thesacrificial spacer structure 266S from thespacer layer 266, which may be accomplished on the basis of plasma-assisted etch recipes using an oxygen plasma, wherein a certain lateral etch rate may be taken into consideration by appropriately selecting the initial thickness of thespacer layer 266. As previously explained, in particular by applying an oxygen plasma, a material removal in theactive regions sacrificial spacer structure 266S may be provided without deteriorating the surface topography in the isolation region 202C. -
FIG. 2 b schematically illustrates thesemiconductor device 200 in a further advanced manufacturing stage in which thedevice 200 is exposed to anetch process 206 in order to remove the dielectric cap layers 264 from thegate 260B, 260C. In one illustrative embodiment, theelectrode structures 260Aetch process 206 may be performed as a plasma-assisted etch process by using well-established etch chemistries, in which silicon nitride material may be removed selectively with respect to oxide and also selectively with respect to silicon material. Typically, a plasma-assisted silicon nitride etch process may have a certain lateral etch rate, which, however, may not substantially affect thesidewall spacer structure 265 due to the presence of thesacrificial spacer 266S comprising a carbon material, which has a significantly reduced etch rate when exposed to the etch ambient 206. Thus, during theprocess 206, any undue material erosion in the isolation structure 202C may be substantially avoided. On the other hand, in theactive regions etch chemistry 206 may result in the formation of a thin silicon oxide material (not shown), which may thus suppress a further material erosion during theprocess 206. -
FIG. 2 c schematically illustrates thesemiconductor device 200 in a further advanced manufacturing stage in which thesacrificial spacer structure 266S or at least a carbon spacer element may be removed during aprocess 212, which may be performed on the basis of an oxygen plasma. Consequently, during theprocess 212, at least the carbon material of thespacer structure 266S may be efficiently removed, substantially without affecting other exposed device areas, such as the isolation structure 202C and theactive regions gate electrode structures spacer structure 266S, theprocess 212 for removing the carbon material may not substantially affect the isolation structure 202C, thereby preserving a desired substantially planar surface topography. After the removal of thesacrificial spacer structure 266S, the processing may be continued, in some illustrative embodiments, by forming the drain and source extension regions (not shown inFIG. 2 c), wherein the corresponding implantation energies, in particular the energy of the implantation step for incorporating the counter-doping species, may be adapted to the resulting reduced height of thegate electrode structures FIG. 2 b). -
FIG. 2 d schematically illustrates thesemiconductor device 200 in a further advanced manufacturing stage. As illustrated, thetransistors source regions 253 including theextension regions 253E, in whichmetal silicide regions 254 may also be provided. Furthermore, thegate electrode structures metal silicide regions 267, such as nickel silicide, platinum silicide, a combination thereof and the like. Moreover, a furthersidewall spacer structure 255 may be formed adjacent to thespacer structure 265 and may comprise one or more spacer elements, such as silicon nitride spacers, silicon oxide spacers and the like, in combination with one or more etch stop liners (not shown), depending on the overall device and process requirements. Furthermore, adielectric material 220 may be formed above theactive regions gate electrode structures dielectric layer 220 may comprise a highly-stressed dielectric material so as to enhance performance of one or both of thetransistors layer portion 220A may be formed above the structure 202C and theactive region 202A with a high internal stress level, such as a compressive stress, in order to enhance performance of thetransistor 250A together with the strain-inducingmaterial 251. On the other hand, alayer portion 220B may be formed above thegate electrode structure 260B and theactive region 202B with an internal stress level so as to enhance performance of thetransistor 250B, for instance by inducing a tensile strain component in the channel region of thetransistor 250B. Furthermore, a certain degree of material erosion, indicated as 205R may have occurred, thereby contributing to a certain degree of recessing in the isolation structure 202C, which, however, may be significantly less pronounced compared to a corresponding recessing obtained in accordance with conventional strategies, as previously explained with reference toFIG. 1 f. - The
semiconductor device 200 as illustrated inFIG. 2 d may be formed in accordance with any appropriate process strategies, for instance as also described with reference to thesemiconductor device 100. Thus, during the process sequence, the recessing 205R in the isolation structure 202C may be substantially caused by any cleaning processes and by a pre-cleaning process prior to forming themetal silicide regions semiconductor device 100. Consequently, after the silicidation process, thedielectric material 220 may be provided on the basis of a less-pronounced surface topography compared to conventional devices, thereby enabling an enhanced degree of flexibility in forming thedielectric material 220 and any further dielectric materials to be formed on thematerial 220. For example, the less pronounced surface topography may reduce the probability of creating deposition-related irregularities, such as voids, in particular in isolation regions comprising a plurality of closely-spaced gate electrode structures, such as thestructure 260C. Consequently, during the further processing, for instance for forming contact openings in an interlayer dielectric material to be formed above thedielectric material 220, the probability of creating leakage paths upon filling the contact openings with a conductive material may be reduced. Moreover, the less pronounced surface topography may provide the possibility of depositing an increased layer thickness of a highly-stressed dielectric material above thetransistors - As a result, the present disclosure provides manufacturing techniques, in which sophisticated gate electrode structures may be formed on the basis of a high-k dielectric material and work function adjusting species in an early manufacturing stage by confining the sensitive materials by an appropriate spacer structure. On the other hand, the integrity of the spacer structure may be preserved during the removal of a dielectric cap material by providing a sacrificial spacer structure, which may comprise at least one carbon-based spacer material. Since carbon may be efficiently patterned and removed substantially without affecting other materials, such as silicon dioxide, a corresponding material erosion, as may typically occur in conventional approaches, may be reduced, thereby providing superior process conditions during the further processing of the semiconductor device. Hence, reduced yield losses, for instance caused by contact failures, in combination with superior device performance, may be accomplished by using a carbon-based sacrificial spacer element.
- The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
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DE102009046261A DE102009046261B4 (en) | 2009-10-30 | 2009-10-30 | A method of fabricating transistors having large ε metal gate electrode structures made in front of the sacrificial carbon spacer based drain / source regions |
DE102009046261.9 | 2009-10-30 | ||
DE102009046261 | 2009-10-30 |
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US20140235045A1 (en) * | 2013-02-19 | 2014-08-21 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
CN104078426A (en) * | 2013-03-27 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
US8877642B2 (en) * | 2013-02-01 | 2014-11-04 | Globalfoundries Inc. | Double-pattern gate formation processing with critical dimension control |
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US20140235045A1 (en) * | 2013-02-19 | 2014-08-21 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
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