CN103456641B - Pmos设备的晚原位掺杂硅锗接合 - Google Patents

Pmos设备的晚原位掺杂硅锗接合 Download PDF

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CN103456641B
CN103456641B CN201310202981.3A CN201310202981A CN103456641B CN 103456641 B CN103456641 B CN 103456641B CN 201310202981 A CN201310202981 A CN 201310202981A CN 103456641 B CN103456641 B CN 103456641B
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stack
dielectric constant
metal grid
constant metal
grid pole
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CN103456641A (zh
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J·亨治尔
S·Y·翁
S·弗莱克豪斯基
T·沙伊普
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GlobalFoundries Singapore Pte Ltd
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Abstract

本发明涉及PMOS设备的晚原位掺杂硅锗接合。实施例包含形成第一及第二高介电常数金属栅极栅极堆栈于基板上、形成氮化物衬垫及氧化物间隙壁于各该第一及第二高介电常数金属栅极栅极堆栈的各侧、于各该第一及第二高介电常数金属栅极栅极堆栈的各侧执行晕/延伸植入、形成氧化物衬垫及氮化物间隙壁于各该第一及第二高介电常数金属栅极栅极堆栈的该氧化物间隙壁上；形成深源极/漏极区域在该第二高介电常数金属栅极栅极堆栈的相反侧上；形成氧化物硬掩模于该第二高介电常数金属栅极栅极堆栈之上；形成嵌入式硅锗于该第一高介电常数金属栅极栅极堆栈的相反侧上；以及移除该氧化物硬掩模。

Description

PMOS设备的晚原位掺杂硅锗接合
技术领域
本发明是关于一种具有嵌入式硅锗(silicon germanium,SiGe)的源极/漏极区域的高介电常数金属栅极(High-K Metal Gate,HKMG)半导体装置。本发明是特别适用于28奈米(nm)的超级低功率(28nmsuper-low-power,28SLP)技术。
背景技术
在目前的行动/多媒体市场中，对于长待机时间，确切的说，低漏电产品有巨大的需求。28SLP制程原本是设计来满足此需求。然而，对于高效能且低功耗也有需求。用于高效能的驱动需要要求高驱动电流的微电子组件的高速运作。典型地，倾向于提供所需要的驱动电流的增加的结构及掺杂参数对于漏电电流会有不利的影响。高介电常数金属栅极(High-k metal gate,HKMG)电极是发展来通过降低多晶硅空乏(polysilicon depletion)以改善驱动电流。
在现代的CMOS技术中，嵌入式硅锗(silicon germanium,SiGe)的源极/漏极区域在PFET装置中为标准的，因其通过导入单轴应变至信道中来改善效能。然而，至今28SLP制程并未包含例如硅锗的嵌入式源极/漏极压力源(stressor)在p活跃(p-active)的源极/漏极区域中，且因此由于较低的电洞迁移率而在效能上有所缺乏。
因此，存在需要用于通过整合硅锗至HKMG制程中以使具有高效能的SLP装置能够制造的方法及所产生的装置。
发明内容
本发明揭露的实施例为一种用于形成具有嵌入式硅锗(eSiGe)在PMOS中的HKMG CMOS装置的晚原位掺杂(in-situ-doped late)硅锗(在制程流程中所有的植入之后)制程流程。
本发明揭露的另一实施例为一种由晚硅锗制程所形成的具有嵌入式硅锗在PMOS中的HKMG CMOS装置。
本发明揭露的额外方面及其它特征将在以下的内容中加以描述，其中某些部分对于本领域技术人员而言，在检视过以下的内容后，会认为是显而易见的，或者也可从本发明的实作中加以学习。本发明的优点，可通过附随的权利要求书中所特别指出的，来加以实现及获得。
根据本发明揭露的方面，一些技术效果可通过一种方法部分达成，该方法包含：形成第一及第二高介电常数金属栅极(HKMG)栅极堆栈于基板上；形成氮化物衬垫及氧化物间隙壁于各该第一及第二HKMG栅极堆栈的各侧；于各该第一及第二HKMG栅极堆栈的各侧执行晕/延伸植入；形成氧化物衬垫及氮化物间隙壁于各该第一及第二HKMG栅极堆栈的该氧化物间隙壁上；形成深源极/漏极区域在该第二HKMG栅极堆栈的相反侧上；形成氧化物硬掩模于该第二高介电金属栅极栅极堆栈之上；形成嵌入式硅锗于该第一HKMG栅极堆栈的相反侧上；以及移除该氧化物硬掩模。
本发明揭露的方面包括：形成氮化硅的该氮化物衬垫；形成二氧化硅的该氧化物间隙壁；以及形成氮化硅的该氮化物间隙壁。本发明揭露的另一方面包括该第一及第二HKMG栅极堆栈各包含高介电常数介电质、功函数金属、多晶硅、以及氮化硅上盖。本发明揭露的其它方面包括于形成该嵌入式硅锗前进行预清洗；以及最佳化该预清洗以保护该二氧化硅间隙壁。本发明揭露的又一方面包括形成该嵌入式硅锗于该第一HKMG栅极堆栈的各侧上，通过：经由以氢氧化四甲基铵(tetramethylammonium hydroxide,TMAH)的湿式蚀刻形成孔穴；以及于该孔穴中磊晶成长硅锗。本发明揭露的额外方面包括例如以梯度掺杂分布原位植入硼掺质至该嵌入式硅锗中。本发明揭露的再一方面包括退火以在形成该氧化物硬掩模之后活化植入的掺质。本发明揭露的另一方面包括经由以稀释氢氟酸(diluted hydrofluoric acid,dHF)的湿式蚀刻移除该氧化物硬掩模。本发明揭露的其它方面包括于移除该氧化物硬掩模之后移除该氮化硅上盖及该氮化物间隙壁。本发明揭露的额外方面包括由干式或湿式蚀刻制程移除该氮化硅上盖及该氮化物间隙壁。本发明揭露的又一方面包括形成硅化物于该源极/漏极区域、该嵌入式硅锗、及该第一及第二HKMG栅极堆栈上。本发明揭露的另一方面包括形成信道硅锗区域在该第一HKMG栅极堆栈之下。
本发明揭露的再一方面为一种装置，包括：第一及第二高介电常数金属栅极（HKMG）栅极堆栈，各自包含高介电常数介电质、功函数金属、及多晶硅；氮化物衬垫及第一与第二氧化物间隙壁，依次地形成于各该第一及第二高介电金属栅极栅极堆栈的各侧；晕及延伸植入区域，位于各该第一及第二HKMG栅极堆栈的相反侧，其形成于该第二氧化物间隙壁之前；深源极/漏极区域，位于该第二HKMG栅极堆栈的相反侧上，其形成于该第二氧化物间隙壁之后；以及嵌入式硅锗，位于该第一HKMG栅极堆栈的相反侧上，其利用该第二栅极堆栈之上的氧化物硬掩模形成于该深源极/漏极区域之后。
方面包括第一及第二高介电常数金属栅极（HKMG）栅极堆栈，各自包含高介电常数介电质、功函数金属、及多晶硅；氮化物衬垫及第一与第二氧化物间隙壁，依次地形成于各该第一及第二HKMG栅极堆栈的各侧；晕及延伸植入区域，位于各该第一及第二HKMG栅极堆栈的相反侧，其形成于该第二氧化物间隙壁之前；深源极/漏极区域，位于该第二栅极HKMG栅极堆栈的相反侧上，其形成于该第二氧化物间隙壁之后；以及嵌入式硅锗，位于该第一HKMG栅极堆栈的相反侧上，其利用该第二栅极堆栈之上的氧化物硬掩模形成于该深源极/漏极区域之后。其它方面包括氮化物间隙壁是形成于该第二氧化物间隙壁之上，且位于该第二栅极HKMG栅极堆栈的相反侧上的该深源极/漏极区域是以该氮化物间隙壁作为软掩模而形成。另一方面包括该氮化物衬垫及该氮化物间隙壁包含氮化硅(silicon nitride,SiN)且该氧化物间隙壁包含二氧化硅(silicon dioxide,SiO2)。额外方面包括该嵌入式硅锗是以具有梯度掺杂分布的硼原位植入。其它方面包括硅化物，其位于该嵌入式硅锗、该深源极/漏极区域、及该第一及第二HKMG栅极堆栈上。再一方面包括信道硅锗区域，其位于该第一HKMG栅极堆栈之下。
本发明揭露的另一方面为一种方法，包括：形成PMOS及NMOS高介电常数金属栅极(HKMG)栅极堆栈于基板上；形成L型氮化硅衬垫及二氧化硅间隙壁于各该PMOS及NMOS高介电金属栅极栅极堆栈的各侧；于各该PMOS及NMOS的HKMG栅极堆栈的各侧执行晕/延伸植入；形成L型二氧化硅衬垫及氮化硅间隙壁于各该PMOS及NMOS的HKMG栅极堆栈的该二氧化硅间隙壁上；植入深源极/漏极区域在该NMOS的HKMG栅极堆栈的相反侧；形成二氧化硅硬掩模于该NMOS的HKMG栅极堆栈之上；形成嵌入式硅锗于该PMOS的HKMG栅极堆栈的相反侧上，通过：经由以氢氧化四甲基铵(TMAH)的湿式蚀刻在该PMOS的HKMG栅极堆栈的各侧形成孔穴；于该孔穴中磊晶成长硅锗；及于磊晶成长的同时，以梯度掺杂分布原位植入硼掺质至该嵌入式硅锗中；经由稀释氢氟酸湿式蚀刻该氧化物硬掩模；干式或湿式蚀刻该氮化硅上盖及该氮化硅间隙壁；以及形成硅化物于该源极/漏极区域、该嵌入式硅锗、及该PMOS及NMOS的HKMG栅极堆栈上。
对于本领域技术人员而言，从以下的详细描述中，可明显地认识到本案的额外认识及技术效果，其中，本发明的实施例仅通过例示用以实行本发明的最佳模式来加以描述。将会了解到，本发明可有其它不同的实施例，并且，可针对各种显而易知的方面，修改部分的细节，而不致背离本发明。因此，附图及描述其本质仅视为例示之用，而非用以限制本发明。
附图说明
本发明是通过范例中的随附附图来加以例示，而非限制之用，在该附图中，相同的组件符号视为类似的组件，其中：
图1A至图1I是根据本发明揭露的实施例，示意地例示用于形成具有PMOS嵌入式硅锗源极/漏极区域的半导体装置的制程。
符号说明
具体实施方式
在以下的描述中，为了解释的目的，列出各种特定的细节，以提供示范实施例的全盘了解。然而，很明显地，示范实施例不需要这些特定细节、或以均等配置，也可加以实行。在其它例子中，众所周知的结构及装置是以方块图的表现形式加以显示，以避免不必要地模糊示范实施例。此外，除非特别指明，否则应了解到，说明书及附图中所使用的所有数字表示的数量、比例、以及成分及反应条件等的数值特性。在所有例子中，均可通过“大约”这个术语来加以修饰。
本发明面对并解决目前栅极优先（gate first）HKMG的包覆不足的问题，并伴随着在PMOS装置中形成嵌入式硅锗源极/漏极区域。依据本发明揭露的实施例，一种晚硅锗方法是合并至HKMG制程中，在较高的PFET效能下增加良率。详言之，在各种植入过程期间，形成氮化物衬垫、氧化物间隙壁、氧化物衬垫、及氮化物间隙壁以包覆该栅极，在全部植入完成后，形成氧化物硬掩模于该NMOS栅极堆栈之上，并在形成于PMOS的相反侧的孔穴中磊晶成长嵌入式硅锗。
依据本发明的实施例的方法，包括形成第一及第二高介电常数金属栅极(HKMG)栅极堆栈于基板上、形成氮化物衬垫及氧化物间隙壁于各该第一及第二HKMG栅极堆栈的各侧上、于各该第一及第二HKMG栅极堆栈的各侧执行晕/延伸植入、形成氧化物衬垫及氮化物间隙壁于各该第一及第二HKMG栅极堆栈的该氧化物间隙壁上、形成深源极/漏极区域在该第二HKMG栅极堆栈的相反侧上、形成氧化物硬掩模于该第二HKMG栅极堆栈之上、形成嵌入式硅锗于该第一HKMG栅极堆栈的相反侧上、以及移除该氧化物硬掩模。
对于本领域技术人员而言，从以下的详细描述中，可明显地认识到本案的额外方面、特征及技术效果，其中，本发明的实施例仅通过例示用以实行本发明的最佳模式来加以描述。本发明可有其它不同的实施例，并且，可针对各种显而易知的方面，修改部分的细节。因此，附图及描述其本质仅视为例示之用，而非用以限制本发明。
图1A至图1I是根据本发明的示范实施例，例示将嵌入式硅锗整合至PMOS的制程流程。参照图1A，栅极优先HKMG堆栈101，包括高介电常数介电质103(例如二氧化铪(hafnium oxide,HfO2)或氮氧硅铪(hafnium silicon oxynitride,HfSiON))、功函数金属105(例如氮化钛(titanium nitride,TiN))、多晶硅107(poly silicon,poly-Si)、以及氮化硅上盖109是显示在基板111上以用于NMOS 113及PMOS 115各者。PMOS115还包括在基板111中，位于该高介电常数介电质103之下的5至10nm厚度的信道硅锗117(channel SiGe,cSiGe)以调整由于该栅极优先方法的临限电压(threshold voltage)。使用栅极优先方法还需要包覆层围绕该栅极堆栈以于之后例如清洗及蚀刻的制程步骤保护HKMG。为此目的，多层沉积(multilayer deposition,MLD)氮化硅(Si3N4)层119是毯覆式沉积(blanket deposition)在整个基板上达3nm至6nm的厚度。低压氧基硅烷(low pressure tetra ethyl ortho silicate,LPTEOS)/高温氧化物(hightemperature oxide,HTO)氧化层121是以5nm至10nm的厚度形成于Si3N4 MLD层119上，用以在各栅极堆栈的各侧上形成间隙壁零层(spacer zero)。
如图1B所示，非等向性蚀刻氧化层121以形成SiO2间隙壁(SP0)123。MLD Si3N4层119也从该打开的作用区域被蚀刻。该间隙壁是在形成晕区域129及延伸区域131时，使用来补偿(offset)及调整晕/延伸植入(125/127)，如图1C所示，对于该NMOS及PMOS二者，是对各者使用植入掩模(为了例示方便而未图标)。晕区域是通过在中等能量(例如，35keV至50keV)下，植入低到中剂量(例如，3.5E13至7E13)的砷(As)、硼(B)、或氟化硼(BF2)而形成。延伸区域是通过在低能量(例如，0.7keV对硼或4keV对砷)下，植入高剂量(例如，1.1E15)的砷(As)、硼(B)、或氟化硼(BF2)而形成。
参照图1D，例如为氮化硅的氮化物间隙壁133是形成于该NMOS及该PMOS二者上，具有氧化物衬垫135在下方以作为蚀刻停止层。在NMOS中，氮化物间隙壁133是用作为软掩模用于深源极/漏极植入，以形成深源极/漏极区域137。举例而言，可在高剂量(例如，2E15)及高能量(例如，6keV对硼或20keV对砷)下植入砷(As)、硼(B)、或氟化硼(BF2)。
随后，如图1E所示，氧化层139是以10nm至25nm的厚度沉积在NMOS 113上。氧化层139可被形成在NMOS 113及PMOS 115上，然后由PMOS 115上清除。该氧化层用作为NMOS 113上的硬掩模。接着执行快速热退火(rapid thermal anneal,RTA)以活化该掺质并退火处理所有的植入伤害。RTA透过槽密实化(trough densification)同时硬化了硬掩模139。或者，可在n型深源极/漏极植入之后，以及因此在该氧化硬质掩模139形成前，直接执行RTA。
如图1F所示，在该基板中该PMOS 115栅极堆栈的各侧上，Σ形状(sigma shaped)孔穴141是使用氢氧化四甲基铵(tetramethylammoniumhydroxide,TMAH)所形成。虽然可能为其它形状，该Σ形状孔穴141允许非常接近的近似性(proximity)以及因此该晶体管信道区域内的最大应力。在进一步处理之前，执行预清洗，例如以________，其为最佳化的(也就是，并不非常侵略性的)以保护该氧化物硬掩模139。
在预清洗之后，如图1G所示，硅锗143是在该孔穴141中成长，举例而言通过低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)制程作为用于该PMOS装置的深源极/漏极区域的原位梯度硼掺杂沉积。原位掺杂(in-situ doping)是被使用以允许高且均匀的掺杂水准(doping level)，其因此降低寄生电阻与接触电阻，借此允许较高的驱动电流。此外，硼允许锗的含量增加，例如大于35%，相对于未掺杂硅锗的25%，其引发较高的应力并进一步改善电洞迁移率提升。通过在磊晶过程中掺杂PMOS的源极/漏极区域，消除了专用的源极/漏极植入，借此节省用于掩模及植入的制程成本、减少周期时间(cycle time)、及降低来自植入伤害的应力松弛。再者，硼掺质是通过磊晶而活化，从而消除额外退火的需求。稍微的过度成长(overgrowth)是帮助形成更为坚固的包覆以及用于其会攻击主动开放硅区域(active open siliconarea)之后续清洗的裕度(margin)。过度成长还提供额外的裕度以用于形成坚固的硅化物，例如硅化镍(nickel silicide,NiSi)，并具有较佳的接触电阻。
如图1H所示，另一清洗步骤，例如使用湿式蚀刻，举例而言以稀释氢氟酸(diluted hydrofluoric acid,dHF)，将由NMOS 113上移除该氧化物硬掩模139。参照图1I，该湿式蚀刻是接着干式蚀刻或一额外的湿式蚀刻，举例而言，使用热磷酸(hot phosphoric acid,H3PO4)，以移除该氮化物上盖109及氮化物间隙壁133。如图所示，此将保留曝露出来的L型氧化物间隙壁135。
金属，例如镍(Ni)、镍钛(NiTi)或钴(Co)，可随后沉积在整个装置上并退火处理以形成在源极/漏极区域137及多晶硅107上的硅化物145(即，硅化镍、硅化镍钛、或硅化钴)以及在硅锗143上的硅化物145(即，硅锗化镍(NiSiGe)、硅锗化镍钛(NiTiSiGe)、或硅锗化钴(CoSiGe))，以形成低电阻区域。与硅锗结合的硅化物降低了片电阻及接触电阻，从而改善了效能行为。制程流程随后继续传统的中段(middle-of-line,MOL)制程以及接触形成。或者，在硅化的时间，若L型氧化物间隙壁135过薄，例如小于10nm，举例而言因为在沉积镍之前的预清洗过程中薄化，则必须在形成硅化物之前形成额外的氮化物间隙壁(氮化硅保护间隙壁，为了例示方便而未图标)，以增加远离该信道区域的硅化物距离。之后制程可继续所揭露的硅化制程、中段制程以及接触形成。
本发明揭露的实施例可达成多种技术效果，包含增进栅极优先HKMG的包覆，从而改善良率、降低接触电阻、降低在PMOS装置中的串联电阻、增加在PMOS装置中的载子迁移率及驱动电流、增进效能、及降低制造成本。依据本发明揭露的实施例所形成的装置可在各种产业应用中享有实用性，例如，微处理器、智能型手机、行动电话、蜂巢式手机，机上盒、DVD录像机及播放机、汽车导航、打印机及外围设备、网络及电信装备、游戏系统、以及数字相机。因此，本发明在任何高度整合的半导体装置的各种类型，特别是32nm及28nm技术以上的技术，享有产业利用性。
在先前的段落中，本发明是参考本发明的特定示范实施例来加以描述。然而，很明显地，可对本发明作出各种修正及改变，而不致于背离本发明在权利要求书中所呈现的最广精神及范围。因此，该说明书及附图将被视为例示、而非限制之用。应了解到，本发明可使用不同的其它组合及实施例，并因此可在本文所表示的发明概念的范围内，作任何的改变或修正。

Claims (14)

1.一种形成半导体装置的方法，包括：
形成第一及第二高介电常数金属栅极(HKMG)的栅极堆栈于基板上；
形成氮化物衬垫及氧化物间隙壁于各该第一及第二高介电常数金属栅极的栅极堆栈的各侧上，以使该氮化物衬垫直接接触该第一及第二高介电常数金属栅极的栅极堆栈；
于各该第一及第二高介电常数金属栅极的栅极堆栈的各侧执行晕/延伸植入；
形成氧化物衬垫及氮化物间隙壁于各该第一及第二高介电常数金属栅极的栅极堆栈的该氧化物间隙壁上；
形成深源极/漏极区域在该第二高介电常数金属栅极的栅极堆栈的相反侧上；
形成氧化物硬掩模于该第二高介电常数金属栅极的栅极堆栈之上；
形成嵌入式硅锗于该第一高介电常数金属栅极的栅极堆栈的相反侧上；以及
移除该氧化物硬掩模。
2.根据权利要求1所述的方法，包括：
形成氮化硅的该氮化物衬垫；
形成二氧化硅的该氧化物间隙壁；以及
形成氮化硅的该氮化物间隙壁。
3.根据权利要求1所述的方法，其中，该第一及第二高介电常数金属栅极的栅极堆栈各还包含高介电常数介电质、功函数金属、多晶硅、以及氮化硅上盖。
4.根据权利要求2所述的方法，还包括：
于形成该嵌入式硅锗前进行预清洗；以及
最佳化该预清洗，以保护该二氧化硅的该氧化物间隙壁。
5.根据权利要求1所述的方法，包括：
形成该嵌入式硅锗于该第一高介电常数金属栅极的栅极堆栈的各侧上，其通过：
经由以氢氧化四甲基铵(TMAH)的湿式蚀刻形成孔穴；以及
于该孔穴中磊晶成长硅锗。
6.根据权利要求5所述的方法，还包括原位植入硼掺质至该嵌入式硅锗中。
7.根据权利要求6所述的方法，包括以梯度掺杂分布植入硼。
8.根据权利要求1所述的方法，还包括退火，以在形成该氧化物硬掩模之后活化植入的掺质。
9.根据权利要求1所述的方法，包括经由以稀释氢氟酸的湿式蚀刻移除氧化物硬掩模。
10.根据权利要求9所述的方法，还包括于移除该氧化物硬掩模之后移除该氮化硅上盖及该氮化物间隙壁。
11.根据权利要求10所述的方法，包括经由干式或湿式蚀刻制程移除该氮化硅上盖及该氮化物间隙壁。
12.根据权利要求11所述的方法，还包括形成硅化物于该源极/漏极区域、该嵌入式硅锗、及该第一及第二高介电常数金属栅极的栅极堆栈上。
13.根据权利要求1所述的方法，还包括形成信道硅锗区域在该第一高介电常数金属栅极的栅极堆栈之下。
14.一种形成半导体装置的方法，包括：
形成PMOS及NMOS高介电常数金属栅极(HKMG)栅极堆栈于基板上；
形成L型氮化硅衬垫及二氧化硅间隙壁于各该PMOS及NMOS的高介电常数金属栅极的栅极堆栈的各侧上，以使该氮化矽衬垫直接接触该PMOS及NMOS的高介电常数金属栅极的栅极堆栈；
于各该PMOS及NMOS的高介电常数金属栅极的栅极堆栈的各侧执行晕/延伸植入；
形成L型二氧化硅衬垫及氮化硅间隙壁于各该PMOS及NMOS的高介电常数金属栅极的栅极堆栈的该二氧化硅间隙壁上；
植入深源极/漏极区域在该NMOS的高介电常数金属栅极的栅极堆栈的相反侧；
形成二氧化硅硬掩模于该NMOS的高介电常数金属栅极的栅极堆栈之上；
形成嵌入式硅锗于该PMOS的高介电常数金属栅极的栅极堆栈的相反侧上，其通过：
经由以氢氧化四甲基铵(TMAH)的湿式蚀刻在该PMOS的高介电常数金属栅极的栅极堆栈的各侧形成孔穴；
于该孔穴中磊晶成长硅锗；及
于磊晶成长的同时，以梯度掺杂分布原位植入硼掺质至该嵌入式硅锗中；
经由稀释氢氟酸湿式蚀刻该二氧化硅硬掩模；
干式或湿式蚀刻该氮化硅上盖及该氮化硅间隙壁；以及
形成硅化物于该源极/漏极区域、该嵌入式硅锗、及该PMOS及NMOS的高介电常数金属栅极的栅极堆栈上。
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