TWI485802B - 子欄位增強的全域對準 - Google Patents

子欄位增強的全域對準 Download PDF

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TWI485802B
TWI485802B TW099123672A TW99123672A TWI485802B TW I485802 B TWI485802 B TW I485802B TW 099123672 A TW099123672 A TW 099123672A TW 99123672 A TW99123672 A TW 99123672A TW I485802 B TWI485802 B TW I485802B
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wafer
wafers
reconstituted
overlap
subfields
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TW099123672A
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TW201142978A (en
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安卓Ｍ 哈瑞盧克
愛密麗Ｍ 楚
曼尼許 瑞真
華倫 弗拉克
戴特拉夫 福克司
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精微超科技公司
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Description

子欄位增強的全域對準
本揭示內容大體上係關於微影術及半導體製造，且特定言之係關於在具有一重疊需要之一微影術程序中執行重構晶圓之對準的方法。
本申請案主張於2009年8月12日申請之標題為「Sub-field enhanced global alignment for lithography in fan-out wafer-level packaging」的美國臨時申請案第61/274,012號之35 U.S.C. § 119(e)下的優先權之權益，該申請案以引用的方式併入本文中。
尖端的消費電子產品需要創新且具成本效益的封裝解決方案。雖然前端矽技術已藉由裝置按比例調整而遵循摩爾定律(Moore's law)，但是後端的基礎結構已在類似的前進中落後。此已產生一互連間隙，藉此在矽方面達成之信號速度明顯高於在印刷電路板達成之速度。為此，已發展後端處理(諸如扇出晶圓級封裝技術)中之創新的前進，而給予穩健的封裝解決方案以符合對於尖端裝置(諸如無線晶片)之效能及可靠性需要。
扇出晶圓級封裝技術解決與習知晶圓級封裝技術關聯之墊限制且具有微型化及可能的低成本封裝的優點。其亦致能具有超出原始前端晶片尺寸之容量的輸入/輸出(I/O)計數的高效能凸塊互連。各晶片之凸塊陣列面積藉由按一大於原始晶圓之重複節距以經測試之「已知良好」的晶片填入一複合晶圓而增加。該重構晶圓較佳具有一標準矽晶圓之尺寸及形狀，藉此允許將現存的晶圓處理設備用於後續的處置及處理。為了與平面處理步驟之相容性，晶片表面需要與晶圓模製化合物共面。亦需要使各晶片之X、Y及θ定位精確地在網格內以維持重合效能同時每次曝光圖案化多重晶片。
一重構晶圓內之晶片定位控制係影響下游處理需要之關鍵因素的一因素。雖然已經使用晶片取放設備完成可觀的改良，但是難以在模壓程序期間控制矽晶片之偏移。此在後續的光微影術程序步驟期間產生明顯的對準挑戰。
本揭示內容大體上係關於微影術及半導體製造，且特定言之係關於執行用於微影術程序(諸如晶圓級封裝)之子欄位增強的全域對準(SEGA)之方法。本文所揭示之該等SEGA方法提供在執行微影術程序(如扇出晶圓級封裝)之程序中適應布置在一重構晶圓上之若干晶片的位置的放置誤差(特定言之隨機放置誤差)之能力。
本揭示內容之一態樣係一種在具有一重疊需要之一微影術程序中執行對準的方法。該方法包含提供至少一重構晶圓，該重構晶圓包含由一載體支撐且配置在不同位置的複數個晶片，其中該等晶片位置妨礙執行在該重疊需要內之整個晶圓上晶片之一單一增強的全域對準。該方法亦包含量測該至少一重構晶圓上之該等晶片位置。該方法亦包含基於該量測之晶片位置識別該重構晶圓之兩個或兩個以上子欄位，其中可分別執行增強的全域對準以在該重疊需要內。該方法進一步包含執行各自的兩個或兩個以上子欄位內之分別增強的全域對準。
本揭示內容之另一態樣係一種在一微影術程序中對準放置在一重構晶圓上之若干晶片的方法。該方法包含建立該重構晶圓上之兩個或兩個以上子欄位，其中在晶片放置中之一給定的系統誤差及隨機誤差係於重疊需要內。該方法亦包含執行各自的兩個或兩個以上子欄位內之一或多個晶片之各自的兩次或兩次以上增強的全域對準。
本揭示內容之另一態樣係一種在具有一重疊需要之一微影術程序中執行重構晶圓之對準的方法。該方法包含形成一第一組多重重構晶圓，各重構晶圓具有一載體，該載體具有藉此可操作地支撐於不同位置的若干晶片，使得不可對於該第一組中之一給定重構晶圓上的該等晶片之全部執行一單一增強的全域對準。該方法亦包含量測該多重晶圓上之晶片位置。該方法亦包含基於該等量測之晶片位置而判定子欄位，於該等子欄位上可執行在該重疊需要內之增強的全域對準。
在下列的詳細描述中提出本揭示內容之額外的特徵及優點，且熟習此項技術者將自該描述而易於得知部分特徵及優點，或藉由實踐如本文所述之該揭示內容(包含下列的詳細描述、申請專利範圍以及隨附圖式)而認知部分特徵及優點。
應瞭解的是，以上一般描述及下列詳細描述兩者呈現本揭示內容之若干實施例，且意欲提供用於瞭解如所請求之本揭示內容的本質及特性的一概述或框架。包含該等隨附圖式以提供對本揭示內容之一進一步瞭解，且將該等隨附圖式併入而且構成本說明書之一部分。該等圖式繪示本揭示內容之各種實施例，且連同該描述用於解釋本揭示內容的原理及操作。
圖式中所描繪之各種元件係純粹代表性，且無需按比例繪製。圖式之某些區段可能誇大，而其他區段可能最小化。該圖式意欲繪示可為此項技術之一般技術者瞭解並合適地實施的本揭示內容之一實例實施例。
現在詳細地對本揭示內容之當前較佳的實施例進行參考，隨附圖式中繪示其等之實例。盡可能地，相同的參考數字及符號遍及該等圖式而使用以指代相同或相似的部件。
本揭示內容大體上係關於微影術及半導體製造，且特定言之係關於具有一重疊需要之SEGA方法微影術程序，諸如晶圓級封裝，且特定言之扇出晶圓級封裝。本文所揭示之該等SEGA方法提供適應布置在一重構晶圓上之晶片之位置的隨機放置誤差以執行落於該重疊需要內之對準的能力。
晶圓級封裝
微影術通常在半導體工業及微電子機械系統(MEMS)工業中用於製作裝置。實際上，微影術被視為在尋求生產越來越小的電晶體中用於推進摩爾定律之技術驅策者。最近，微影術已開始在半導體製作之「後端」或更特定言之在封裝領域中發揮一更加重要的作用。從前，封裝係由導線接合所支配。近期，非關鍵層微影術(亦即，低解析度微影術，通常1微米至50微米)被用於圖案化重構基板上之若干矽裝置之間的互連。
基本半導體積體電路之製造通常在大(150 mm至300 mm的直徑或均等物)的矽晶圓上完成。因為處理成本係非常昂貴，故儘一切努力使一單一晶圓上之積體電路的數目最大化。
圖1係一典型的積體裝置佈局之一晶圓20上之晶片(晶粒)10的一實例先前技術配置的一平面視圖。晶片10係於標記線16之內，且儘可能靠近地予以放置以使良率最大化且使製作成本最小化。因此，在該等積體電路(晶片)10之間存在非常小的空間。該等晶片10之間的面積大體上為自該晶圓單一化該等晶片所需之最小面積。因此，線16經常被稱為「劃線」，且通常為近似50微米至100微米寬。
隨著現代積體裝置變得更加複雜且具有更多性能，該等裝置自身需要更多的輸入及輸出連接。因此，封裝晶片成為激烈活動之一領域。一基本問題在於封裝的尺寸經常比晶片自身的尺寸大很多。
圖2A及圖2B係一封裝基板(「封裝」)30(具有在其上形成之大量接觸墊40)上之一晶片10之各自的側視圖及俯視圖。圖2A及圖2B中所示之總成在本文中被稱為一「封裝晶片」32。一現代封裝晶片32可具有數百個接觸墊40。該等接觸墊40係足夠大(通常尺寸為50微米至100微米，但是可小至1微米)以產生至其他晶片、裝置或電路板的巨觀接觸(例如，使用導線接合或穿透矽導通體)。另外，在個別接觸墊40與該晶片上之相關區域之間添加路徑選擇線50(展示為圖2B中之虛線)。此等路徑選擇線50經常使用微影術製作。應注意，電連接至晶片10之接觸件40在該晶片外側延伸。該等接觸件40自該晶片「扇出」，且因此，此程序已被稱為「扇出封裝」。
由於封裝30之相對大尺寸，故不可能將該封裝程序整合至原始的矽晶圓20上。因此，封裝中的一新趨勢係建立一「重構晶圓」。圖3係一實例重構晶圓100之一平面視圖，其中該等晶片10自該原始晶圓20切割，經封裝以形成封裝晶片32，且將該等封裝晶片放置到一載體102上。晶片10之間的分離係大於與該原始晶圓20之劃線16關聯的分離。載體102不必由矽組成，且可(例如)由封裝材料製成，且大體上亦為一典型矽晶圓之尺寸，使得習知的矽處理設備可用於額外處理。藉由將該等晶片10進一步分開放置在較不昂貴的重構晶圓100上，現在存在足夠的空間來產生隨後封裝所需的全部接觸件。
圖4A至圖4F中繪示與扇出封裝程序關聯之基本的程序流程。在圖4A中所示之第一步驟中，自一晶圓20單一化個別的晶片10，且使用一習知的取放機器將其等裝配到一臨時載體104上。為了繪示起見僅展示臨時載體104的一區段及藉此所支撐的兩個晶片。晶片10具有晶片接觸件12。一種選項係測試該等個別的晶片，且僅使用已知良好的晶片10形成該重構晶圓。
參考圖4B，然後將該等晶片10嵌入允許乾燥及硬化之一材料110中。在硬化之後，材料110作為一保護層且成為該重構晶圓100之載體102。
參考圖4C，移除該臨時載體104，留下由材料110(亦即，載體102)支撐(例如，嵌入材料110中)的晶片10。
參考圖4D，然後將具有嵌入其中之晶片10的該硬化材料110倒置，使得可執行隨後的處理(諸如微影術、電鍍或蝕刻)。此時，微影術用於在該硬化材料110上界定接觸墊40(如圖4E中所示)，且經由晶片接觸件12產生該等接觸墊與該晶片內之相關功能區塊之間的電連接50(如圖4F中所示)。其結果為具有如同圖3之理想化版本中所示之一扇出組態的一重構晶圓100，圖4F中僅展示該重構晶圓之一部分。
在扇出晶圓級封裝之一先進形式中，可將個別的接觸墊40製成作為「穿透導通體」40T，其中其等自該封裝之頂部延伸至底部。在此實施例中，可如圖5A及圖5B中所示將若干晶片堆疊。
重構晶圓之對準
對準重構晶圓100(作為具有一重疊需要之一微影術程序的一部分)之困難在於該重構晶圓100內之該等個別晶片10的位置經常不良控制。晶片10之放置可受該取放機器之精度及可重複性以及封裝材料之硬化程序(其將趨於以一不均勻方式跨區域收縮)影響。因此，晶片10未被規則隔開。在該封裝材料110硬化之後，嵌入其中之該等個別晶片10大體上具有近似5微米至25微米的隨機位置誤差。因此，用於後端處理(例如，界定接觸墊、穿透導通體及該等接觸墊與功能區塊之間的連接等)中之習知的微影術設備難以符合對於與晶圓級封裝關聯之後續處理步驟(例如，濺射、光微影術、電鍍、鋼球降落程序等)的該重疊需要。
正常的微影術工具用於在矽晶圓20上曝光圖案，其中該等晶片10位於一非常精確的陣列中(諸如圖1中所示)。該等個別晶片10之位置經常精確至數奈米。微影術工具通常識別且定位少量全域對準標記(通常3至5個標記)，且自此等標記並使用透過對準方法所提供之其他資訊，該工具計算笛卡爾(Cartesian)座標系統及該晶圓20上之各個別晶片10的位置。此係EGA(增強的全域對準)技術之基礎。此方法可使線性校正適應該座標系統(亦即，以x及y之線性放大項，及兩個座標系統之間的一旋轉角度θ)。然而，一問題在於正常的微影術工具不具有適應該等晶片之位置的大隨機或系統位置誤差或不可由一線性校正項模型化之誤差之性能。因此，其等不可在一單一操作中於全部晶片上實施EGA，同時滿足該微影術程序之重疊需要。
在重構晶圓100之材料處置期間可發生額外的問題。該重構晶圓100不如一矽晶圓20般平坦及規則。實際上，該重構晶圓100通常為不平坦達數百微米。因此，習知的材料處置技術及工具(例如，機器人及末端效應器)及與習知微影術工具關聯之習知的預對準器及傳統的平台不會良好地處置及處理此等重構晶圓，藉此在後端處理期間添增晶圓放置誤差。
另一問題在於晶片10並非精確地以一規則陣列放置。晶片10之位置具有歸因於該取放工具的有限精度且歸因於隨著該封裝材料110硬化以形成載體102之該封裝材料110的收縮的一隨機誤差成分。該封裝材料收縮可能與材料有關且與位置有關。因此，在載體102中心的晶片10可具有比接近該載體之邊緣的晶片更小的收縮引發的偏移。在一未知的晶片位置之情況下，難以在重構晶圓100上執行微影術且仍然符合該重疊需要。
逐一區位對準
逐一區位對準係一種已在晶片位置(於矽晶圓上)較不精確時之微影術的早期使用的方法。因此，值得考慮將逐一區位對準用於圖案化重構晶圓。一般而言，對於具有隨機誤差之任意晶片位置，逐一區位對準提供將曝光工具之標線精確地對準至各晶片的一方法。隨著晶片位置變得更加精確，增強的全域對準(EGA)因為其更加快速而成為選擇的方法。當逐一區位對準量測晶圓上之各晶片(晶片)的位置及定向時，EGA量測該晶圓上之少量對準標記的位置。
兩種方法所需之量測次數的差異可為明顯，例如，在一300 mm晶圓上逐一區位量測數百個晶片，而EGA通常量測3至5個對準區位。
因為各對準量測佔用明顯的一瞬間，所以數百次量測之減少大幅改良整體的生產產量。然而，該EGA對準方法僅在若該等晶片之位置係精確控制且可預測(其大體上不為重構晶圓100之情況)時運作。另一方面，雖然在重構晶圓100上使用逐一區位對準可提供對準及重疊之足夠精度，但是其導致對於一製造環境而言一不可接受的產量減少。
子欄位增強的全域對準(SEGA)方法
本揭示內容之一態樣係針對在晶片位置的誤差不允許EGA在全部晶片上以一單一步驟執行之情況下在一或多個重構晶圓上執行子欄位增強的全域對準(SEGA)以作為具有一重疊需要之一微影術程序的一部分的方法。該SEGA方法以一逐一區位對準程序之更好的對準性能最佳化一EGA程序之產量益處，以達成在該重疊需要內之全部晶片上的對準。可將該SEGA方法視為明智而審慎地將逐一區位對準與EGA方法之益處組合之一混合的對準方法。
一給定的微影術程序之重疊需要係由裝置(晶片)需要指定。較小的線寬趨於需要較緊的重疊。通常將該重疊需要判定為最小線寬之一分數(通常近似該線寬之)。
重構晶圓100上之晶片位置誤差通常會具有一隨機成分及一系統成分兩者。用於將該等晶片放置在該重構晶圓上之取放工具自身會具有其自身之隨機誤差及系統誤差，且構成載體102之封裝材料110的收縮亦會引起隨機誤差及系統誤差。載體收縮名義上會具有一系統表徵，其表示固化程序、材料之厚度、材料屬性及嵌入該材料中之晶片的尺寸(及數目)。該隨機成分可由該固化程序或該材料屬性及厚度中的變動組成。
本文所述之該SEGA方法的一態樣涉及利用在一給定重構晶圓100上存在至少一子欄位之事實，其中一人士可在該子欄位內使用一EGA類型方法時對於一給定重疊需要達成晶片放置中的一給定系統誤差及隨機誤差所需的重疊。在一實例SEGA方法中，識別兩個或兩個以上子欄位，其中可在各子欄位內執行EGA以在被實施之特定微影術程序(諸如用於後端封裝中的非關鍵層微影術)的重疊需要內。此處，該等EGA方法無需涉及量測對準標記本身，而是可替代地依賴於如下文所述之晶片位置的量測。
例如，該晶片放置的系統誤差及隨機誤差可為過大，以至於不能對於一特定重疊需要在一整個(300 mm)重構晶圓100上使用一EGA類型方法，但是一子欄位S(諸如該重構晶圓之)內之系統誤差及隨機誤差可為足夠小，使得一EGA類型方法會在該子欄位內運作。在一實例中，該子欄位S之尺寸係藉由量測來自在處理多重晶圓(例如，一整批生產晶圓)之前的程序之一或多個晶圓(例如，來自以相同或類似方式處理之一共同批晶圓的多重晶圓)而判定。因此，一第一組重構晶圓可用於判定子欄位S之尺寸及位置，同時可將該SEGA方法應用於此第一組，應用於來自該相同(共同)批之一第二組，或應用於兩組。這是因為來自一共同批或群組之重構晶圓大體上會具有相同或類似的晶片配置組態(亦即，大體上遭受相同的放置誤差)，且因此具有相同的子欄位組態。
圖6繪示可存在於一重構晶圓100上之一類型系統誤差，藉此晶片10之中心行的位置係相對於側行而位移。如圖7中所繪示，無全晶圓、習知的EGA演算法可充分補償此類型誤差。圖7中展示一單一的x-y座標系統，且可看見中心晶片10並未與x-y軸同樣地對準，因為放置誤差在該晶圓上各處並非為線性。
然而，現在參考圖8，藉由將晶圓分割為子欄位S(諸如，具有如所示之子欄位S1及S2的兩部分，或在其他實例中為具有子欄位S1至S3的三部分，或具有子欄位S1至S4的四部分等)，可能獨立地在不同的子欄位上執行一EGA類型對準。在圖8中，一全域、線性的EGA x-y座標系統(諸如圖7中所示)將對於正確地定位全部晶片10係不起作用的。然而，在將該重構晶圓100分割為子欄位S1及S2之情況下，可在各子欄位中個別地(亦即，分別地)執行EGA。座標軸x1、y1係用於對準至子欄位S1中之左側的兩行，而座標軸x2、y2係用於子欄位S2以對準至右側行。
圖9類似於圖8，但是具有晶片放置之一不同的系統誤差，此需要將該重構晶圓100分割為允許在各子欄位之各行上使用子欄位EGA之三個子欄位S1至S3。子欄位S1中之座標軸x1、y1係用於對準至左側行，且子欄位S2中之座標軸x2、y2係用於對準至中心行，子欄位S3中之座標軸x3、y3係用於對準右側行。
類似於圖6至圖9之晶圓晶片圖經常用於判定達成期望重疊之最佳的晶圓分割。通常，可量測來自一晶圓群組(例如，來自一「批」晶圓)中之一單一晶圓的晶圓晶片圖以作為判定不同的子欄位S之數目及空間範圍的分割計算的基礎。晶圓晶片圖量測可使用一分別的度量衡工具離線進行，或可使用該微影術工具自身進行。
實例SEGA方法
在具有一重疊需要之一微影術程序中執行SEGA對準之一實例方法如下：
1)使用(例如)上文所述之方法提供或形成一或多個重構晶圓。
2)量測代表性數目的重構晶圓(例如，1至25個晶圓)上之晶片位置。對於各晶片，量測平均晶片位置及該晶片位置之晶圓至晶圓變量兩者。晶片位置可使用個別晶粒內之傳統的對準標記(諸如格狀類型結構)或藉由使用一機器視覺類型的系統來定位該晶粒內之可視特徵而量測。
3)計算平均的晶片位置誤差(亦即，實際晶片位置相對於對應的理想晶片位置的差異)且與該等晶片位置的變量比較。採用此兩個值之較大者。
4)在線性及非線性成分方面相對於一理想的笛卡爾網格模型化該等晶片位置誤差(或該變量，自步驟3其正是較大者)。
5)相對於該微影術程序之重疊需要比較該晶片位置誤差(或該變量)之非線性成分。
6)識別具有其等之小於該重疊需要之非線性晶片位置誤差成分(或變量)的兩個或兩個以上子欄位S。
7)在步驟6)中所識別之各自的子欄位S上執行SEGA(子欄位EGA)。
一旦在代表性數目的晶圓上執行該計算，然後可無需進一步分析而對生產(亦即，非樣品)晶圓執行該SEGA程序。
亦應注意的是，步驟7)之該SEGA可藉由使用傳統的對準標記或藉由使用一機器視覺系統來識別且定位晶粒中之特定特徵(例如，定位該晶粒之「左下角落」)而完成。
在一實例實施例中，至少部分使用一電腦實施以上方法，其中將晶片位置量測資料儲存在一電腦可讀媒體中，且一處理器執行必要的計算來識別該等區段(子欄位)且實施如本文所述之該SEGA方法。
熟習此項技術者將易於得知，在不脫離本揭示內容之精神及範疇下可對本揭示內容進行各種修改及變更。因此，意欲使本揭示內容涵蓋本揭示內容之修改及變更(假如該等修改及變更在隨附申請專利範圍及其等之等效物之範疇內)。
10．．．晶片(晶粒)
12．．．晶片接觸件
16．．．標記線
20．．．晶圓
30．．．封裝基板
32．．．封裝晶片
40．．．接觸墊
40T．．．穿透導通體
50．．．路徑選擇線
100．．．重構晶圓
102．．．載體
104．．．臨時載體
110．．．材料
圖1係一典型的積體裝置佈局之一晶圓上之晶片的一實例先前技術配置的一平面視圖；
圖2A及圖2B係一封裝晶片之各自的側視圖及俯視圖，該封裝晶片包含由一封裝基板(「封裝」)(具有在該封裝基板上所形成之大量接觸墊)支撐之一晶片；
圖3係包含配置在一載體上之封裝晶片的一規則配置的一實例重構晶圓之一平面視圖；
圖4A至圖4F繪示基本的扇出程序流程；
圖5A及圖5B繪示扇出晶圓級封裝之一先進形式，其中個別接觸墊被製成具有配置為一堆疊幾何之該等封裝晶片的穿透導通體；
圖6係繪示一類型系統誤差之一實例重構晶圓的一平面視圖，藉此晶片之中心行的位置相對於周圍行而位移；
圖7類似於圖6，且展示一單一的x-y座標系統，該單一的x-y座標系統將在一次執行全部晶片上之EGA中歸因於中心行偏移而並非有效的；
圖8類似於圖6，除了該重構晶圓被劃分為兩個子欄位，各子欄位具有其自身之x-y座標系統，其中在各自的子欄位之各子欄位中獨立地執行EGA；及
圖9類似於圖8，但是具有一不同的晶片放置誤差，該晶片放置誤差要求將該重構晶圓劃分為三個子欄位，各子欄位具有用於執行該等各自的子欄位內之EGA對準之其自身的x-y座標系統。
10．．．晶片(晶粒)
40T．．．穿透導通體
110．．．材料

Claims (20)

  1. 一種在具有一重疊需要之一微影術程序中執行對準的方法，該方法包括：提供至少一重構晶圓，該重構晶圓包含由一載體支撐且配置於不同位置的複數個晶片，其中該等晶片位置妨礙執行在該重疊需要內之整個晶圓上之該等晶片之一單一增強的全域對準；量測該至少一重構晶圓上之該等晶片位置；基於該等量測之晶片位置而識別該重構晶圓之兩個或兩個以上子欄位，其中可分別執行增強的全域對準以在該重疊需要內；及執行各自的該兩個或兩個以上子欄位內之分別的增強全域對準。
  2. 如請求項1之方法，其中該量測包括量測各晶片之一平均晶片位置及各晶片位置之一晶圓至晶圓變量。
  3. 如請求項2之方法，其中該識別包括：基於該等量測之平均晶片位置計算一平均晶片位置誤差；使用一理想的笛卡爾網格之線性及非線性成分模型化該平均晶片位置誤差與該變量之較大者；及比較該非線性成分與該重疊需要。
  4. 如請求項1之方法，其中該量測係在來自一共同群組之重構晶圓的一或多個重構晶圓上執行。
  5. 如請求項4之方法，其中一或多個重構晶圓係介於1與25個晶圓之間。
  6. 如請求項4之方法，其中該微影術程序包含晶圓級封裝。
  7. 一種在一微影術程序中對準放置在一重構晶圓上之若干晶片的方法，該方法包括：建立該重構晶圓上之兩個或兩個以上子欄位，其中晶片放置中之一給定的系統誤差及隨機誤差係於該重疊需要內；及執行各自的該兩個或兩個以上子欄位內之一或多個晶片之各自的兩次或兩次以上增強的全域對準。
  8. 如請求項7之方法，其進一步包括藉由執行一或多個樣品重構晶圓之晶片量測而建立該兩個或兩個以上子欄位之一尺寸及位置。
  9. 如請求項8之方法，其進一步包括：在非樣品重構晶圓上重複執行各自的該兩個或兩個以上子欄位之該兩次或兩次以上增強的全域對準。
  10. 如請求項7之方法，其進一步包括基於理想的晶片位置量測各晶片之一平均晶片位置及各晶片位置之一晶圓至晶圓變量。
  11. 如請求項10之方法，其中進一步包括：基於該等量測之平均晶片位置而計算一平均晶片位置誤差；使用一理想的笛卡爾網格之線性及非線性成分模型化該平均晶片位置誤差與該變量之較大者；及比較該非線性成分與該重疊需要，且藉由在該兩個或兩個以上子欄位之各子欄位內使該非線性成分與該重疊需要一致而建立該兩個或兩個以上子欄位。
  12. 如請求項11之方法，其中該量測係在來自一共同批晶圓之一或多個晶圓上執行。
  13. 如請求項12之方法，其中一或多個晶圓係介於1與25個晶圓之間。
  14. 如請求項7之方法，其中該微影術程序包含執行晶圓級扇出封裝。
  15. 一種在具有一重疊需要之一微影術程序中執行重構晶圓之對準的方法，該方法包括：形成一第一組多重重構晶圓，各重構晶圓具有一載體，該載體具有藉此可操作地支撐於不同位置的若干晶片，使得不可對於該第一組中之一給定重構晶圓上的該等晶片之全部執行一單一增強的全域對準；量測該等多重晶圓上之該等晶片位置；及基於該等量測之晶片位置而判定若干子欄位，於該等子欄位上可執行在該重疊需要內之增強的全域對準。
  16. 如請求項15之方法，其進一步包含：對於該第一組重構晶圓及具有與該第一組重構晶圓相同之一般晶片位置的一第二組多重重構晶圓之至少一者的各自子欄位執行個別增強的全域對準。
  17. 如請求項15之方法，其中該判定包含：計算平均晶片位置；基於該等計算的平均晶片位置而計算一平均晶片位置誤差；計算各晶片位置之一晶圓至晶圓變量；使用一理想的笛卡爾網格之線性及非線性成分模型化該平均晶片位置誤差與該晶圓至晶圓之晶片位置變量的較大者；及比較該非線性成分與該重疊需要。
  18. 如請求項17之方法，其中該等第一組及第二組重構晶圓係來自一共同批重構晶圓。
  19. 如請求項18之方法，其中該共同批晶圓包含多達25個晶圓。
  20. 如請求項15之方法，其中該微影術程序包含扇出晶圓級封裝。
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