TWI484564B - 半導體裝置及其製造方法 - Google Patents
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Description
本發明係有關於半導體裝置及其製造方法。
在最近幾十年來，使用矽基材的互補式金氧半導體(CMOS)技術在例如微處理器的數位電路中已佔有主要地位。然而，當臨界特徵尺寸接近22奈米或更小時，更進一步的尺寸微縮化其造成的效能優勢，似乎會受限於矽通道而被縮減。為了持續地提高效能，是使用例如砷化銦鎵(indium gallium arsenide;InGaAs)、銻砷化銦(indium arsenide antimonide;InAsSb)與鍺(germanium;Ge)的遷移率高的材料，取代矽作為通道材料。然而，這樣遷移率高的材料其結晶結構、晶格常數、熱膨脹係數與其他參數並不相容於矽。此不相容性會造成降低材料特性、裝置效能與電路良率的缺陷。
這裡說明兩種不同習知在晶格失配(lattice mismatch)系統的異質磊晶中減少缺陷密度的方法。一種方法是使用一般為三元或四元半導體的覆蓋薄膜或緩衝層。缺陷(特別是穿過差排(threading dislocation))會被捕捉或終止在緩衝層中的某些區域。另一種方法是捕捉或終止圖案化罩幕側壁上晶格失配所造成的缺陷，上述罩幕一般包含介電質。在此方法中，磊晶晶格失配的材料是成長至一厚度，而橫向地延伸在罩幕上。一般而言，在上述兩種方法中，穿過差排的密度會隨著離基底表面的距離愈遠而愈低。這種習知技術的缺點包括需要相當厚的緩衝層，而厚度一般是超過0.5μm至1μm，或者會在靠近表面的位置或當中留下密度相當高的穿過差排，而上述缺陷密度一般是介於105
cm-2
至106
個/cm2
，或更高。此厚度的緩衝層不相容於CMOS的平坦度與製程需求，且更不益於熱能的移除，特別是一般的CMOS微處理器需要消散超過100瓦特至300瓦特的熱能。此三元或四元材料的導熱係數(heat conductivity)一般比矽差一個數量級或更多。
習知技術還揭示在矽基底上異質磊晶(heteroepitaxial)成長晶格失配(lattice mismatched)、無差排(dislocation-free)的奈米線。此奈米線的高度一般介於5μm至10μm。舉例來說，雖然無差排的InAs奈米線能夠成長至150nm(T. Martensson等人，Advanced Materials 2007,19,1801-1806)，然而其一般是使用例如金或自組有機塗物(self-assembled organic coating)的成核模板(template)，成核在未圖案化的矽基底上，並成長至50nm。已有文獻報導閘極環繞線結構的奈米線金氧半導體場效電晶體(nanowire MOSFET)(Q.T. Do等人，“High Transconductance MISFET with a Single InAs Nanowire Channel,”Electron Device Letters,Vol. 28,No. 8,p. 682(2007)，以及C. Thelander等人“Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor with 50nm Wrap Gate,”Electron Device Letters,Vol. 29,No. 3,p. 206(2008))。而奈米線MOSFET的缺點是，其非平面的結構並不相容於標準的CMOS技術。
習知技術也揭示淺溝槽隔離(shallow trench isolation;STI)製程，其是在半導體裝置製程的前段、在形成電晶體之前進行。淺溝槽隔離製程的主要步驟包括在矽基材中蝕刻溝槽圖案；沉積例如二氧化矽的一或多個介電材料以填充溝槽；及使用例如化學機械研磨的技術移除多餘的介電質。
本發明提供一種半導體裝置的製造方法，包括：在一矽基底上定義一罩幕，該罩幕包括多數個穿過其中的奈米尺寸開口；在定義該罩幕之後，在該矽基底穿過該些罩幕開口而露出的表面部分建造實質上無缺陷的非矽半導體奈米島；在建造該些奈米島之後，在該些奈米島上沉積高介電常數閘極介電質；以及在沉積該高介電常數閘極介電質之後，在該些奈米島上架構電晶體。
本發明也提供一種半導體裝置，包括：一矽基底；一罩幕，設置在該矽基底的頂表面上，並包括多數個穿過其中的奈米尺寸開口；實質上無缺陷的非矽半導體奈米島，成長在該矽基底穿過該些罩幕開口而露出的頂表面部分；高介電常數閘極介電質，設置在該些奈米島上；以及電晶體，形成在該些奈米島上。
本發明還提供一種半導體裝置的製造方法，包括：在一矽基底上定義一罩幕，該罩幕包括多數個穿過其中的奈米尺寸開口；使用金屬有機化學氣相沉積法與氣相源分子束磊晶法中的至少一個方法，在該矽基底穿過該些罩幕開口而露出的表面進行實質上無缺陷的非矽半導體奈米島的選擇性的異質磊晶成長；在建造該些奈米島之後，藉由金屬有機化學氣相沉積法、原子層沉積法與分子束磊晶法中的至少一個方法，在該些奈米島上沉積高介電常數閘極介電質；以及在沉積該高介電常數閘極介電質之後，在該些奈米島上架構電晶體。
以下是透過圖示說明本發明的概念。要強調的是，圖中的各種元件並未畫成與工業標準規範相符的比例。實際上，為了清楚地描述本發明，各種元件的尺寸可任意地放大或縮小。
在此說明的實施例提供一種相容於CMOS需求的少缺陷(low-defect)或無缺陷(defect-free)的異質磊晶方法，其形成的結構包括、但不限於，有益於熱能的移除並有良好的平坦度，且相容於目前22奈米節點或低於22奈米節點的CMOS製造需求。詳細地說，在此說明的實施例是在矽基底上提供單晶材料的無差排異質磊晶奈米島(dislocation-free heteroepitaxial nano-island)。架構在奈米島上的電晶體相容於CMOS製造需求；詳細地說，上述結構是平坦的，薄的裝置層能益於熱能的移除，且需求的面積相同於如國際半導體技術藍圖(International Technology Roadmap for Semiconductors;ITRS)中所述的標準矽CMOS。此外，用來在矽基底上建造奈米島的罩幕也同時用來電性隔離各個裝置。
請參考第1圖，可包括例如介電質的硬罩幕100是用來在矽基底200(參考第2圖)上建造無差排、薄的異質磊晶、單晶的奈米島102，如參照第4圖的說明。奈米島102可解釋為只包含裝置功能需要的薄層厚度的終止奈米線。於一實施例中，奈米島102的總厚度不超過50nm。如第2圖中所示，奈米島102可根據裝置的需求而包括一些異質磊晶層。詳細地說，第2圖顯示單一個奈米島102的n型通道MOSFET層結構，其包括閘極氧化層202、小能隙通道層204、未摻雜的大能隙層206與p+型大能隙層208。每個奈米島102上可製得一或更多個電晶體，或者可將奈米島合併以形成較大的電晶體。奈米島102的尺寸相似於一般奈米線的剖面尺寸，且奈米島102尺寸的上限是取決於無差排成長的限制。
由於奈米線一般是以橫剖面為六角形(hexagonal)的結構成長，因此於一實施例中，用來促進無差排的成長的硬罩幕100包括六角形的開口(hexagonally-shaped opening)(因此也可稱之為“蜂巢孔(honeycomb)”)。矽基底200可更具有(111)表面方向，以促進無差排的成長。可設計硬罩幕100，讓使用奈米島架構之電晶體其需要的面積等於一特定節點的標準CMOS矽電晶體，如第3A圖與第3B圖所示。詳細地說，第3A圖顯示一實施例架構在奈米島302上的電晶體300。第3B圖顯示習知技術架構在一般的材料上，於此例子中，是形成在矽材料302'上的電晶體300'。在第3A圖中，區域304表示硬罩幕與隔離物。在第3B圖中，區域304'表示淺溝槽隔離結構與隔離物。每個電晶體300，300'分別包括閘極306、306'與歐姆接觸308、308'。從第3A圖與第3B圖的比較可發現，如上所述，電晶體300的面積實質上等於電晶體300'的面積。
第4圖顯示一實施例在基底上建造無差排、薄的異質磊晶、單晶的奈米島的方法流程圖。請參考第4圖，在步驟400中，罩幕是藉由例如熱氧化法、氧化沉積法及/或微影法定義在矽基底上。如參照第1圖所述的內容，在步驟400中定義的罩幕為硬罩幕。在步驟402中，藉由例如金屬有機化學氣相沉積法及/或氣相源分子束磊晶法，在露出的矽表面進行非矽半導體奈米島的選擇性的異質磊晶成長。在步驟404中，高介電常數閘極介電質是藉由例如金屬有機化學氣相沉積法、原子層沉積法及/或分子束磊晶法沉積。最後，在步驟406中，在奈米島上架構電晶體的閘極、側壁與歐姆接觸。
非矽通道材料，例如III-V族半導體與鍺(Ge)，可應用於超過22奈米世代的CMOS。一般此技術的的電晶體面積是小於20,000nm2
。第5圖顯示嵌入式微處理器(MPU)閘極尺寸(四個電晶體(4t))的歷史與預計的尺寸曲線圖。舉例來說，包括隔離結構的單一個電晶體，在16奈米節點與11奈米節點(節點在此是以嵌入式微處理器/特定應用積體電路第一層金屬1/2間距(MPU/ASIC metal 1(M1)pitch)定義)的預計尺寸為約20,000nm2
與約10,000nm2
，分別如圖中的點500與點501所示。此說明是假設電晶體單元包括隔離結構且佔有正方形面積時，電晶體單元的邊緣長度為140nm與100nm。要注意由於異質磊晶材料的奈米島是建造在隔離罩幕圖案中，因此上述奈米島仍是非常小的。目前已證實能在此尺寸的矽基底上形成無差排的InAs奈米線。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾。舉例來說，所述方法的各種步驟可以不同的順序或連續地執行，或與其他步驟合併、更分割成其他步驟或以其他步驟取代，或全部移除。另外，在說明書中的方法或其他部分所述的各種功能，可合併提供額外及/或其他的功能。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．罩幕
102．．．奈米島
200．．．矽基底
202．．．閘極氧化層
204．．．小能隙通道層
206．．．未摻雜的大能隙層
208．．．p+型大能隙層
300．．．電晶體
300'．．．電晶體
302．．．奈米島
302'．．．一般的矽材料
304．．．區域
304'．．．區域
306．．．閘極
306'．．．閘極
308．．．歐姆接觸
308'．．．歐姆接觸
第1圖顯示一實施例設置在矽基底上的硬罩幕與形成於硬罩幕中的奈米島。
第2圖顯示一實施例用來形成n型通道MOSFET之奈米島的磊晶層結構。
第3A圖顯示一實施例形成在奈米島上的電晶體。
第3B圖顯示習知技術形成在一般材料上的電晶體。
第4圖顯示一實施例在基底上形成無差排、薄的異質磊晶、單晶的奈米島的方法流程圖。
第5圖顯示各種邏輯閘極單元的歷史與預計尺寸的曲線圖。
100．．．罩幕
102．．．奈米島
Claims (14)
- 一種半導體裝置的製造方法，包括：在一矽基底上定義一罩幕，該罩幕包括多數個穿過其中的奈米尺寸開口，每一個該些奈米尺寸開口定義一溝槽(trench)，其延伸至且曝露出該矽基底的一表面；在定義該罩幕之後，在該矽基底露出的每一個表面上建造實質上無缺陷的非矽半導體奈米島於每一個溝槽之中，其中每一個該些非矽半導體奈米島包括一氧化層，其設置在建造有實質上無缺陷的非矽半導體奈米島之該溝槽之中；以及在建造該些奈米島之後，在該些奈米島上架構電晶體。
- 如申請專利範圍第1項所述的半導體裝置的製造方法，其中建造該些奈米島包括藉由金屬有機化學氣相沉積法進行該些非矽半導體奈米島的選擇性的異質磊晶成長。
- 如申請專利範圍第1項所述的半導體裝置的製造方法，其中建造該些奈米島包括藉由氣相源分子束磊晶法進行該些非矽半導體奈米島的選擇性的異質磊晶成長。
- 如申請專利範圍第1項所述的半導體裝置的製造方法，其中該些開口中的每一個是六角形。
- 一種半導體裝置，包括：一矽基底；一罩幕，設置在該矽基底的頂表面上，並包括多數 個穿過其中的奈米尺寸開口，每一個該些奈米尺寸開口定義一溝槽(trench)，其延伸至且曝露出該矽基底的頂表面；實質上無缺陷的非矽半導體奈米島，成長在該矽基底露出的每一個頂表面上且位於每一個溝槽之中，其中每一個該些非矽半導體奈米島包括一氧化層，其設置在建造有實質上無缺陷的非矽半導體奈米島之該溝槽之中；以及電晶體，形成在該些奈米島上。
- 如申請專利範圍第5項所述的半導體裝置，其中該些奈米島是藉由使用金屬有機化學氣相沉積法的選擇性異質磊晶成長。
- 如申請專利範圍第5項所述的半導體裝置，其中該些奈米島是藉由使用氣相源分子束磊晶法的選擇性異質磊晶成長。
- 如申請專利範圍第5項所述的半導體裝置，其中該些開口中的每一個是六角形。
- 如申請專利範圍第5項所述的半導體裝置，其中該奈米島的厚度小於或等於50nm。
- 如申請專利範圍第5項所述的半導體裝置，其中該矽基底具有(111)表面方向。
- 如申請專利範圍第5項所述的半導體裝置，其中該罩幕包括一硬罩幕。
- 一種半導體裝置的製造方法，包括：在一矽基底上定義一罩幕，該罩幕包括多數個穿過 其中的奈米尺寸開口，每一個該些奈米尺寸開口定義一溝槽(trench)，其延伸至且曝露出該矽基底的一表面；使用金屬有機化學氣相沉積法與氣相源分子束磊晶法中的至少一個方法，在該矽基底露出的每一個表面進行實質上無缺陷的非矽半導體奈米島的選擇性的異質磊晶成長於每一個溝槽中，其中每一個該些非矽半導體奈米島包括一氧化層，其設置在建造有實質上無缺陷的非矽半導體奈米島之該溝槽之中；以及在該些奈米島上架構電晶體。
- 如申請專利範圍第12項所述的半導體裝置的製造方法，其中架構該些電晶體包括設置閘極、側壁與歐姆接觸。
- 如申請專利範圍第12項所述的半導體裝置的製造方法，其中該些開口中的每一個是六角形。
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| JP2014225681A (ja) | 2014-12-04 |
| KR101345897B1 (ko) | 2013-12-30 |
| CN102024759A (zh) | 2011-04-20 |
| JP2011066410A (ja) | 2011-03-31 |
| US20110068368A1 (en) | 2011-03-24 |
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